1*b1763769SSeonGu Kang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*b1763769SSeonGu Kang/* 3*b1763769SSeonGu Kang * Axis ARTPEC-8 Grizzly board device tree source 4*b1763769SSeonGu Kang * 5*b1763769SSeonGu Kang * Copyright (c) 2025 Samsung Electronics Co., Ltd. 6*b1763769SSeonGu Kang * https://www.samsung.com 7*b1763769SSeonGu Kang * Copyright (c) 2025 Axis Communications AB. 8*b1763769SSeonGu Kang * https://www.axis.com 9*b1763769SSeonGu Kang */ 10*b1763769SSeonGu Kang 11*b1763769SSeonGu Kang/dts-v1/; 12*b1763769SSeonGu Kang#include "artpec8.dtsi" 13*b1763769SSeonGu Kang#include "artpec8-pinctrl.dtsi" 14*b1763769SSeonGu Kang#include <dt-bindings/gpio/gpio.h> 15*b1763769SSeonGu Kang/ { 16*b1763769SSeonGu Kang model = "ARTPEC-8 grizzly board"; 17*b1763769SSeonGu Kang compatible = "axis,artpec8-grizzly", "axis,artpec8"; 18*b1763769SSeonGu Kang 19*b1763769SSeonGu Kang aliases { 20*b1763769SSeonGu Kang serial0 = &serial_0; 21*b1763769SSeonGu Kang }; 22*b1763769SSeonGu Kang 23*b1763769SSeonGu Kang chosen { 24*b1763769SSeonGu Kang stdout-path = &serial_0; 25*b1763769SSeonGu Kang }; 26*b1763769SSeonGu Kang 27*b1763769SSeonGu Kang memory@80000000 { 28*b1763769SSeonGu Kang device_type = "memory"; 29*b1763769SSeonGu Kang reg = <0x0 0x80000000 0x0 0x80000000>; 30*b1763769SSeonGu Kang }; 31*b1763769SSeonGu Kang}; 32*b1763769SSeonGu Kang 33*b1763769SSeonGu Kang&osc_clk { 34*b1763769SSeonGu Kang clock-frequency = <50000000>; 35*b1763769SSeonGu Kang}; 36