1*44839e2aSDave Stevenson// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*44839e2aSDave Stevenson/dts-v1/; 3*44839e2aSDave Stevenson 4*44839e2aSDave Stevenson#include "bcm2712-rpi-5-b.dts" 5*44839e2aSDave Stevenson 6*44839e2aSDave Stevenson&gio_aon { 7*44839e2aSDave Stevenson brcm,gpio-bank-widths = <15 6>; 8*44839e2aSDave Stevenson 9*44839e2aSDave Stevenson gpio-line-names = 10*44839e2aSDave Stevenson "RP1_SDA", // AON_GPIO_00 11*44839e2aSDave Stevenson "RP1_SCL", // AON_GPIO_01 12*44839e2aSDave Stevenson "RP1_RUN", // AON_GPIO_02 13*44839e2aSDave Stevenson "SD_IOVDD_SEL", // AON_GPIO_03 14*44839e2aSDave Stevenson "SD_PWR_ON", // AON_GPIO_04 15*44839e2aSDave Stevenson "SD_CDET_N", // AON_GPIO_05 16*44839e2aSDave Stevenson "SD_FLG_N", // AON_GPIO_06 17*44839e2aSDave Stevenson "", // AON_GPIO_07 18*44839e2aSDave Stevenson "2712_WAKE", // AON_GPIO_08 19*44839e2aSDave Stevenson "2712_STAT_LED", // AON_GPIO_09 20*44839e2aSDave Stevenson "", // AON_GPIO_10 21*44839e2aSDave Stevenson "", // AON_GPIO_11 22*44839e2aSDave Stevenson "PMIC_INT", // AON_GPIO_12 23*44839e2aSDave Stevenson "UART_TX_FS", // AON_GPIO_13 24*44839e2aSDave Stevenson "UART_RX_FS", // AON_GPIO_14 25*44839e2aSDave Stevenson "", // AON_GPIO_15 26*44839e2aSDave Stevenson "", // AON_GPIO_16 27*44839e2aSDave Stevenson 28*44839e2aSDave Stevenson // Pad bank0 out to 32 entries 29*44839e2aSDave Stevenson "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", 30*44839e2aSDave Stevenson 31*44839e2aSDave Stevenson "HDMI0_SCL", // AON_SGPIO_00 32*44839e2aSDave Stevenson "HDMI0_SDA", // AON_SGPIO_01 33*44839e2aSDave Stevenson "HDMI1_SCL", // AON_SGPIO_02 34*44839e2aSDave Stevenson "HDMI1_SDA", // AON_SGPIO_03 35*44839e2aSDave Stevenson "PMIC_SCL", // AON_SGPIO_04 36*44839e2aSDave Stevenson "PMIC_SDA"; // AON_SGPIO_05 37*44839e2aSDave Stevenson}; 38