10806906bSKonrad Dybcio// SPDX-License-Identifier: GPL-2.0+ OR MIT 20806906bSKonrad Dybcio/* 30806906bSKonrad Dybcio * Apple S8000 "A9" (Samsung) SoC 40806906bSKonrad Dybcio * 50806906bSKonrad Dybcio * Other names: H8P, "Maui" 60806906bSKonrad Dybcio * 7*1fd51c73SNick Chan * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> 80806906bSKonrad Dybcio */ 90806906bSKonrad Dybcio 10ef7980d4SNick Chan#include "s800-0-3.dtsi" 110806906bSKonrad Dybcio 12*1fd51c73SNick Chan/ { 13*1fd51c73SNick Chan twister_opp: opp-table { 14*1fd51c73SNick Chan compatible = "operating-points-v2"; 15*1fd51c73SNick Chan 16*1fd51c73SNick Chan opp01 { 17*1fd51c73SNick Chan opp-hz = /bits/ 64 <300000000>; 18*1fd51c73SNick Chan opp-level = <1>; 19*1fd51c73SNick Chan clock-latency-ns = <650>; 20*1fd51c73SNick Chan }; 21*1fd51c73SNick Chan opp02 { 22*1fd51c73SNick Chan opp-hz = /bits/ 64 <396000000>; 23*1fd51c73SNick Chan opp-level = <2>; 24*1fd51c73SNick Chan clock-latency-ns = <75000>; 25*1fd51c73SNick Chan }; 26*1fd51c73SNick Chan opp03 { 27*1fd51c73SNick Chan opp-hz = /bits/ 64 <600000000>; 28*1fd51c73SNick Chan opp-level = <3>; 29*1fd51c73SNick Chan clock-latency-ns = <27000>; 30*1fd51c73SNick Chan }; 31*1fd51c73SNick Chan opp04 { 32*1fd51c73SNick Chan opp-hz = /bits/ 64 <912000000>; 33*1fd51c73SNick Chan opp-level = <4>; 34*1fd51c73SNick Chan clock-latency-ns = <32000>; 35*1fd51c73SNick Chan }; 36*1fd51c73SNick Chan opp05 { 37*1fd51c73SNick Chan opp-hz = /bits/ 64 <1200000000>; 38*1fd51c73SNick Chan opp-level = <5>; 39*1fd51c73SNick Chan clock-latency-ns = <35000>; 40*1fd51c73SNick Chan }; 41*1fd51c73SNick Chan opp06 { 42*1fd51c73SNick Chan opp-hz = /bits/ 64 <1512000000>; 43*1fd51c73SNick Chan opp-level = <6>; 44*1fd51c73SNick Chan clock-latency-ns = <45000>; 45*1fd51c73SNick Chan }; 46*1fd51c73SNick Chan opp07 { 47*1fd51c73SNick Chan opp-hz = /bits/ 64 <1800000000>; 48*1fd51c73SNick Chan opp-level = <7>; 49*1fd51c73SNick Chan clock-latency-ns = <58000>; 50*1fd51c73SNick Chan }; 51*1fd51c73SNick Chan#if 0 52*1fd51c73SNick Chan /* Not available until CPU deep sleep is implemented */ 53*1fd51c73SNick Chan opp08 { 54*1fd51c73SNick Chan opp-hz = /bits/ 64 <1844000000>; 55*1fd51c73SNick Chan opp-level = <8>; 56*1fd51c73SNick Chan clock-latency-ns = <58000>; 57*1fd51c73SNick Chan turbo-mode; 58*1fd51c73SNick Chan }; 59*1fd51c73SNick Chan#endif 60*1fd51c73SNick Chan }; 61*1fd51c73SNick Chan}; 62*1fd51c73SNick Chan 630806906bSKonrad Dybcio/* 640806906bSKonrad Dybcio * The A9 was made by two separate fabs on two different process 650806906bSKonrad Dybcio * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made 66ef7980d4SNick Chan * the S8003 (APL1022) on 16nm. There are some minor differences 67ef7980d4SNick Chan * such as timing in cpufreq state transistions. 680806906bSKonrad Dybcio */ 69