1*9e908d5fSNick Chan// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*9e908d5fSNick Chan/* 3*9e908d5fSNick Chan * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz 4*9e908d5fSNick Chan * 5*9e908d5fSNick Chan * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m 6*9e908d5fSNick Chan * 7*9e908d5fSNick Chan * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> 8*9e908d5fSNick Chan */ 9*9e908d5fSNick Chan 10*9e908d5fSNick Chan/ { 11*9e908d5fSNick Chan cyclone_opp: opp-table { 12*9e908d5fSNick Chan compatible = "operating-points-v2"; 13*9e908d5fSNick Chan 14*9e908d5fSNick Chan opp01 { 15*9e908d5fSNick Chan opp-hz = /bits/ 64 <300000000>; 16*9e908d5fSNick Chan opp-level = <1>; 17*9e908d5fSNick Chan clock-latency-ns = <15500>; 18*9e908d5fSNick Chan }; 19*9e908d5fSNick Chan opp02 { 20*9e908d5fSNick Chan opp-hz = /bits/ 64 <396000000>; 21*9e908d5fSNick Chan opp-level = <2>; 22*9e908d5fSNick Chan clock-latency-ns = <43000>; 23*9e908d5fSNick Chan }; 24*9e908d5fSNick Chan opp03 { 25*9e908d5fSNick Chan opp-hz = /bits/ 64 <600000000>; 26*9e908d5fSNick Chan opp-level = <3>; 27*9e908d5fSNick Chan clock-latency-ns = <26000>; 28*9e908d5fSNick Chan }; 29*9e908d5fSNick Chan opp04 { 30*9e908d5fSNick Chan opp-hz = /bits/ 64 <840000000>; 31*9e908d5fSNick Chan opp-level = <4>; 32*9e908d5fSNick Chan clock-latency-ns = <30000>; 33*9e908d5fSNick Chan }; 34*9e908d5fSNick Chan opp05 { 35*9e908d5fSNick Chan opp-hz = /bits/ 64 <1128000000>; 36*9e908d5fSNick Chan opp-level = <5>; 37*9e908d5fSNick Chan clock-latency-ns = <39500>; 38*9e908d5fSNick Chan }; 39*9e908d5fSNick Chan opp06 { 40*9e908d5fSNick Chan opp-hz = /bits/ 64 <1296000000>; 41*9e908d5fSNick Chan opp-level = <6>; 42*9e908d5fSNick Chan clock-latency-ns = <45500>; 43*9e908d5fSNick Chan }; 44*9e908d5fSNick Chan }; 45*9e908d5fSNick Chan}; 46