1*a702d4f0SJerome Brunet// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*a702d4f0SJerome Brunet/* 3*a702d4f0SJerome Brunet * Copyright (c) 2023 BayLibre, SAS. 4*a702d4f0SJerome Brunet * Author: Jerome Brunet <jbrunet@baylibre.com> 5*a702d4f0SJerome Brunet */ 6*a702d4f0SJerome Brunet 7*a702d4f0SJerome Brunet/dts-v1/; 8*a702d4f0SJerome Brunet 9*a702d4f0SJerome Brunet#include <dt-bindings/clock/g12a-clkc.h> 10*a702d4f0SJerome Brunet#include "meson-sm1.dtsi" 11*a702d4f0SJerome Brunet#include "meson-libretech-cottonwood.dtsi" 12*a702d4f0SJerome Brunet 13*a702d4f0SJerome Brunet/ { 14*a702d4f0SJerome Brunet compatible = "libretech,aml-s905d3-cc", "amlogic,sm1"; 15*a702d4f0SJerome Brunet model = "Libre Computer AML-S905D3-CC Solitude"; 16*a702d4f0SJerome Brunet 17*a702d4f0SJerome Brunet sound { 18*a702d4f0SJerome Brunet model = "LC-SOLITUDE"; 19*a702d4f0SJerome Brunet audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", 20*a702d4f0SJerome Brunet "TDMOUT_A IN 1", "FRDDR_B OUT 0", 21*a702d4f0SJerome Brunet "TDMOUT_A IN 2", "FRDDR_C OUT 0", 22*a702d4f0SJerome Brunet "TDM_A Playback", "TDMOUT_A OUT", 23*a702d4f0SJerome Brunet "TDMOUT_B IN 0", "FRDDR_A OUT 1", 24*a702d4f0SJerome Brunet "TDMOUT_B IN 1", "FRDDR_B OUT 1", 25*a702d4f0SJerome Brunet "TDMOUT_B IN 2", "FRDDR_C OUT 1", 26*a702d4f0SJerome Brunet "TDM_B Playback", "TDMOUT_B OUT", 27*a702d4f0SJerome Brunet "TDMOUT_C IN 0", "FRDDR_A OUT 2", 28*a702d4f0SJerome Brunet "TDMOUT_C IN 1", "FRDDR_B OUT 2", 29*a702d4f0SJerome Brunet "TDMOUT_C IN 2", "FRDDR_C OUT 2", 30*a702d4f0SJerome Brunet "TDM_C Playback", "TDMOUT_C OUT", 31*a702d4f0SJerome Brunet "TDMIN_A IN 0", "TDM_A Capture", 32*a702d4f0SJerome Brunet "TDMIN_B IN 0", "TDM_A Capture", 33*a702d4f0SJerome Brunet "TDMIN_C IN 0", "TDM_A Capture", 34*a702d4f0SJerome Brunet "TDMIN_A IN 13", "TDM_A Loopback", 35*a702d4f0SJerome Brunet "TDMIN_B IN 13", "TDM_A Loopback", 36*a702d4f0SJerome Brunet "TDMIN_C IN 13", "TDM_A Loopback", 37*a702d4f0SJerome Brunet "TDMIN_A IN 1", "TDM_B Capture", 38*a702d4f0SJerome Brunet "TDMIN_B IN 1", "TDM_B Capture", 39*a702d4f0SJerome Brunet "TDMIN_C IN 1", "TDM_B Capture", 40*a702d4f0SJerome Brunet "TDMIN_A IN 14", "TDM_B Loopback", 41*a702d4f0SJerome Brunet "TDMIN_B IN 14", "TDM_B Loopback", 42*a702d4f0SJerome Brunet "TDMIN_C IN 14", "TDM_B Loopback", 43*a702d4f0SJerome Brunet "TDMIN_A IN 2", "TDM_C Capture", 44*a702d4f0SJerome Brunet "TDMIN_B IN 2", "TDM_C Capture", 45*a702d4f0SJerome Brunet "TDMIN_C IN 2", "TDM_C Capture", 46*a702d4f0SJerome Brunet "TDMIN_A IN 15", "TDM_C Loopback", 47*a702d4f0SJerome Brunet "TDMIN_B IN 15", "TDM_C Loopback", 48*a702d4f0SJerome Brunet "TDMIN_C IN 15", "TDM_C Loopback", 49*a702d4f0SJerome Brunet "TODDR_A IN 0", "TDMIN_A OUT", 50*a702d4f0SJerome Brunet "TODDR_B IN 0", "TDMIN_A OUT", 51*a702d4f0SJerome Brunet "TODDR_C IN 0", "TDMIN_A OUT", 52*a702d4f0SJerome Brunet "TODDR_A IN 1", "TDMIN_B OUT", 53*a702d4f0SJerome Brunet "TODDR_B IN 1", "TDMIN_B OUT", 54*a702d4f0SJerome Brunet "TODDR_C IN 1", "TDMIN_B OUT", 55*a702d4f0SJerome Brunet "TODDR_A IN 2", "TDMIN_C OUT", 56*a702d4f0SJerome Brunet "TODDR_B IN 2", "TDMIN_C OUT", 57*a702d4f0SJerome Brunet "TODDR_C IN 2", "TDMIN_C OUT", 58*a702d4f0SJerome Brunet "Lineout", "ACODEC LOLP", 59*a702d4f0SJerome Brunet "Lineout", "ACODEC LORP"; 60*a702d4f0SJerome Brunet }; 61*a702d4f0SJerome Brunet}; 62*a702d4f0SJerome Brunet 63*a702d4f0SJerome Brunet&cpu0 { 64*a702d4f0SJerome Brunet cpu-supply = <&vddcpu_b>; 65*a702d4f0SJerome Brunet operating-points-v2 = <&cpu_opp_table>; 66*a702d4f0SJerome Brunet clocks = <&clkc CLKID_CPU_CLK>; 67*a702d4f0SJerome Brunet}; 68*a702d4f0SJerome Brunet 69*a702d4f0SJerome Brunet&cpu1 { 70*a702d4f0SJerome Brunet cpu-supply = <&vddcpu_b>; 71*a702d4f0SJerome Brunet operating-points-v2 = <&cpu_opp_table>; 72*a702d4f0SJerome Brunet clocks = <&clkc CLKID_CPU1_CLK>; 73*a702d4f0SJerome Brunet}; 74*a702d4f0SJerome Brunet 75*a702d4f0SJerome Brunet&cpu2 { 76*a702d4f0SJerome Brunet cpu-supply = <&vddcpu_b>; 77*a702d4f0SJerome Brunet operating-points-v2 = <&cpu_opp_table>; 78*a702d4f0SJerome Brunet clocks = <&clkc CLKID_CPU2_CLK>; 79*a702d4f0SJerome Brunet}; 80*a702d4f0SJerome Brunet 81*a702d4f0SJerome Brunet&cpu3 { 82*a702d4f0SJerome Brunet cpu-supply = <&vddcpu_b>; 83*a702d4f0SJerome Brunet operating-points-v2 = <&cpu_opp_table>; 84*a702d4f0SJerome Brunet clocks = <&clkc CLKID_CPU3_CLK>; 85*a702d4f0SJerome Brunet}; 86