xref: /linux/scripts/dtc/include-prefixes/arm64/amlogic/amlogic-s7.dtsi (revision 115e74a29b530d121891238e9551c4bcdf7b04b5)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2025 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>

/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x200>;
			enable-method = "psci";
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x300>;
			enable-method = "psci";
		};

	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@fff01000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xfff01000 0 0x1000>,
			      <0x0 0xfff02000 0 0x0100>;
			interrupts = <GIC_PPI 9 0xf04>;
		};

		apb: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x480000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;

			uart_b: serial@7a000 {
				compatible = "amlogic,s7-uart",
					     "amlogic,meson-s4-uart";
				reg = <0x0 0x7a000 0x0 0x18>;
				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&xtal>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};

			periphs_pinctrl: pinctrl@4000 {
				compatible = "amlogic,pinctrl-s7";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;

				gpioz: gpio@c0 {
					reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>;
				};

				gpiox: gpio@100 {
					reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>;
				};

				gpioh: gpio@140 {
					reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>;
				};

				gpiod: gpio@180 {
					reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>;
				};

				gpioe: gpio@1c0 {
					reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
				};

				gpioc: gpio@200 {
					reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>;
				};

				gpiob: gpio@240 {
					reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
				};

				test_n: gpio@2c0 {
					reg = <0 0x2c0 0 0x20>;
					reg-names = "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges =
						<&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
				};

				gpiocc: gpio@300 {
					reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>;
					reg-names = "gpio", "mux";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>;
				};
			};
		};
	};
};