xref: /linux/scripts/dtc/include-prefixes/arm64/amlogic/amlogic-a4-common.dtsi (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
16ef63301SXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
26ef63301SXianwei Zhao/*
36ef63301SXianwei Zhao * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
46ef63301SXianwei Zhao */
56ef63301SXianwei Zhao
66ef63301SXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h>
76ef63301SXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h>
86ef63301SXianwei Zhao#include <dt-bindings/gpio/gpio.h>
96ef63301SXianwei Zhao/ {
106ef63301SXianwei Zhao	timer {
116ef63301SXianwei Zhao		compatible = "arm,armv8-timer";
126ef63301SXianwei Zhao		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
136ef63301SXianwei Zhao			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
146ef63301SXianwei Zhao			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
156ef63301SXianwei Zhao			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
166ef63301SXianwei Zhao	};
176ef63301SXianwei Zhao
186ef63301SXianwei Zhao	psci {
196ef63301SXianwei Zhao		compatible = "arm,psci-1.0";
206ef63301SXianwei Zhao		method = "smc";
216ef63301SXianwei Zhao	};
226ef63301SXianwei Zhao
236ef63301SXianwei Zhao	xtal: xtal-clk {
246ef63301SXianwei Zhao		compatible = "fixed-clock";
256ef63301SXianwei Zhao		clock-frequency = <24000000>;
266ef63301SXianwei Zhao		clock-output-names = "xtal";
276ef63301SXianwei Zhao		#clock-cells = <0>;
286ef63301SXianwei Zhao	};
296ef63301SXianwei Zhao
306ef63301SXianwei Zhao	soc {
316ef63301SXianwei Zhao		compatible = "simple-bus";
326ef63301SXianwei Zhao		#address-cells = <2>;
336ef63301SXianwei Zhao		#size-cells = <2>;
346ef63301SXianwei Zhao		ranges;
356ef63301SXianwei Zhao
366ef63301SXianwei Zhao		gic: interrupt-controller@fff01000 {
376ef63301SXianwei Zhao			compatible = "arm,gic-400";
386ef63301SXianwei Zhao			reg = <0x0 0xfff01000 0 0x1000>,
396ef63301SXianwei Zhao			      <0x0 0xfff02000 0 0x2000>,
406ef63301SXianwei Zhao			      <0x0 0xfff04000 0 0x2000>,
416ef63301SXianwei Zhao			      <0x0 0xfff06000 0 0x2000>;
426ef63301SXianwei Zhao			#interrupt-cells = <3>;
436ef63301SXianwei Zhao			#address-cells = <0>;
446ef63301SXianwei Zhao			interrupt-controller;
456ef63301SXianwei Zhao			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
466ef63301SXianwei Zhao		};
476ef63301SXianwei Zhao
486ef63301SXianwei Zhao		apb: bus@fe000000 {
496ef63301SXianwei Zhao			compatible = "simple-bus";
506ef63301SXianwei Zhao			reg = <0x0 0xfe000000 0x0 0x480000>;
516ef63301SXianwei Zhao			#address-cells = <2>;
526ef63301SXianwei Zhao			#size-cells = <2>;
536ef63301SXianwei Zhao			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
546ef63301SXianwei Zhao
5548635ba6SHuqiang Qin			watchdog@2100 {
5648635ba6SHuqiang Qin				compatible = "amlogic,a4-wdt", "amlogic,t7-wdt";
5748635ba6SHuqiang Qin				reg = <0x0 0x2100 0x0 0x10>;
5848635ba6SHuqiang Qin				clocks = <&xtal>;
5948635ba6SHuqiang Qin			};
6048635ba6SHuqiang Qin
616ef63301SXianwei Zhao			uart_b: serial@7a000 {
626ef63301SXianwei Zhao				compatible = "amlogic,a4-uart",
636ef63301SXianwei Zhao					     "amlogic,meson-s4-uart";
646ef63301SXianwei Zhao				reg = <0x0 0x7a000 0x0 0x18>;
656ef63301SXianwei Zhao				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
666ef63301SXianwei Zhao				clocks = <&xtal>, <&xtal>, <&xtal>;
676ef63301SXianwei Zhao				clock-names = "xtal", "pclk", "baud";
686ef63301SXianwei Zhao				status = "disabled";
696ef63301SXianwei Zhao			};
70*b2d7fd0eSXianwei Zhao
71*b2d7fd0eSXianwei Zhao			sec_ao: ao-secure@10220 {
72*b2d7fd0eSXianwei Zhao				compatible = "amlogic,a4-ao-secure",
73*b2d7fd0eSXianwei Zhao					     "amlogic,meson-gx-ao-secure",
74*b2d7fd0eSXianwei Zhao					     "syscon";
75*b2d7fd0eSXianwei Zhao				reg = <0x0 0x10220 0x0 0x140>;
76*b2d7fd0eSXianwei Zhao				amlogic,has-chip-id;
77*b2d7fd0eSXianwei Zhao			};
786ef63301SXianwei Zhao		};
796ef63301SXianwei Zhao	};
806ef63301SXianwei Zhao};
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