xref: /linux/scripts/dtc/include-prefixes/arm64/altera/socfpga_stratix10.dtsi (revision 78cd6a9d8e154fe2ac5d2b912519e27545cfd13b)
1*78cd6a9dSDinh Nguyen/*
2*78cd6a9dSDinh Nguyen * Copyright Altera Corporation (C) 2015. All rights reserved.
3*78cd6a9dSDinh Nguyen *
4*78cd6a9dSDinh Nguyen * This program is free software; you can redistribute it and/or modify
5*78cd6a9dSDinh Nguyen * it under the terms and conditions of the GNU General Public License,
6*78cd6a9dSDinh Nguyen * version 2, as published by the Free Software Foundation.
7*78cd6a9dSDinh Nguyen *
8*78cd6a9dSDinh Nguyen * This program is distributed in the hope it will be useful, but WITHOUT
9*78cd6a9dSDinh Nguyen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10*78cd6a9dSDinh Nguyen * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11*78cd6a9dSDinh Nguyen * more details.
12*78cd6a9dSDinh Nguyen *
13*78cd6a9dSDinh Nguyen * You should have received a copy of the GNU General Public License along with
14*78cd6a9dSDinh Nguyen * this program.  If not, see <http://www.gnu.org/licenses/>.
15*78cd6a9dSDinh Nguyen */
16*78cd6a9dSDinh Nguyen
17*78cd6a9dSDinh Nguyen/dts-v1/;
18*78cd6a9dSDinh Nguyen
19*78cd6a9dSDinh Nguyen/ {
20*78cd6a9dSDinh Nguyen	compatible = "altr,socfpga-stratix10";
21*78cd6a9dSDinh Nguyen	#address-cells = <2>;
22*78cd6a9dSDinh Nguyen	#size-cells = <2>;
23*78cd6a9dSDinh Nguyen
24*78cd6a9dSDinh Nguyen	cpus {
25*78cd6a9dSDinh Nguyen		#address-cells = <1>;
26*78cd6a9dSDinh Nguyen		#size-cells = <0>;
27*78cd6a9dSDinh Nguyen
28*78cd6a9dSDinh Nguyen		cpu0: cpu@0 {
29*78cd6a9dSDinh Nguyen			compatible = "arm,cortex-a53", "arm,armv8";
30*78cd6a9dSDinh Nguyen			device_type = "cpu";
31*78cd6a9dSDinh Nguyen			enable-method = "psci";
32*78cd6a9dSDinh Nguyen			reg = <0x0>;
33*78cd6a9dSDinh Nguyen		};
34*78cd6a9dSDinh Nguyen
35*78cd6a9dSDinh Nguyen		cpu1: cpu@1 {
36*78cd6a9dSDinh Nguyen			compatible = "arm,cortex-a53", "arm,armv8";
37*78cd6a9dSDinh Nguyen			device_type = "cpu";
38*78cd6a9dSDinh Nguyen			enable-method = "psci";
39*78cd6a9dSDinh Nguyen			reg = <0x1>;
40*78cd6a9dSDinh Nguyen		};
41*78cd6a9dSDinh Nguyen
42*78cd6a9dSDinh Nguyen		cpu2: cpu@2 {
43*78cd6a9dSDinh Nguyen			compatible = "arm,cortex-a53", "arm,armv8";
44*78cd6a9dSDinh Nguyen			device_type = "cpu";
45*78cd6a9dSDinh Nguyen			enable-method = "psci";
46*78cd6a9dSDinh Nguyen			reg = <0x2>;
47*78cd6a9dSDinh Nguyen		};
48*78cd6a9dSDinh Nguyen
49*78cd6a9dSDinh Nguyen		cpu3: cpu@3 {
50*78cd6a9dSDinh Nguyen			compatible = "arm,cortex-a53", "arm,armv8";
51*78cd6a9dSDinh Nguyen			device_type = "cpu";
52*78cd6a9dSDinh Nguyen			enable-method = "psci";
53*78cd6a9dSDinh Nguyen			reg = <0x3>;
54*78cd6a9dSDinh Nguyen		};
55*78cd6a9dSDinh Nguyen	};
56*78cd6a9dSDinh Nguyen
57*78cd6a9dSDinh Nguyen	pmu {
58*78cd6a9dSDinh Nguyen		compatible = "arm,armv8-pmuv3";
59*78cd6a9dSDinh Nguyen		interrupts = <0 120 8>,
60*78cd6a9dSDinh Nguyen			     <0 121 8>,
61*78cd6a9dSDinh Nguyen			     <0 122 8>,
62*78cd6a9dSDinh Nguyen			     <0 123 8>;
63*78cd6a9dSDinh Nguyen		interrupt-affinity = <&cpu0>,
64*78cd6a9dSDinh Nguyen				     <&cpu1>,
65*78cd6a9dSDinh Nguyen				     <&cpu2>,
66*78cd6a9dSDinh Nguyen				     <&cpu3>;
67*78cd6a9dSDinh Nguyen	};
68*78cd6a9dSDinh Nguyen
69*78cd6a9dSDinh Nguyen	psci {
70*78cd6a9dSDinh Nguyen		compatible = "arm,psci-0.2";
71*78cd6a9dSDinh Nguyen		method = "smc";
72*78cd6a9dSDinh Nguyen	};
73*78cd6a9dSDinh Nguyen
74*78cd6a9dSDinh Nguyen	intc: intc@fffc1000 {
75*78cd6a9dSDinh Nguyen		compatible = "arm,gic-400", "arm,cortex-a15-gic";
76*78cd6a9dSDinh Nguyen		#interrupt-cells = <3>;
77*78cd6a9dSDinh Nguyen		interrupt-controller;
78*78cd6a9dSDinh Nguyen		reg = <0x0 0xfffc1000 0x1000>,
79*78cd6a9dSDinh Nguyen		      <0x0 0xfffc2000 0x2000>,
80*78cd6a9dSDinh Nguyen		      <0x0 0xfffc4000 0x2000>,
81*78cd6a9dSDinh Nguyen		      <0x0 0xfffc6000 0x2000>;
82*78cd6a9dSDinh Nguyen	};
83*78cd6a9dSDinh Nguyen
84*78cd6a9dSDinh Nguyen	soc {
85*78cd6a9dSDinh Nguyen		#address-cells = <1>;
86*78cd6a9dSDinh Nguyen		#size-cells = <1>;
87*78cd6a9dSDinh Nguyen		compatible = "simple-bus";
88*78cd6a9dSDinh Nguyen		device_type = "soc";
89*78cd6a9dSDinh Nguyen		interrupt-parent = <&intc>;
90*78cd6a9dSDinh Nguyen		ranges = <0 0 0 0xffffffff>;
91*78cd6a9dSDinh Nguyen
92*78cd6a9dSDinh Nguyen		clkmgr@ffd1000 {
93*78cd6a9dSDinh Nguyen			compatible = "altr,clk-mgr";
94*78cd6a9dSDinh Nguyen			reg = <0xffd10000 0x1000>;
95*78cd6a9dSDinh Nguyen		};
96*78cd6a9dSDinh Nguyen
97*78cd6a9dSDinh Nguyen		gmac0: ethernet@ff800000 {
98*78cd6a9dSDinh Nguyen			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
99*78cd6a9dSDinh Nguyen			reg = <0xff800000 0x2000>;
100*78cd6a9dSDinh Nguyen			interrupts = <0 90 4>;
101*78cd6a9dSDinh Nguyen			interrupt-names = "macirq";
102*78cd6a9dSDinh Nguyen			mac-address = [00 00 00 00 00 00];
103*78cd6a9dSDinh Nguyen			status = "disabled";
104*78cd6a9dSDinh Nguyen		};
105*78cd6a9dSDinh Nguyen
106*78cd6a9dSDinh Nguyen		gmac1: ethernet@ff802000 {
107*78cd6a9dSDinh Nguyen			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
108*78cd6a9dSDinh Nguyen			reg = <0xff802000 0x2000>;
109*78cd6a9dSDinh Nguyen			interrupts = <0 91 4>;
110*78cd6a9dSDinh Nguyen			interrupt-names = "macirq";
111*78cd6a9dSDinh Nguyen			mac-address = [00 00 00 00 00 00];
112*78cd6a9dSDinh Nguyen			status = "disabled";
113*78cd6a9dSDinh Nguyen		};
114*78cd6a9dSDinh Nguyen
115*78cd6a9dSDinh Nguyen		gmac2: ethernet@ff804000 {
116*78cd6a9dSDinh Nguyen			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
117*78cd6a9dSDinh Nguyen			reg = <0xff804000 0x2000>;
118*78cd6a9dSDinh Nguyen			interrupts = <0 92 4>;
119*78cd6a9dSDinh Nguyen			interrupt-names = "macirq";
120*78cd6a9dSDinh Nguyen			mac-address = [00 00 00 00 00 00];
121*78cd6a9dSDinh Nguyen			status = "disabled";
122*78cd6a9dSDinh Nguyen		};
123*78cd6a9dSDinh Nguyen
124*78cd6a9dSDinh Nguyen		gpio0: gpio@ffc03200 {
125*78cd6a9dSDinh Nguyen			#address-cells = <1>;
126*78cd6a9dSDinh Nguyen			#size-cells = <0>;
127*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-gpio";
128*78cd6a9dSDinh Nguyen			reg = <0xffc03200 0x100>;
129*78cd6a9dSDinh Nguyen			status = "disabled";
130*78cd6a9dSDinh Nguyen
131*78cd6a9dSDinh Nguyen			porta: gpio-controller@0 {
132*78cd6a9dSDinh Nguyen				compatible = "snps,dw-apb-gpio-port";
133*78cd6a9dSDinh Nguyen				gpio-controller;
134*78cd6a9dSDinh Nguyen				#gpio-cells = <2>;
135*78cd6a9dSDinh Nguyen				snps,nr-gpios = <24>;
136*78cd6a9dSDinh Nguyen				reg = <0>;
137*78cd6a9dSDinh Nguyen				interrupt-controller;
138*78cd6a9dSDinh Nguyen				#interrupt-cells = <2>;
139*78cd6a9dSDinh Nguyen				interrupts = <0 110 4>;
140*78cd6a9dSDinh Nguyen			};
141*78cd6a9dSDinh Nguyen		};
142*78cd6a9dSDinh Nguyen
143*78cd6a9dSDinh Nguyen		gpio1: gpio@ffc03300 {
144*78cd6a9dSDinh Nguyen			#address-cells = <1>;
145*78cd6a9dSDinh Nguyen			#size-cells = <0>;
146*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-gpio";
147*78cd6a9dSDinh Nguyen			reg = <0xffc03300 0x100>;
148*78cd6a9dSDinh Nguyen			status = "disabled";
149*78cd6a9dSDinh Nguyen
150*78cd6a9dSDinh Nguyen			portb: gpio-controller@0 {
151*78cd6a9dSDinh Nguyen				compatible = "snps,dw-apb-gpio-port";
152*78cd6a9dSDinh Nguyen				gpio-controller;
153*78cd6a9dSDinh Nguyen				#gpio-cells = <2>;
154*78cd6a9dSDinh Nguyen				snps,nr-gpios = <24>;
155*78cd6a9dSDinh Nguyen				reg = <0>;
156*78cd6a9dSDinh Nguyen				interrupt-controller;
157*78cd6a9dSDinh Nguyen				#interrupt-cells = <2>;
158*78cd6a9dSDinh Nguyen				interrupts = <0 110 4>;
159*78cd6a9dSDinh Nguyen			};
160*78cd6a9dSDinh Nguyen		};
161*78cd6a9dSDinh Nguyen
162*78cd6a9dSDinh Nguyen		i2c0: i2c@ffc02800 {
163*78cd6a9dSDinh Nguyen			#address-cells = <1>;
164*78cd6a9dSDinh Nguyen			#size-cells = <0>;
165*78cd6a9dSDinh Nguyen			compatible = "snps,designware-i2c";
166*78cd6a9dSDinh Nguyen			reg = <0xffc02800 0x100>;
167*78cd6a9dSDinh Nguyen			interrupts = <0 103 4>;
168*78cd6a9dSDinh Nguyen			status = "disabled";
169*78cd6a9dSDinh Nguyen		};
170*78cd6a9dSDinh Nguyen
171*78cd6a9dSDinh Nguyen		i2c1: i2c@ffc02900 {
172*78cd6a9dSDinh Nguyen			#address-cells = <1>;
173*78cd6a9dSDinh Nguyen			#size-cells = <0>;
174*78cd6a9dSDinh Nguyen			compatible = "snps,designware-i2c";
175*78cd6a9dSDinh Nguyen			reg = <0xffc02900 0x100>;
176*78cd6a9dSDinh Nguyen			interrupts = <0 104 4>;
177*78cd6a9dSDinh Nguyen			status = "disabled";
178*78cd6a9dSDinh Nguyen		};
179*78cd6a9dSDinh Nguyen
180*78cd6a9dSDinh Nguyen		i2c2: i2c@ffc02a00 {
181*78cd6a9dSDinh Nguyen			#address-cells = <1>;
182*78cd6a9dSDinh Nguyen			#size-cells = <0>;
183*78cd6a9dSDinh Nguyen			compatible = "snps,designware-i2c";
184*78cd6a9dSDinh Nguyen			reg = <0xffc02a00 0x100>;
185*78cd6a9dSDinh Nguyen			interrupts = <0 105 4>;
186*78cd6a9dSDinh Nguyen			status = "disabled";
187*78cd6a9dSDinh Nguyen		};
188*78cd6a9dSDinh Nguyen
189*78cd6a9dSDinh Nguyen		i2c3: i2c@ffc02b00 {
190*78cd6a9dSDinh Nguyen			#address-cells = <1>;
191*78cd6a9dSDinh Nguyen			#size-cells = <0>;
192*78cd6a9dSDinh Nguyen			compatible = "snps,designware-i2c";
193*78cd6a9dSDinh Nguyen			reg = <0xffc02b00 0x100>;
194*78cd6a9dSDinh Nguyen			interrupts = <0 106 4>;
195*78cd6a9dSDinh Nguyen			status = "disabled";
196*78cd6a9dSDinh Nguyen		};
197*78cd6a9dSDinh Nguyen
198*78cd6a9dSDinh Nguyen		i2c4: i2c@ffc02c00 {
199*78cd6a9dSDinh Nguyen			#address-cells = <1>;
200*78cd6a9dSDinh Nguyen			#size-cells = <0>;
201*78cd6a9dSDinh Nguyen			compatible = "snps,designware-i2c";
202*78cd6a9dSDinh Nguyen			reg = <0xffc02c00 0x100>;
203*78cd6a9dSDinh Nguyen			interrupts = <0 107 4>;
204*78cd6a9dSDinh Nguyen			status = "disabled";
205*78cd6a9dSDinh Nguyen		};
206*78cd6a9dSDinh Nguyen
207*78cd6a9dSDinh Nguyen		mmc: dwmmc0@ff808000 {
208*78cd6a9dSDinh Nguyen			#address-cells = <1>;
209*78cd6a9dSDinh Nguyen			#size-cells = <0>;
210*78cd6a9dSDinh Nguyen			compatible = "altr,socfpga-dw-mshc";
211*78cd6a9dSDinh Nguyen			reg = <0xff808000 0x1000>;
212*78cd6a9dSDinh Nguyen			interrupts = <0 96 4>;
213*78cd6a9dSDinh Nguyen			fifo-depth = <0x400>;
214*78cd6a9dSDinh Nguyen			status = "disabled";
215*78cd6a9dSDinh Nguyen		};
216*78cd6a9dSDinh Nguyen
217*78cd6a9dSDinh Nguyen		ocram: sram@ffe00000 {
218*78cd6a9dSDinh Nguyen			compatible = "mmio-sram";
219*78cd6a9dSDinh Nguyen			reg = <0xffe00000 0x100000>;
220*78cd6a9dSDinh Nguyen		};
221*78cd6a9dSDinh Nguyen
222*78cd6a9dSDinh Nguyen		rst: rstmgr@ffd11000 {
223*78cd6a9dSDinh Nguyen			#reset-cells = <1>;
224*78cd6a9dSDinh Nguyen			compatible = "altr,rst-mgr";
225*78cd6a9dSDinh Nguyen			reg = <0xffd11000 0x1000>;
226*78cd6a9dSDinh Nguyen		};
227*78cd6a9dSDinh Nguyen
228*78cd6a9dSDinh Nguyen		spi0: spi@ffda4000 {
229*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-ssi";
230*78cd6a9dSDinh Nguyen			#address-cells = <1>;
231*78cd6a9dSDinh Nguyen			#size-cells = <0>;
232*78cd6a9dSDinh Nguyen			reg = <0xffda4000 0x1000>;
233*78cd6a9dSDinh Nguyen			interrupts = <0 101 4>;
234*78cd6a9dSDinh Nguyen			num-chipselect = <4>;
235*78cd6a9dSDinh Nguyen			bus-num = <0>;
236*78cd6a9dSDinh Nguyen			status = "disabled";
237*78cd6a9dSDinh Nguyen		};
238*78cd6a9dSDinh Nguyen
239*78cd6a9dSDinh Nguyen		spi1: spi@ffda5000 {
240*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-ssi";
241*78cd6a9dSDinh Nguyen			#address-cells = <1>;
242*78cd6a9dSDinh Nguyen			#size-cells = <0>;
243*78cd6a9dSDinh Nguyen			reg = <0xffda5000 0x1000>;
244*78cd6a9dSDinh Nguyen			interrupts = <0 102 4>;
245*78cd6a9dSDinh Nguyen			num-chipselect = <4>;
246*78cd6a9dSDinh Nguyen			bus-num = <0>;
247*78cd6a9dSDinh Nguyen			status = "disabled";
248*78cd6a9dSDinh Nguyen		};
249*78cd6a9dSDinh Nguyen
250*78cd6a9dSDinh Nguyen		sysmgr: sysmgr@ffd12000 {
251*78cd6a9dSDinh Nguyen			compatible = "altr,sys-mgr", "syscon";
252*78cd6a9dSDinh Nguyen			reg = <0xffd12000 0x1000>;
253*78cd6a9dSDinh Nguyen		};
254*78cd6a9dSDinh Nguyen
255*78cd6a9dSDinh Nguyen		/* Local timer */
256*78cd6a9dSDinh Nguyen		timer {
257*78cd6a9dSDinh Nguyen			compatible = "arm,armv8-timer";
258*78cd6a9dSDinh Nguyen			interrupts = <1 13 0xf01>,
259*78cd6a9dSDinh Nguyen				     <1 14 0xf01>,
260*78cd6a9dSDinh Nguyen				     <1 11 0xf01>,
261*78cd6a9dSDinh Nguyen				     <1 10 0xf01>;
262*78cd6a9dSDinh Nguyen		};
263*78cd6a9dSDinh Nguyen
264*78cd6a9dSDinh Nguyen		timer0: timer0@ffc03000 {
265*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-timer";
266*78cd6a9dSDinh Nguyen			interrupts = <0 113 4>;
267*78cd6a9dSDinh Nguyen			reg = <0xffc03000 0x100>;
268*78cd6a9dSDinh Nguyen		};
269*78cd6a9dSDinh Nguyen
270*78cd6a9dSDinh Nguyen		timer1: timer1@ffc03100 {
271*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-timer";
272*78cd6a9dSDinh Nguyen			interrupts = <0 114 4>;
273*78cd6a9dSDinh Nguyen			reg = <0xffc03100 0x100>;
274*78cd6a9dSDinh Nguyen		};
275*78cd6a9dSDinh Nguyen
276*78cd6a9dSDinh Nguyen		timer2: timer2@ffd00000 {
277*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-timer";
278*78cd6a9dSDinh Nguyen			interrupts = <0 115 4>;
279*78cd6a9dSDinh Nguyen			reg = <0xffd00000 0x100>;
280*78cd6a9dSDinh Nguyen		};
281*78cd6a9dSDinh Nguyen
282*78cd6a9dSDinh Nguyen		timer3: timer3@ffd00100 {
283*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-timer";
284*78cd6a9dSDinh Nguyen			interrupts = <0 116 4>;
285*78cd6a9dSDinh Nguyen			reg = <0xffd00100 0x100>;
286*78cd6a9dSDinh Nguyen		};
287*78cd6a9dSDinh Nguyen
288*78cd6a9dSDinh Nguyen		uart0: serial0@ffc02000 {
289*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-uart";
290*78cd6a9dSDinh Nguyen			reg = <0xffc02000 0x100>;
291*78cd6a9dSDinh Nguyen			interrupts = <0 108 4>;
292*78cd6a9dSDinh Nguyen			reg-shift = <2>;
293*78cd6a9dSDinh Nguyen			reg-io-width = <4>;
294*78cd6a9dSDinh Nguyen			status = "disabled";
295*78cd6a9dSDinh Nguyen		};
296*78cd6a9dSDinh Nguyen
297*78cd6a9dSDinh Nguyen		uart1: serial1@ffc02100 {
298*78cd6a9dSDinh Nguyen			compatible = "snps,dw-apb-uart";
299*78cd6a9dSDinh Nguyen			reg = <0xffc02100 0x100>;
300*78cd6a9dSDinh Nguyen			interrupts = <0 109 4>;
301*78cd6a9dSDinh Nguyen			reg-shift = <2>;
302*78cd6a9dSDinh Nguyen			reg-io-width = <4>;
303*78cd6a9dSDinh Nguyen			status = "disabled";
304*78cd6a9dSDinh Nguyen		};
305*78cd6a9dSDinh Nguyen
306*78cd6a9dSDinh Nguyen		usbphy0: usbphy@0 {
307*78cd6a9dSDinh Nguyen			#phy-cells = <0>;
308*78cd6a9dSDinh Nguyen			compatible = "usb-nop-xceiv";
309*78cd6a9dSDinh Nguyen			status = "okay";
310*78cd6a9dSDinh Nguyen		};
311*78cd6a9dSDinh Nguyen
312*78cd6a9dSDinh Nguyen		usb0: usb@ffb00000 {
313*78cd6a9dSDinh Nguyen			compatible = "snps,dwc2";
314*78cd6a9dSDinh Nguyen			reg = <0xffb00000 0x40000>;
315*78cd6a9dSDinh Nguyen			interrupts = <0 93 4>;
316*78cd6a9dSDinh Nguyen			phys = <&usbphy0>;
317*78cd6a9dSDinh Nguyen			phy-names = "usb2-phy";
318*78cd6a9dSDinh Nguyen			status = "disabled";
319*78cd6a9dSDinh Nguyen		};
320*78cd6a9dSDinh Nguyen
321*78cd6a9dSDinh Nguyen		usb1: usb@ffb40000 {
322*78cd6a9dSDinh Nguyen			compatible = "snps,dwc2";
323*78cd6a9dSDinh Nguyen			reg = <0xffb40000 0x40000>;
324*78cd6a9dSDinh Nguyen			interrupts = <0 94 4>;
325*78cd6a9dSDinh Nguyen			phys = <&usbphy0>;
326*78cd6a9dSDinh Nguyen			phy-names = "usb2-phy";
327*78cd6a9dSDinh Nguyen			status = "disabled";
328*78cd6a9dSDinh Nguyen		};
329*78cd6a9dSDinh Nguyen
330*78cd6a9dSDinh Nguyen		watchdog0: watchdog@ffd00200 {
331*78cd6a9dSDinh Nguyen			compatible = "snps,dw-wdt";
332*78cd6a9dSDinh Nguyen			reg = <0xffd00200 0x100>;
333*78cd6a9dSDinh Nguyen			interrupts = <0 117 4>;
334*78cd6a9dSDinh Nguyen			status = "disabled";
335*78cd6a9dSDinh Nguyen		};
336*78cd6a9dSDinh Nguyen
337*78cd6a9dSDinh Nguyen		watchdog1: watchdog@ffd00300 {
338*78cd6a9dSDinh Nguyen			compatible = "snps,dw-wdt";
339*78cd6a9dSDinh Nguyen			reg = <0xffd00300 0x100>;
340*78cd6a9dSDinh Nguyen			interrupts = <0 118 4>;
341*78cd6a9dSDinh Nguyen			status = "disabled";
342*78cd6a9dSDinh Nguyen		};
343*78cd6a9dSDinh Nguyen
344*78cd6a9dSDinh Nguyen		watchdog2: watchdog@ffd00400 {
345*78cd6a9dSDinh Nguyen			compatible = "snps,dw-wdt";
346*78cd6a9dSDinh Nguyen			reg = <0xffd00400 0x100>;
347*78cd6a9dSDinh Nguyen			interrupts = <0 125 4>;
348*78cd6a9dSDinh Nguyen			status = "disabled";
349*78cd6a9dSDinh Nguyen		};
350*78cd6a9dSDinh Nguyen
351*78cd6a9dSDinh Nguyen		watchdog3: watchdog@ffd00500 {
352*78cd6a9dSDinh Nguyen			compatible = "snps,dw-wdt";
353*78cd6a9dSDinh Nguyen			reg = <0xffd00500 0x100>;
354*78cd6a9dSDinh Nguyen			interrupts = <0 126 4>;
355*78cd6a9dSDinh Nguyen			status = "disabled";
356*78cd6a9dSDinh Nguyen		};
357*78cd6a9dSDinh Nguyen	};
358*78cd6a9dSDinh Nguyen};
359