xref: /linux/scripts/dtc/include-prefixes/arm/ti/omap/omap36xx.dtsi (revision c771600c6af14749609b49565ffb4cac2959710d)
1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only
2724ba675SRob Herring/*
3724ba675SRob Herring * Device Tree Source for OMAP3 SoC
4724ba675SRob Herring *
5724ba675SRob Herring * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6724ba675SRob Herring */
7724ba675SRob Herring
8724ba675SRob Herring#include <dt-bindings/bus/ti-sysc.h>
9724ba675SRob Herring#include <dt-bindings/media/omap3-isp.h>
10724ba675SRob Herring
11724ba675SRob Herring#include "omap3.dtsi"
12724ba675SRob Herring
13724ba675SRob Herring/ {
14724ba675SRob Herring	aliases {
15724ba675SRob Herring		serial3 = &uart4;
16724ba675SRob Herring	};
17724ba675SRob Herring
18724ba675SRob Herring	cpus {
19724ba675SRob Herring		/* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
20724ba675SRob Herring		cpu: cpu@0 {
21724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
22724ba675SRob Herring
23724ba675SRob Herring			vbb-supply = <&abb_mpu_iva>;
24724ba675SRob Herring			clock-latency = <300000>; /* From omap-cpufreq driver */
25724ba675SRob Herring			#cooling-cells = <2>;
26724ba675SRob Herring		};
27724ba675SRob Herring	};
28724ba675SRob Herring
29724ba675SRob Herring	cpu0_opp_table: opp-table {
30724ba675SRob Herring		compatible = "operating-points-v2-ti-cpu";
31724ba675SRob Herring		syscon = <&scm_conf>;
32724ba675SRob Herring
335821d766SNishanth Menon		opp-50-300000000 {
345821d766SNishanth Menon			/* OPP50 */
35724ba675SRob Herring			opp-hz = /bits/ 64 <300000000>;
36724ba675SRob Herring			/*
37724ba675SRob Herring			 * we currently only select the max voltage from table
38724ba675SRob Herring			 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
39724ba675SRob Herring			 * Format is:	cpu0-supply:	<target min max>
40724ba675SRob Herring			 *		vbb-supply:	<target min max>
41724ba675SRob Herring			 */
42724ba675SRob Herring			opp-microvolt = <1012500 1012500 1012500>,
43724ba675SRob Herring					 <1012500 1012500 1012500>;
44724ba675SRob Herring			/*
45724ba675SRob Herring			 * first value is silicon revision bit mask
46724ba675SRob Herring			 * second one is "speed binned" bit mask
47724ba675SRob Herring			 */
48724ba675SRob Herring			opp-supported-hw = <0xffffffff 3>;
49724ba675SRob Herring			opp-suspend;
50724ba675SRob Herring		};
51724ba675SRob Herring
525821d766SNishanth Menon		opp-100-600000000 {
535821d766SNishanth Menon			/* OPP100 */
54724ba675SRob Herring			opp-hz = /bits/ 64 <600000000>;
55724ba675SRob Herring			opp-microvolt = <1200000 1200000 1200000>,
56724ba675SRob Herring					 <1200000 1200000 1200000>;
57724ba675SRob Herring			opp-supported-hw = <0xffffffff 3>;
58724ba675SRob Herring		};
59724ba675SRob Herring
605821d766SNishanth Menon		opp-130-800000000 {
615821d766SNishanth Menon			/* OPP130 */
62724ba675SRob Herring			opp-hz = /bits/ 64 <800000000>;
63724ba675SRob Herring			opp-microvolt = <1325000 1325000 1325000>,
64724ba675SRob Herring					 <1325000 1325000 1325000>;
65724ba675SRob Herring			opp-supported-hw = <0xffffffff 3>;
66724ba675SRob Herring		};
67724ba675SRob Herring
685821d766SNishanth Menon		opp-1000000000 {
695821d766SNishanth Menon			/* OPP1G */
70724ba675SRob Herring			opp-hz = /bits/ 64 <1000000000>;
71724ba675SRob Herring			opp-microvolt = <1375000 1375000 1375000>,
72724ba675SRob Herring					 <1375000 1375000 1375000>;
73724ba675SRob Herring			/* only on am/dm37x with speed-binned bit set */
74724ba675SRob Herring			opp-supported-hw = <0xffffffff 2>;
75*96a64e97SAndreas Kemnade			turbo-mode;
76724ba675SRob Herring		};
77724ba675SRob Herring	};
78724ba675SRob Herring
79bb29eb38SNishanth Menon	opp_supply_mpu_iva: opp-supply {
80724ba675SRob Herring		compatible = "ti,omap-opp-supply";
81724ba675SRob Herring		ti,absolute-max-voltage-uv = <1375000>;
82724ba675SRob Herring	};
83724ba675SRob Herring
84724ba675SRob Herring	ocp@68000000 {
85724ba675SRob Herring		uart4: serial@49042000 {
86724ba675SRob Herring			compatible = "ti,omap3-uart";
87724ba675SRob Herring			reg = <0x49042000 0x400>;
88724ba675SRob Herring			interrupts = <80>;
89724ba675SRob Herring			dmas = <&sdma 81 &sdma 82>;
90724ba675SRob Herring			dma-names = "tx", "rx";
91724ba675SRob Herring			ti,hwmods = "uart4";
92724ba675SRob Herring			clock-frequency = <48000000>;
93724ba675SRob Herring		};
94724ba675SRob Herring
95724ba675SRob Herring		abb_mpu_iva: regulator-abb-mpu {
96724ba675SRob Herring			compatible = "ti,abb-v1";
97724ba675SRob Herring			regulator-name = "abb_mpu_iva";
98724ba675SRob Herring			#address-cells = <0>;
99724ba675SRob Herring			#size-cells = <0>;
100724ba675SRob Herring			reg = <0x483072f0 0x8>, <0x48306818 0x4>;
101724ba675SRob Herring			reg-names = "base-address", "int-address";
102724ba675SRob Herring			ti,tranxdone-status-mask = <0x4000000>;
103724ba675SRob Herring			clocks = <&sys_ck>;
104724ba675SRob Herring			ti,settling-time = <30>;
105724ba675SRob Herring			ti,clock-cycles = <8>;
106724ba675SRob Herring			ti,abb_info = <
107724ba675SRob Herring			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
108724ba675SRob Herring			1012500		0	0	0	0	0
109724ba675SRob Herring			1200000		0	0	0	0	0
110724ba675SRob Herring			1325000		0	0	0	0	0
111724ba675SRob Herring			1375000		1	0	0	0	0
112724ba675SRob Herring			>;
113724ba675SRob Herring		};
114724ba675SRob Herring
115724ba675SRob Herring		omap3_pmx_core2: pinmux@480025a0 {
116724ba675SRob Herring			compatible = "ti,omap3-padconf", "pinctrl-single";
117724ba675SRob Herring			reg = <0x480025a0 0x5c>;
118724ba675SRob Herring			#address-cells = <1>;
119724ba675SRob Herring			#size-cells = <0>;
120724ba675SRob Herring			#pinctrl-cells = <1>;
121724ba675SRob Herring			#interrupt-cells = <1>;
122724ba675SRob Herring			interrupt-controller;
123724ba675SRob Herring			pinctrl-single,register-width = <16>;
124724ba675SRob Herring			pinctrl-single,function-mask = <0xff1f>;
125724ba675SRob Herring		};
126724ba675SRob Herring
127724ba675SRob Herring		isp: isp@480bc000 {
128724ba675SRob Herring			compatible = "ti,omap3-isp";
129724ba675SRob Herring			reg = <0x480bc000 0x12fc
130724ba675SRob Herring			       0x480bd800 0x0600>;
131724ba675SRob Herring			interrupts = <24>;
132724ba675SRob Herring			iommus = <&mmu_isp>;
133724ba675SRob Herring			syscon = <&scm_conf 0x2f0>;
134724ba675SRob Herring			ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
135724ba675SRob Herring			#clock-cells = <1>;
136724ba675SRob Herring			ports {
137724ba675SRob Herring				#address-cells = <1>;
138724ba675SRob Herring				#size-cells = <0>;
139724ba675SRob Herring			};
140724ba675SRob Herring		};
141724ba675SRob Herring
142724ba675SRob Herring		bandgap: bandgap@48002524 {
143724ba675SRob Herring			reg = <0x48002524 0x4>;
144724ba675SRob Herring			compatible = "ti,omap36xx-bandgap";
145724ba675SRob Herring			#thermal-sensor-cells = <0>;
146724ba675SRob Herring		};
147724ba675SRob Herring
148724ba675SRob Herring		target-module@480cb000 {
149724ba675SRob Herring			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
150724ba675SRob Herring			ti,hwmods = "smartreflex_core";
151724ba675SRob Herring			reg = <0x480cb038 0x4>;
152724ba675SRob Herring			reg-names = "sysc";
153724ba675SRob Herring			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
154724ba675SRob Herring			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
155724ba675SRob Herring					<SYSC_IDLE_NO>,
156724ba675SRob Herring					<SYSC_IDLE_SMART>;
157724ba675SRob Herring			clocks = <&sr2_fck>;
158724ba675SRob Herring			clock-names = "fck";
159724ba675SRob Herring			#address-cells = <1>;
160724ba675SRob Herring			#size-cells = <1>;
161724ba675SRob Herring			ranges = <0 0x480cb000 0x001000>;
162724ba675SRob Herring
163724ba675SRob Herring			smartreflex_core: smartreflex@0 {
164724ba675SRob Herring				compatible = "ti,omap3-smartreflex-core";
165724ba675SRob Herring				reg = <0 0x400>;
166724ba675SRob Herring				interrupts = <19>;
167724ba675SRob Herring			};
168724ba675SRob Herring		};
169724ba675SRob Herring
170724ba675SRob Herring		target-module@480c9000 {
171724ba675SRob Herring			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
172724ba675SRob Herring			ti,hwmods = "smartreflex_mpu_iva";
173724ba675SRob Herring			reg = <0x480c9038 0x4>;
174724ba675SRob Herring			reg-names = "sysc";
175724ba675SRob Herring			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
176724ba675SRob Herring			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
177724ba675SRob Herring					<SYSC_IDLE_NO>,
178724ba675SRob Herring					<SYSC_IDLE_SMART>;
179724ba675SRob Herring			clocks = <&sr1_fck>;
180724ba675SRob Herring			clock-names = "fck";
181724ba675SRob Herring			#address-cells = <1>;
182724ba675SRob Herring			#size-cells = <1>;
183724ba675SRob Herring			ranges = <0 0x480c9000 0x001000>;
184724ba675SRob Herring
185724ba675SRob Herring
186724ba675SRob Herring			smartreflex_mpu_iva: smartreflex@480c9000 {
187724ba675SRob Herring				compatible = "ti,omap3-smartreflex-mpu-iva";
188724ba675SRob Herring				reg = <0 0x400>;
189724ba675SRob Herring				interrupts = <18>;
190724ba675SRob Herring			};
191724ba675SRob Herring		};
192724ba675SRob Herring
193724ba675SRob Herring		/*
194724ba675SRob Herring		 * Note that the sysconfig register layout is a subset of the
195724ba675SRob Herring		 * "ti,sysc-omap4" type register with just sidle and midle bits
196724ba675SRob Herring		 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
197724ba675SRob Herring		 */
198724ba675SRob Herring		sgx_module: target-module@50000000 {
199724ba675SRob Herring			compatible = "ti,sysc-omap4", "ti,sysc";
200724ba675SRob Herring			reg = <0x5000fe00 0x4>,
201724ba675SRob Herring			      <0x5000fe10 0x4>;
202724ba675SRob Herring			reg-names = "rev", "sysc";
203724ba675SRob Herring			ti,sysc-midle = <SYSC_IDLE_FORCE>,
204724ba675SRob Herring					<SYSC_IDLE_NO>,
205724ba675SRob Herring					<SYSC_IDLE_SMART>;
206724ba675SRob Herring			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
207724ba675SRob Herring					<SYSC_IDLE_NO>,
208724ba675SRob Herring					<SYSC_IDLE_SMART>;
209724ba675SRob Herring			clocks = <&sgx_fck>, <&sgx_ick>;
210724ba675SRob Herring			clock-names = "fck", "ick";
211724ba675SRob Herring			#address-cells = <1>;
212724ba675SRob Herring			#size-cells = <1>;
213724ba675SRob Herring			ranges = <0 0x50000000 0x2000000>;
214724ba675SRob Herring
21570f028ffSAndrew Davis			gpu@0 {
21670f028ffSAndrew Davis				compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
21770f028ffSAndrew Davis				reg = <0x0 0x2000000>; /* 32MB */
21870f028ffSAndrew Davis				interrupts = <21>;
21970f028ffSAndrew Davis			};
220724ba675SRob Herring		};
221724ba675SRob Herring	};
222724ba675SRob Herring
223724ba675SRob Herring	thermal_zones: thermal-zones {
224724ba675SRob Herring		#include "omap3-cpu-thermal.dtsi"
225724ba675SRob Herring	};
226724ba675SRob Herring};
227724ba675SRob Herring
228724ba675SRob Herring&sdma {
229724ba675SRob Herring	compatible = "ti,omap3630-sdma", "ti,omap-sdma";
230724ba675SRob Herring};
231724ba675SRob Herring
232724ba675SRob Herring/* OMAP3630 needs dss_96m_fck for VENC */
233724ba675SRob Herring&venc {
234724ba675SRob Herring	clocks = <&dss_tv_fck>, <&dss_96m_fck>;
235724ba675SRob Herring	clock-names = "fck", "tv_dac_clk";
236724ba675SRob Herring};
237724ba675SRob Herring
238724ba675SRob Herring&ssi {
239724ba675SRob Herring	status = "okay";
240724ba675SRob Herring
241724ba675SRob Herring	clocks = <&ssi_ssr_fck>,
242724ba675SRob Herring		 <&ssi_sst_fck>,
243724ba675SRob Herring		 <&ssi_ick>;
244724ba675SRob Herring	clock-names = "ssi_ssr_fck",
245724ba675SRob Herring		      "ssi_sst_fck",
246724ba675SRob Herring		      "ssi_ick";
247724ba675SRob Herring};
248724ba675SRob Herring
249724ba675SRob Herring&usb_otg_target {
250724ba675SRob Herring	clocks = <&hsotgusb_ick_3430es2>;
251724ba675SRob Herring};
252724ba675SRob Herring
253724ba675SRob Herring/include/ "omap34xx-omap36xx-clocks.dtsi"
254724ba675SRob Herring/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
255724ba675SRob Herring/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
256724ba675SRob Herring/include/ "omap36xx-clocks.dtsi"
257