1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Keystone 2 Lamarr EVM device tree 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ 6*724ba675SRob Herring */ 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring 9*724ba675SRob Herring#include "keystone.dtsi" 10*724ba675SRob Herring#include "keystone-k2l.dtsi" 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; 14*724ba675SRob Herring model = "Texas Instruments Keystone 2 Lamarr EVM"; 15*724ba675SRob Herring 16*724ba675SRob Herring reserved-memory { 17*724ba675SRob Herring #address-cells = <2>; 18*724ba675SRob Herring #size-cells = <2>; 19*724ba675SRob Herring ranges; 20*724ba675SRob Herring 21*724ba675SRob Herring dsp_common_memory: dsp-common-memory@81f800000 { 22*724ba675SRob Herring compatible = "shared-dma-pool"; 23*724ba675SRob Herring reg = <0x00000008 0x1f800000 0x00000000 0x800000>; 24*724ba675SRob Herring reusable; 25*724ba675SRob Herring status = "okay"; 26*724ba675SRob Herring }; 27*724ba675SRob Herring }; 28*724ba675SRob Herring}; 29*724ba675SRob Herring 30*724ba675SRob Herring&soc0 { 31*724ba675SRob Herring clocks { 32*724ba675SRob Herring refclksys: refclksys { 33*724ba675SRob Herring #clock-cells = <0>; 34*724ba675SRob Herring compatible = "fixed-clock"; 35*724ba675SRob Herring clock-frequency = <122880000>; 36*724ba675SRob Herring clock-output-names = "refclk-sys"; 37*724ba675SRob Herring }; 38*724ba675SRob Herring }; 39*724ba675SRob Herring}; 40*724ba675SRob Herring 41*724ba675SRob Herring&usb_phy { 42*724ba675SRob Herring status = "okay"; 43*724ba675SRob Herring}; 44*724ba675SRob Herring 45*724ba675SRob Herring&keystone_usb0 { 46*724ba675SRob Herring status = "okay"; 47*724ba675SRob Herring}; 48*724ba675SRob Herring 49*724ba675SRob Herring&usb0 { 50*724ba675SRob Herring dr_mode = "host"; 51*724ba675SRob Herring}; 52*724ba675SRob Herring 53*724ba675SRob Herring&i2c0 { 54*724ba675SRob Herring eeprom@50 { 55*724ba675SRob Herring compatible = "atmel,24c1024"; 56*724ba675SRob Herring reg = <0x50>; 57*724ba675SRob Herring }; 58*724ba675SRob Herring}; 59*724ba675SRob Herring 60*724ba675SRob Herring&aemif { 61*724ba675SRob Herring cs0 { 62*724ba675SRob Herring #address-cells = <2>; 63*724ba675SRob Herring #size-cells = <1>; 64*724ba675SRob Herring clock-ranges; 65*724ba675SRob Herring ranges; 66*724ba675SRob Herring 67*724ba675SRob Herring ti,cs-chipselect = <0>; 68*724ba675SRob Herring /* all timings in nanoseconds */ 69*724ba675SRob Herring ti,cs-min-turnaround-ns = <12>; 70*724ba675SRob Herring ti,cs-read-hold-ns = <6>; 71*724ba675SRob Herring ti,cs-read-strobe-ns = <23>; 72*724ba675SRob Herring ti,cs-read-setup-ns = <9>; 73*724ba675SRob Herring ti,cs-write-hold-ns = <8>; 74*724ba675SRob Herring ti,cs-write-strobe-ns = <23>; 75*724ba675SRob Herring ti,cs-write-setup-ns = <8>; 76*724ba675SRob Herring 77*724ba675SRob Herring nand@0,0 { 78*724ba675SRob Herring compatible = "ti,keystone-nand","ti,davinci-nand"; 79*724ba675SRob Herring #address-cells = <1>; 80*724ba675SRob Herring #size-cells = <1>; 81*724ba675SRob Herring reg = <0 0 0x4000000 82*724ba675SRob Herring 1 0 0x0000100>; 83*724ba675SRob Herring 84*724ba675SRob Herring ti,davinci-chipselect = <0>; 85*724ba675SRob Herring ti,davinci-mask-ale = <0x2000>; 86*724ba675SRob Herring ti,davinci-mask-cle = <0x4000>; 87*724ba675SRob Herring ti,davinci-mask-chipsel = <0>; 88*724ba675SRob Herring nand-ecc-mode = "hw"; 89*724ba675SRob Herring ti,davinci-ecc-bits = <4>; 90*724ba675SRob Herring nand-on-flash-bbt; 91*724ba675SRob Herring 92*724ba675SRob Herring partition@0 { 93*724ba675SRob Herring label = "u-boot"; 94*724ba675SRob Herring reg = <0x0 0x100000>; 95*724ba675SRob Herring read-only; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring partition@100000 { 99*724ba675SRob Herring label = "params"; 100*724ba675SRob Herring reg = <0x100000 0x80000>; 101*724ba675SRob Herring read-only; 102*724ba675SRob Herring }; 103*724ba675SRob Herring 104*724ba675SRob Herring partition@180000 { 105*724ba675SRob Herring label = "ubifs"; 106*724ba675SRob Herring reg = <0x180000 0x7fe80000>; 107*724ba675SRob Herring }; 108*724ba675SRob Herring }; 109*724ba675SRob Herring }; 110*724ba675SRob Herring}; 111*724ba675SRob Herring 112*724ba675SRob Herring&spi0 { 113*724ba675SRob Herring nor_flash: flash@0 { 114*724ba675SRob Herring #address-cells = <1>; 115*724ba675SRob Herring #size-cells = <1>; 116*724ba675SRob Herring compatible = "micron,n25q128a11", "jedec,spi-nor"; 117*724ba675SRob Herring spi-max-frequency = <54000000>; 118*724ba675SRob Herring m25p,fast-read; 119*724ba675SRob Herring reg = <0>; 120*724ba675SRob Herring 121*724ba675SRob Herring partition@0 { 122*724ba675SRob Herring label = "u-boot-spl"; 123*724ba675SRob Herring reg = <0x0 0x80000>; 124*724ba675SRob Herring read-only; 125*724ba675SRob Herring }; 126*724ba675SRob Herring 127*724ba675SRob Herring partition@1 { 128*724ba675SRob Herring label = "misc"; 129*724ba675SRob Herring reg = <0x80000 0xf80000>; 130*724ba675SRob Herring }; 131*724ba675SRob Herring }; 132*724ba675SRob Herring}; 133*724ba675SRob Herring 134*724ba675SRob Herring&mdio { 135*724ba675SRob Herring status = "okay"; 136*724ba675SRob Herring ethphy0: ethernet-phy@0 { 137*724ba675SRob Herring compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; 138*724ba675SRob Herring reg = <0>; 139*724ba675SRob Herring }; 140*724ba675SRob Herring 141*724ba675SRob Herring ethphy1: ethernet-phy@1 { 142*724ba675SRob Herring compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; 143*724ba675SRob Herring reg = <1>; 144*724ba675SRob Herring }; 145*724ba675SRob Herring}; 146*724ba675SRob Herring 147*724ba675SRob Herring&dsp0 { 148*724ba675SRob Herring memory-region = <&dsp_common_memory>; 149*724ba675SRob Herring status = "okay"; 150*724ba675SRob Herring}; 151*724ba675SRob Herring 152*724ba675SRob Herring&dsp1 { 153*724ba675SRob Herring memory-region = <&dsp_common_memory>; 154*724ba675SRob Herring status = "okay"; 155*724ba675SRob Herring}; 156*724ba675SRob Herring 157*724ba675SRob Herring&dsp2 { 158*724ba675SRob Herring memory-region = <&dsp_common_memory>; 159*724ba675SRob Herring status = "okay"; 160*724ba675SRob Herring}; 161*724ba675SRob Herring 162*724ba675SRob Herring&dsp3 { 163*724ba675SRob Herring memory-region = <&dsp_common_memory>; 164*724ba675SRob Herring status = "okay"; 165*724ba675SRob Herring}; 166