1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Keystone 2 Edison soc device tree 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/reset/ti-syscon.h> 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring compatible = "ti,k2e", "ti,keystone"; 12*724ba675SRob Herring model = "Texas Instruments Keystone 2 Edison SoC"; 13*724ba675SRob Herring 14*724ba675SRob Herring cpus { 15*724ba675SRob Herring #address-cells = <1>; 16*724ba675SRob Herring #size-cells = <0>; 17*724ba675SRob Herring 18*724ba675SRob Herring interrupt-parent = <&gic>; 19*724ba675SRob Herring 20*724ba675SRob Herring cpu@0 { 21*724ba675SRob Herring compatible = "arm,cortex-a15"; 22*724ba675SRob Herring device_type = "cpu"; 23*724ba675SRob Herring reg = <0>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring cpu@1 { 27*724ba675SRob Herring compatible = "arm,cortex-a15"; 28*724ba675SRob Herring device_type = "cpu"; 29*724ba675SRob Herring reg = <1>; 30*724ba675SRob Herring }; 31*724ba675SRob Herring 32*724ba675SRob Herring cpu@2 { 33*724ba675SRob Herring compatible = "arm,cortex-a15"; 34*724ba675SRob Herring device_type = "cpu"; 35*724ba675SRob Herring reg = <2>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring 38*724ba675SRob Herring cpu@3 { 39*724ba675SRob Herring compatible = "arm,cortex-a15"; 40*724ba675SRob Herring device_type = "cpu"; 41*724ba675SRob Herring reg = <3>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring aliases { 46*724ba675SRob Herring rproc0 = &dsp0; 47*724ba675SRob Herring }; 48*724ba675SRob Herring}; 49*724ba675SRob Herring 50*724ba675SRob Herring&soc0 { 51*724ba675SRob Herring /include/ "keystone-k2e-clocks.dtsi" 52*724ba675SRob Herring 53*724ba675SRob Herring usb: usb@2680000 { 54*724ba675SRob Herring interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 55*724ba675SRob Herring usb@2690000 { 56*724ba675SRob Herring interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 57*724ba675SRob Herring }; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring usb1_phy: usb_phy@2620750 { 61*724ba675SRob Herring compatible = "ti,keystone-usbphy"; 62*724ba675SRob Herring #address-cells = <1>; 63*724ba675SRob Herring #size-cells = <1>; 64*724ba675SRob Herring reg = <0x2620750 24>; 65*724ba675SRob Herring status = "disabled"; 66*724ba675SRob Herring }; 67*724ba675SRob Herring 68*724ba675SRob Herring keystone_usb1: usb@25000000 { 69*724ba675SRob Herring compatible = "ti,keystone-dwc3"; 70*724ba675SRob Herring #address-cells = <1>; 71*724ba675SRob Herring #size-cells = <1>; 72*724ba675SRob Herring reg = <0x25000000 0x10000>; 73*724ba675SRob Herring clocks = <&clkusb1>; 74*724ba675SRob Herring clock-names = "usb"; 75*724ba675SRob Herring interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; 76*724ba675SRob Herring ranges; 77*724ba675SRob Herring dma-coherent; 78*724ba675SRob Herring dma-ranges; 79*724ba675SRob Herring status = "disabled"; 80*724ba675SRob Herring 81*724ba675SRob Herring usb1: usb@25010000 { 82*724ba675SRob Herring compatible = "snps,dwc3"; 83*724ba675SRob Herring reg = <0x25010000 0x70000>; 84*724ba675SRob Herring interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; 85*724ba675SRob Herring usb-phy = <&usb1_phy>, <&usb1_phy>; 86*724ba675SRob Herring }; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring msm_ram: sram@c000000 { 90*724ba675SRob Herring compatible = "mmio-sram"; 91*724ba675SRob Herring reg = <0x0c000000 0x200000>; 92*724ba675SRob Herring ranges = <0x0 0x0c000000 0x200000>; 93*724ba675SRob Herring #address-cells = <1>; 94*724ba675SRob Herring #size-cells = <1>; 95*724ba675SRob Herring 96*724ba675SRob Herring bm-sram@1f0000 { 97*724ba675SRob Herring reg = <0x001f0000 0x8000>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring psc: power-sleep-controller@2350000 { 102*724ba675SRob Herring pscrst: reset-controller { 103*724ba675SRob Herring compatible = "ti,k2e-pscrst", "ti,syscon-reset"; 104*724ba675SRob Herring #reset-cells = <1>; 105*724ba675SRob Herring 106*724ba675SRob Herring ti,reset-bits = < 107*724ba675SRob Herring 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ 108*724ba675SRob Herring >; 109*724ba675SRob Herring }; 110*724ba675SRob Herring }; 111*724ba675SRob Herring 112*724ba675SRob Herring devctrl: device-state-control@2620000 { 113*724ba675SRob Herring dspgpio0: keystone_dsp_gpio@240 { 114*724ba675SRob Herring compatible = "ti,keystone-dsp-gpio"; 115*724ba675SRob Herring reg = <0x240 0x4>; 116*724ba675SRob Herring gpio-controller; 117*724ba675SRob Herring #gpio-cells = <2>; 118*724ba675SRob Herring gpio,syscon-dev = <&devctrl 0x240>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring }; 121*724ba675SRob Herring 122*724ba675SRob Herring dsp0: dsp@10800000 { 123*724ba675SRob Herring compatible = "ti,k2e-dsp"; 124*724ba675SRob Herring reg = <0x10800000 0x00080000>, 125*724ba675SRob Herring <0x10e00000 0x00008000>, 126*724ba675SRob Herring <0x10f00000 0x00008000>; 127*724ba675SRob Herring reg-names = "l2sram", "l1pram", "l1dram"; 128*724ba675SRob Herring clocks = <&clkgem0>; 129*724ba675SRob Herring ti,syscon-dev = <&devctrl 0x844>; 130*724ba675SRob Herring resets = <&pscrst 0>; 131*724ba675SRob Herring interrupt-parent = <&kirq0>; 132*724ba675SRob Herring interrupts = <0 8>; 133*724ba675SRob Herring interrupt-names = "vring", "exception"; 134*724ba675SRob Herring kick-gpios = <&dspgpio0 27 0>; 135*724ba675SRob Herring status = "disabled"; 136*724ba675SRob Herring }; 137*724ba675SRob Herring 138*724ba675SRob Herring pcie1: pcie@21020000 { 139*724ba675SRob Herring compatible = "ti,keystone-pcie","snps,dw-pcie"; 140*724ba675SRob Herring clocks = <&clkpcie1>; 141*724ba675SRob Herring clock-names = "pcie"; 142*724ba675SRob Herring #address-cells = <3>; 143*724ba675SRob Herring #size-cells = <2>; 144*724ba675SRob Herring reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; 145*724ba675SRob Herring ranges = <0x82000000 0 0x60000000 0x60000000 146*724ba675SRob Herring 0 0x10000000>; 147*724ba675SRob Herring 148*724ba675SRob Herring status = "disabled"; 149*724ba675SRob Herring device_type = "pci"; 150*724ba675SRob Herring num-lanes = <2>; 151*724ba675SRob Herring bus-range = <0x00 0xff>; 152*724ba675SRob Herring 153*724ba675SRob Herring /* error interrupt */ 154*724ba675SRob Herring interrupts = <GIC_SPI 385 IRQ_TYPE_EDGE_RISING>; 155*724ba675SRob Herring #interrupt-cells = <1>; 156*724ba675SRob Herring interrupt-map-mask = <0 0 0 7>; 157*724ba675SRob Herring interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ 158*724ba675SRob Herring <0 0 0 2 &pcie_intc1 1>, /* INT B */ 159*724ba675SRob Herring <0 0 0 3 &pcie_intc1 2>, /* INT C */ 160*724ba675SRob Herring <0 0 0 4 &pcie_intc1 3>; /* INT D */ 161*724ba675SRob Herring 162*724ba675SRob Herring pcie_msi_intc1: msi-interrupt-controller { 163*724ba675SRob Herring interrupt-controller; 164*724ba675SRob Herring #interrupt-cells = <1>; 165*724ba675SRob Herring interrupt-parent = <&gic>; 166*724ba675SRob Herring interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 167*724ba675SRob Herring <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 168*724ba675SRob Herring <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>, 169*724ba675SRob Herring <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>, 170*724ba675SRob Herring <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>, 171*724ba675SRob Herring <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>, 172*724ba675SRob Herring <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>, 173*724ba675SRob Herring <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>; 174*724ba675SRob Herring }; 175*724ba675SRob Herring 176*724ba675SRob Herring pcie_intc1: legacy-interrupt-controller { 177*724ba675SRob Herring interrupt-controller; 178*724ba675SRob Herring #interrupt-cells = <1>; 179*724ba675SRob Herring interrupt-parent = <&gic>; 180*724ba675SRob Herring interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 181*724ba675SRob Herring <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 182*724ba675SRob Herring <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 183*724ba675SRob Herring <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>; 184*724ba675SRob Herring }; 185*724ba675SRob Herring }; 186*724ba675SRob Herring 187*724ba675SRob Herring mdio: mdio@24200f00 { 188*724ba675SRob Herring compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 189*724ba675SRob Herring #address-cells = <1>; 190*724ba675SRob Herring #size-cells = <0>; 191*724ba675SRob Herring reg = <0x24200f00 0x100>; 192*724ba675SRob Herring status = "disabled"; 193*724ba675SRob Herring clocks = <&clkcpgmac>; 194*724ba675SRob Herring clock-names = "fck"; 195*724ba675SRob Herring bus_freq = <2500000>; 196*724ba675SRob Herring }; 197*724ba675SRob Herring /include/ "keystone-k2e-netcp.dtsi" 198*724ba675SRob Herring}; 199