xref: /linux/scripts/dtc/include-prefixes/arm/samsung/exynos4412.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Samsung's Exynos4412 SoC device tree source
4*724ba675SRob Herring *
5*724ba675SRob Herring * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6*724ba675SRob Herring *		http://www.samsung.com
7*724ba675SRob Herring *
8*724ba675SRob Herring * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9*724ba675SRob Herring * based board files can include this file and provide values for board specific
10*724ba675SRob Herring * bindings.
11*724ba675SRob Herring *
12*724ba675SRob Herring * Note: This file does not include device nodes for all the controllers in
13*724ba675SRob Herring * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14*724ba675SRob Herring * nodes can be added to this file.
15*724ba675SRob Herring */
16*724ba675SRob Herring
17*724ba675SRob Herring#include "exynos4x12.dtsi"
18*724ba675SRob Herring
19*724ba675SRob Herring/ {
20*724ba675SRob Herring	compatible = "samsung,exynos4412", "samsung,exynos4";
21*724ba675SRob Herring
22*724ba675SRob Herring	cpus {
23*724ba675SRob Herring		#address-cells = <1>;
24*724ba675SRob Herring		#size-cells = <0>;
25*724ba675SRob Herring
26*724ba675SRob Herring		cpu-map {
27*724ba675SRob Herring			cluster0 {
28*724ba675SRob Herring				core0 {
29*724ba675SRob Herring					cpu = <&cpu0>;
30*724ba675SRob Herring				};
31*724ba675SRob Herring				core1 {
32*724ba675SRob Herring					cpu = <&cpu1>;
33*724ba675SRob Herring				};
34*724ba675SRob Herring				core2 {
35*724ba675SRob Herring					cpu = <&cpu2>;
36*724ba675SRob Herring				};
37*724ba675SRob Herring				core3 {
38*724ba675SRob Herring					cpu = <&cpu3>;
39*724ba675SRob Herring				};
40*724ba675SRob Herring			};
41*724ba675SRob Herring		};
42*724ba675SRob Herring
43*724ba675SRob Herring		cpu0: cpu@a00 {
44*724ba675SRob Herring			device_type = "cpu";
45*724ba675SRob Herring			compatible = "arm,cortex-a9";
46*724ba675SRob Herring			reg = <0xa00>;
47*724ba675SRob Herring			clocks = <&clock CLK_ARM_CLK>;
48*724ba675SRob Herring			clock-names = "cpu";
49*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
50*724ba675SRob Herring			#cooling-cells = <2>; /* min followed by max */
51*724ba675SRob Herring		};
52*724ba675SRob Herring
53*724ba675SRob Herring		cpu1: cpu@a01 {
54*724ba675SRob Herring			device_type = "cpu";
55*724ba675SRob Herring			compatible = "arm,cortex-a9";
56*724ba675SRob Herring			reg = <0xa01>;
57*724ba675SRob Herring			clocks = <&clock CLK_ARM_CLK>;
58*724ba675SRob Herring			clock-names = "cpu";
59*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
60*724ba675SRob Herring			#cooling-cells = <2>; /* min followed by max */
61*724ba675SRob Herring		};
62*724ba675SRob Herring
63*724ba675SRob Herring		cpu2: cpu@a02 {
64*724ba675SRob Herring			device_type = "cpu";
65*724ba675SRob Herring			compatible = "arm,cortex-a9";
66*724ba675SRob Herring			reg = <0xa02>;
67*724ba675SRob Herring			clocks = <&clock CLK_ARM_CLK>;
68*724ba675SRob Herring			clock-names = "cpu";
69*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
70*724ba675SRob Herring			#cooling-cells = <2>; /* min followed by max */
71*724ba675SRob Herring		};
72*724ba675SRob Herring
73*724ba675SRob Herring		cpu3: cpu@a03 {
74*724ba675SRob Herring			device_type = "cpu";
75*724ba675SRob Herring			compatible = "arm,cortex-a9";
76*724ba675SRob Herring			reg = <0xa03>;
77*724ba675SRob Herring			clocks = <&clock CLK_ARM_CLK>;
78*724ba675SRob Herring			clock-names = "cpu";
79*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
80*724ba675SRob Herring			#cooling-cells = <2>; /* min followed by max */
81*724ba675SRob Herring		};
82*724ba675SRob Herring	};
83*724ba675SRob Herring
84*724ba675SRob Herring	cpu0_opp_table: opp-table-0 {
85*724ba675SRob Herring		compatible = "operating-points-v2";
86*724ba675SRob Herring		opp-shared;
87*724ba675SRob Herring
88*724ba675SRob Herring		opp-200000000 {
89*724ba675SRob Herring			opp-hz = /bits/ 64 <200000000>;
90*724ba675SRob Herring			opp-microvolt = <900000>;
91*724ba675SRob Herring			clock-latency-ns = <200000>;
92*724ba675SRob Herring		};
93*724ba675SRob Herring		opp-300000000 {
94*724ba675SRob Herring			opp-hz = /bits/ 64 <300000000>;
95*724ba675SRob Herring			opp-microvolt = <900000>;
96*724ba675SRob Herring			clock-latency-ns = <200000>;
97*724ba675SRob Herring		};
98*724ba675SRob Herring		opp-400000000 {
99*724ba675SRob Herring			opp-hz = /bits/ 64 <400000000>;
100*724ba675SRob Herring			opp-microvolt = <925000>;
101*724ba675SRob Herring			clock-latency-ns = <200000>;
102*724ba675SRob Herring		};
103*724ba675SRob Herring		opp-500000000 {
104*724ba675SRob Herring			opp-hz = /bits/ 64 <500000000>;
105*724ba675SRob Herring			opp-microvolt = <950000>;
106*724ba675SRob Herring			clock-latency-ns = <200000>;
107*724ba675SRob Herring		};
108*724ba675SRob Herring		opp-600000000 {
109*724ba675SRob Herring			opp-hz = /bits/ 64 <600000000>;
110*724ba675SRob Herring			opp-microvolt = <975000>;
111*724ba675SRob Herring			clock-latency-ns = <200000>;
112*724ba675SRob Herring		};
113*724ba675SRob Herring		opp-700000000 {
114*724ba675SRob Herring			opp-hz = /bits/ 64 <700000000>;
115*724ba675SRob Herring			opp-microvolt = <987500>;
116*724ba675SRob Herring			clock-latency-ns = <200000>;
117*724ba675SRob Herring		};
118*724ba675SRob Herring		opp-800000000 {
119*724ba675SRob Herring			opp-hz = /bits/ 64 <800000000>;
120*724ba675SRob Herring			opp-microvolt = <1000000>;
121*724ba675SRob Herring			clock-latency-ns = <200000>;
122*724ba675SRob Herring			opp-suspend;
123*724ba675SRob Herring		};
124*724ba675SRob Herring		opp-900000000 {
125*724ba675SRob Herring			opp-hz = /bits/ 64 <900000000>;
126*724ba675SRob Herring			opp-microvolt = <1037500>;
127*724ba675SRob Herring			clock-latency-ns = <200000>;
128*724ba675SRob Herring		};
129*724ba675SRob Herring		opp-1000000000 {
130*724ba675SRob Herring			opp-hz = /bits/ 64 <1000000000>;
131*724ba675SRob Herring			opp-microvolt = <1087500>;
132*724ba675SRob Herring			clock-latency-ns = <200000>;
133*724ba675SRob Herring		};
134*724ba675SRob Herring		opp-1100000000 {
135*724ba675SRob Herring			opp-hz = /bits/ 64 <1100000000>;
136*724ba675SRob Herring			opp-microvolt = <1137500>;
137*724ba675SRob Herring			clock-latency-ns = <200000>;
138*724ba675SRob Herring		};
139*724ba675SRob Herring		opp-1200000000 {
140*724ba675SRob Herring			opp-hz = /bits/ 64 <1200000000>;
141*724ba675SRob Herring			opp-microvolt = <1187500>;
142*724ba675SRob Herring			clock-latency-ns = <200000>;
143*724ba675SRob Herring		};
144*724ba675SRob Herring		opp-1300000000 {
145*724ba675SRob Herring			opp-hz = /bits/ 64 <1300000000>;
146*724ba675SRob Herring			opp-microvolt = <1250000>;
147*724ba675SRob Herring			clock-latency-ns = <200000>;
148*724ba675SRob Herring		};
149*724ba675SRob Herring		opp-1400000000 {
150*724ba675SRob Herring			opp-hz = /bits/ 64 <1400000000>;
151*724ba675SRob Herring			opp-microvolt = <1287500>;
152*724ba675SRob Herring			clock-latency-ns = <200000>;
153*724ba675SRob Herring		};
154*724ba675SRob Herring		cpu0_opp_1500: opp-1500000000 {
155*724ba675SRob Herring			opp-hz = /bits/ 64 <1500000000>;
156*724ba675SRob Herring			opp-microvolt = <1350000>;
157*724ba675SRob Herring			clock-latency-ns = <200000>;
158*724ba675SRob Herring			turbo-mode;
159*724ba675SRob Herring		};
160*724ba675SRob Herring	};
161*724ba675SRob Herring};
162*724ba675SRob Herring
163*724ba675SRob Herring&clock {
164*724ba675SRob Herring	compatible = "samsung,exynos4412-clock";
165*724ba675SRob Herring};
166*724ba675SRob Herring
167*724ba675SRob Herring&combiner {
168*724ba675SRob Herring	samsung,combiner-nr = <20>;
169*724ba675SRob Herring};
170*724ba675SRob Herring
171*724ba675SRob Herring&gic {
172*724ba675SRob Herring	cpu-offset = <0x4000>;
173*724ba675SRob Herring};
174*724ba675SRob Herring
175*724ba675SRob Herring&pmu {
176*724ba675SRob Herring	interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
177*724ba675SRob Herring	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
178*724ba675SRob Herring	status = "okay";
179*724ba675SRob Herring};
180*724ba675SRob Herring
181*724ba675SRob Herring&pmu_system_controller {
182*724ba675SRob Herring	compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon";
183*724ba675SRob Herring};
184