1*724ba675SRob Herring /* SPDX-License-Identifier: GPL-2.0 */ 2*724ba675SRob Herring /* 3*724ba675SRob Herring * Samsung Exynos DTS pinctrl constants 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6*724ba675SRob Herring * http://www.samsung.com 7*724ba675SRob Herring * Copyright (c) 2022 Linaro Ltd 8*724ba675SRob Herring * Author: Krzysztof Kozlowski <krzk@kernel.org> 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring #ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ 12*724ba675SRob Herring #define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ 13*724ba675SRob Herring 14*724ba675SRob Herring #define EXYNOS_PIN_PULL_NONE 0 15*724ba675SRob Herring #define EXYNOS_PIN_PULL_DOWN 1 16*724ba675SRob Herring #define EXYNOS_PIN_PULL_UP 3 17*724ba675SRob Herring 18*724ba675SRob Herring /* Pin function in power down mode */ 19*724ba675SRob Herring #define EXYNOS_PIN_PDN_OUT0 0 20*724ba675SRob Herring #define EXYNOS_PIN_PDN_OUT1 1 21*724ba675SRob Herring #define EXYNOS_PIN_PDN_INPUT 2 22*724ba675SRob Herring #define EXYNOS_PIN_PDN_PREV 3 23*724ba675SRob Herring 24*724ba675SRob Herring /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ 25*724ba675SRob Herring #define EXYNOS4_PIN_DRV_LV1 0 26*724ba675SRob Herring #define EXYNOS4_PIN_DRV_LV2 2 27*724ba675SRob Herring #define EXYNOS4_PIN_DRV_LV3 1 28*724ba675SRob Herring #define EXYNOS4_PIN_DRV_LV4 3 29*724ba675SRob Herring 30*724ba675SRob Herring /* Drive strengths for Exynos5260 */ 31*724ba675SRob Herring #define EXYNOS5260_PIN_DRV_LV1 0 32*724ba675SRob Herring #define EXYNOS5260_PIN_DRV_LV2 1 33*724ba675SRob Herring #define EXYNOS5260_PIN_DRV_LV4 2 34*724ba675SRob Herring #define EXYNOS5260_PIN_DRV_LV6 3 35*724ba675SRob Herring 36*724ba675SRob Herring /* 37*724ba675SRob Herring * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except 38*724ba675SRob Herring * GPIO_HSI block) 39*724ba675SRob Herring */ 40*724ba675SRob Herring #define EXYNOS5420_PIN_DRV_LV1 0 41*724ba675SRob Herring #define EXYNOS5420_PIN_DRV_LV2 1 42*724ba675SRob Herring #define EXYNOS5420_PIN_DRV_LV3 2 43*724ba675SRob Herring #define EXYNOS5420_PIN_DRV_LV4 3 44*724ba675SRob Herring 45*724ba675SRob Herring #define EXYNOS_PIN_FUNC_INPUT 0 46*724ba675SRob Herring #define EXYNOS_PIN_FUNC_OUTPUT 1 47*724ba675SRob Herring #define EXYNOS_PIN_FUNC_2 2 48*724ba675SRob Herring #define EXYNOS_PIN_FUNC_3 3 49*724ba675SRob Herring #define EXYNOS_PIN_FUNC_4 4 50*724ba675SRob Herring #define EXYNOS_PIN_FUNC_5 5 51*724ba675SRob Herring #define EXYNOS_PIN_FUNC_6 6 52*724ba675SRob Herring #define EXYNOS_PIN_FUNC_EINT 0xf 53*724ba675SRob Herring #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 54*724ba675SRob Herring 55*724ba675SRob Herring #endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */ 56