1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1126-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rv1126-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1126"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 serial4 = &uart4; 29 serial5 = &uart5; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu0: cpu@f00 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a7"; 39 reg = <0xf00>; 40 enable-method = "psci"; 41 clocks = <&cru ARMCLK>; 42 }; 43 44 cpu1: cpu@f01 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a7"; 47 reg = <0xf01>; 48 enable-method = "psci"; 49 clocks = <&cru ARMCLK>; 50 }; 51 52 cpu2: cpu@f02 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0xf02>; 56 enable-method = "psci"; 57 clocks = <&cru ARMCLK>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 enable-method = "psci"; 65 clocks = <&cru ARMCLK>; 66 }; 67 }; 68 69 arm-pmu { 70 compatible = "arm,cortex-a7-pmu"; 71 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 75 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 76 }; 77 78 psci { 79 compatible = "arm,psci-1.0"; 80 method = "smc"; 81 }; 82 83 timer { 84 compatible = "arm,armv7-timer"; 85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 86 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 87 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 88 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 89 clock-frequency = <24000000>; 90 }; 91 92 display_subsystem { 93 compatible = "rockchip,display-subsystem"; 94 ports = <&vop_out>; 95 }; 96 97 xin24m: oscillator { 98 compatible = "fixed-clock"; 99 clock-frequency = <24000000>; 100 clock-output-names = "xin24m"; 101 #clock-cells = <0>; 102 }; 103 104 grf: syscon@fe000000 { 105 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 106 reg = <0xfe000000 0x20000>; 107 }; 108 109 pmugrf: syscon@fe020000 { 110 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 111 reg = <0xfe020000 0x1000>; 112 113 pmu_io_domains: io-domains { 114 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 115 status = "disabled"; 116 }; 117 }; 118 119 qos_emmc: qos@fe860000 { 120 compatible = "rockchip,rv1126-qos", "syscon"; 121 reg = <0xfe860000 0x20>; 122 }; 123 124 qos_nandc: qos@fe860080 { 125 compatible = "rockchip,rv1126-qos", "syscon"; 126 reg = <0xfe860080 0x20>; 127 }; 128 129 qos_sfc: qos@fe860200 { 130 compatible = "rockchip,rv1126-qos", "syscon"; 131 reg = <0xfe860200 0x20>; 132 }; 133 134 qos_sdio: qos@fe86c000 { 135 compatible = "rockchip,rv1126-qos", "syscon"; 136 reg = <0xfe86c000 0x20>; 137 }; 138 139 qos_iep: qos@fe8a0000 { 140 compatible = "rockchip,rv1126-qos", "syscon"; 141 reg = <0xfe8a0000 0x20>; 142 }; 143 144 qos_rga_rd: qos@fe8a0080 { 145 compatible = "rockchip,rv1126-qos", "syscon"; 146 reg = <0xfe8a0080 0x20>; 147 }; 148 149 qos_rga_wr: qos@fe8a0100 { 150 compatible = "rockchip,rv1126-qos", "syscon"; 151 reg = <0xfe8a0100 0x20>; 152 }; 153 154 qos_vop: qos@fe8a0180 { 155 compatible = "rockchip,rv1126-qos", "syscon"; 156 reg = <0xfe8a0180 0x20>; 157 }; 158 159 gic: interrupt-controller@feff0000 { 160 compatible = "arm,gic-400"; 161 interrupt-controller; 162 #interrupt-cells = <3>; 163 #address-cells = <0>; 164 165 reg = <0xfeff1000 0x1000>, 166 <0xfeff2000 0x2000>, 167 <0xfeff4000 0x2000>, 168 <0xfeff6000 0x2000>; 169 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 170 }; 171 172 pmu: power-management@ff3e0000 { 173 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 174 reg = <0xff3e0000 0x1000>; 175 176 power: power-controller { 177 compatible = "rockchip,rv1126-power-controller"; 178 #power-domain-cells = <1>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 power-domain@RV1126_PD_NVM { 183 reg = <RV1126_PD_NVM>; 184 clocks = <&cru HCLK_EMMC>, 185 <&cru CLK_EMMC>, 186 <&cru HCLK_NANDC>, 187 <&cru CLK_NANDC>, 188 <&cru HCLK_SFC>, 189 <&cru HCLK_SFCXIP>, 190 <&cru SCLK_SFC>; 191 pm_qos = <&qos_emmc>, 192 <&qos_nandc>, 193 <&qos_sfc>; 194 #power-domain-cells = <0>; 195 }; 196 197 power-domain@RV1126_PD_SDIO { 198 reg = <RV1126_PD_SDIO>; 199 clocks = <&cru HCLK_SDIO>, 200 <&cru CLK_SDIO>; 201 pm_qos = <&qos_sdio>; 202 #power-domain-cells = <0>; 203 }; 204 205 power-domain@RV1126_PD_VO { 206 reg = <RV1126_PD_VO>; 207 clocks = <&cru ACLK_RGA>, 208 <&cru HCLK_RGA>, 209 <&cru CLK_RGA_CORE>, 210 <&cru ACLK_VOP>, 211 <&cru HCLK_VOP>, 212 <&cru DCLK_VOP>, 213 <&cru PCLK_DSIHOST>, 214 <&cru ACLK_IEP>, 215 <&cru HCLK_IEP>, 216 <&cru CLK_IEP_CORE>; 217 pm_qos = <&qos_rga_rd>, 218 <&qos_rga_wr>, 219 <&qos_vop>, 220 <&qos_iep>; 221 #power-domain-cells = <0>; 222 }; 223 }; 224 }; 225 226 i2c0: i2c@ff3f0000 { 227 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 228 reg = <0xff3f0000 0x1000>; 229 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 230 rockchip,grf = <&pmugrf>; 231 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 232 clock-names = "i2c", "pclk"; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&i2c0_xfer>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 status = "disabled"; 238 }; 239 240 uart1: serial@ff410000 { 241 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 242 reg = <0xff410000 0x100>; 243 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 244 clock-frequency = <24000000>; 245 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 246 clock-names = "baudclk", "apb_pclk"; 247 dmas = <&dmac 7>, <&dmac 6>; 248 dma-names = "tx", "rx"; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&uart1m0_xfer>; 251 reg-shift = <2>; 252 reg-io-width = <4>; 253 status = "disabled"; 254 }; 255 256 pwm2: pwm@ff430020 { 257 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 258 reg = <0xff430020 0x10>; 259 clock-names = "pwm", "pclk"; 260 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pwm2m0_pins>; 263 #pwm-cells = <3>; 264 status = "disabled"; 265 }; 266 267 pmucru: clock-controller@ff480000 { 268 compatible = "rockchip,rv1126-pmucru"; 269 reg = <0xff480000 0x1000>; 270 rockchip,grf = <&grf>; 271 #clock-cells = <1>; 272 #reset-cells = <1>; 273 }; 274 275 cru: clock-controller@ff490000 { 276 compatible = "rockchip,rv1126-cru"; 277 reg = <0xff490000 0x1000>; 278 clocks = <&xin24m>; 279 clock-names = "xin24m"; 280 rockchip,grf = <&grf>; 281 #clock-cells = <1>; 282 #reset-cells = <1>; 283 }; 284 285 dmac: dma-controller@ff4e0000 { 286 compatible = "arm,pl330", "arm,primecell"; 287 reg = <0xff4e0000 0x4000>; 288 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 290 #dma-cells = <1>; 291 arm,pl330-periph-burst; 292 clocks = <&cru ACLK_DMAC>; 293 clock-names = "apb_pclk"; 294 }; 295 296 pwm11: pwm@ff550030 { 297 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 298 reg = <0xff550030 0x10>; 299 clock-names = "pwm", "pclk"; 300 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 301 pinctrl-0 = <&pwm11m0_pins>; 302 pinctrl-names = "default"; 303 #pwm-cells = <3>; 304 status = "disabled"; 305 }; 306 307 uart0: serial@ff560000 { 308 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 309 reg = <0xff560000 0x100>; 310 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 311 clock-frequency = <24000000>; 312 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 313 clock-names = "baudclk", "apb_pclk"; 314 dmas = <&dmac 5>, <&dmac 4>; 315 dma-names = "tx", "rx"; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&uart0_xfer>; 318 reg-shift = <2>; 319 reg-io-width = <4>; 320 status = "disabled"; 321 }; 322 323 uart2: serial@ff570000 { 324 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 325 reg = <0xff570000 0x100>; 326 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 327 clock-frequency = <24000000>; 328 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 329 clock-names = "baudclk", "apb_pclk"; 330 dmas = <&dmac 9>, <&dmac 8>; 331 dma-names = "tx", "rx"; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&uart2m1_xfer>; 334 reg-shift = <2>; 335 reg-io-width = <4>; 336 status = "disabled"; 337 }; 338 339 uart3: serial@ff580000 { 340 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 341 reg = <0xff580000 0x100>; 342 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 343 clock-frequency = <24000000>; 344 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 345 clock-names = "baudclk", "apb_pclk"; 346 dmas = <&dmac 11>, <&dmac 10>; 347 dma-names = "tx", "rx"; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&uart3m0_xfer>; 350 reg-shift = <2>; 351 reg-io-width = <4>; 352 status = "disabled"; 353 }; 354 355 uart4: serial@ff590000 { 356 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 357 reg = <0xff590000 0x100>; 358 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 359 clock-frequency = <24000000>; 360 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 361 clock-names = "baudclk", "apb_pclk"; 362 dmas = <&dmac 13>, <&dmac 12>; 363 dma-names = "tx", "rx"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&uart4m0_xfer>; 366 reg-shift = <2>; 367 reg-io-width = <4>; 368 status = "disabled"; 369 }; 370 371 uart5: serial@ff5a0000 { 372 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 373 reg = <0xff5a0000 0x100>; 374 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 375 clock-frequency = <24000000>; 376 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 377 clock-names = "baudclk", "apb_pclk"; 378 dmas = <&dmac 15>, <&dmac 14>; 379 dma-names = "tx", "rx"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&uart5m0_xfer>; 382 reg-shift = <2>; 383 reg-io-width = <4>; 384 status = "disabled"; 385 }; 386 387 saradc: adc@ff5e0000 { 388 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; 389 reg = <0xff5e0000 0x100>; 390 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 391 #io-channel-cells = <1>; 392 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 393 clock-names = "saradc", "apb_pclk"; 394 resets = <&cru SRST_SARADC_P>; 395 reset-names = "saradc-apb"; 396 status = "disabled"; 397 }; 398 399 timer0: timer@ff660000 { 400 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; 401 reg = <0xff660000 0x20>; 402 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 404 clock-names = "pclk", "timer"; 405 }; 406 407 vop: vop@ffb00000 { 408 compatible = "rockchip,rv1126-vop"; 409 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 410 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 411 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 412 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 413 reset-names = "axi", "ahb", "dclk"; 414 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 415 iommus = <&vop_mmu>; 416 power-domains = <&power RV1126_PD_VO>; 417 status = "disabled"; 418 419 vop_out: port { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 423 vop_out_rgb: endpoint@0 { 424 reg = <0>; 425 }; 426 427 vop_out_dsi: endpoint@1 { 428 reg = <1>; 429 }; 430 }; 431 }; 432 433 vop_mmu: iommu@ffb00f00 { 434 compatible = "rockchip,iommu"; 435 reg = <0xffb00f00 0x100>; 436 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 437 clock-names = "aclk", "iface"; 438 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 439 #iommu-cells = <0>; 440 power-domains = <&power RV1126_PD_VO>; 441 status = "disabled"; 442 }; 443 444 gmac: ethernet@ffc40000 { 445 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 446 reg = <0xffc40000 0x4000>; 447 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 449 interrupt-names = "macirq", "eth_wake_irq"; 450 rockchip,grf = <&grf>; 451 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 452 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 453 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 454 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 455 clock-names = "stmmaceth", "mac_clk_rx", 456 "mac_clk_tx", "clk_mac_ref", 457 "aclk_mac", "pclk_mac", 458 "clk_mac_speed", "ptp_ref"; 459 resets = <&cru SRST_GMAC_A>; 460 reset-names = "stmmaceth"; 461 462 snps,mixed-burst; 463 snps,tso; 464 465 snps,axi-config = <&stmmac_axi_setup>; 466 snps,mtl-rx-config = <&mtl_rx_setup>; 467 snps,mtl-tx-config = <&mtl_tx_setup>; 468 status = "disabled"; 469 470 mdio: mdio { 471 compatible = "snps,dwmac-mdio"; 472 #address-cells = <0x1>; 473 #size-cells = <0x0>; 474 }; 475 476 stmmac_axi_setup: stmmac-axi-config { 477 snps,wr_osr_lmt = <4>; 478 snps,rd_osr_lmt = <8>; 479 snps,blen = <0 0 0 0 16 8 4>; 480 }; 481 482 mtl_rx_setup: rx-queues-config { 483 snps,rx-queues-to-use = <1>; 484 queue0 {}; 485 }; 486 487 mtl_tx_setup: tx-queues-config { 488 snps,tx-queues-to-use = <1>; 489 queue0 {}; 490 }; 491 }; 492 493 emmc: mmc@ffc50000 { 494 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 495 reg = <0xffc50000 0x4000>; 496 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 498 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 499 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 500 fifo-depth = <0x100>; 501 max-frequency = <200000000>; 502 power-domains = <&power RV1126_PD_NVM>; 503 status = "disabled"; 504 }; 505 506 sdmmc: mmc@ffc60000 { 507 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 508 reg = <0xffc60000 0x4000>; 509 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 511 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 512 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 513 fifo-depth = <0x100>; 514 max-frequency = <200000000>; 515 status = "disabled"; 516 }; 517 518 sdio: mmc@ffc70000 { 519 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 520 reg = <0xffc70000 0x4000>; 521 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 523 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 524 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 525 fifo-depth = <0x100>; 526 max-frequency = <200000000>; 527 power-domains = <&power RV1126_PD_SDIO>; 528 status = "disabled"; 529 }; 530 531 sfc: spi@ffc90000 { 532 compatible = "rockchip,sfc"; 533 reg = <0xffc90000 0x4000>; 534 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 535 assigned-clocks = <&cru SCLK_SFC>; 536 assigned-clock-rates = <80000000>; 537 clock-names = "clk_sfc", "hclk_sfc"; 538 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 539 power-domains = <&power RV1126_PD_NVM>; 540 status = "disabled"; 541 }; 542 543 pinctrl: pinctrl { 544 compatible = "rockchip,rv1126-pinctrl"; 545 rockchip,grf = <&grf>; 546 rockchip,pmu = <&pmugrf>; 547 #address-cells = <1>; 548 #size-cells = <1>; 549 ranges; 550 551 gpio0: gpio@ff460000 { 552 compatible = "rockchip,gpio-bank"; 553 reg = <0xff460000 0x100>; 554 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 }; 561 562 gpio1: gpio@ff620000 { 563 compatible = "rockchip,gpio-bank"; 564 reg = <0xff620000 0x100>; 565 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 567 gpio-controller; 568 #gpio-cells = <2>; 569 interrupt-controller; 570 #interrupt-cells = <2>; 571 }; 572 573 gpio2: gpio@ff630000 { 574 compatible = "rockchip,gpio-bank"; 575 reg = <0xff630000 0x100>; 576 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 578 gpio-controller; 579 #gpio-cells = <2>; 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 }; 583 584 gpio3: gpio@ff640000 { 585 compatible = "rockchip,gpio-bank"; 586 reg = <0xff640000 0x100>; 587 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 589 gpio-controller; 590 #gpio-cells = <2>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 }; 594 595 gpio4: gpio@ff650000 { 596 compatible = "rockchip,gpio-bank"; 597 reg = <0xff650000 0x100>; 598 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 600 gpio-controller; 601 #gpio-cells = <2>; 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 }; 606}; 607 608#include "rv1126-pinctrl.dtsi" 609