1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 enable-method = "rockchip,rk3036-smp"; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 resets = <&cru SRST_CORE0>; 39 operating-points-v2 = <&cpu_opp_table>; 40 #cooling-cells = <2>; /* min followed by max */ 41 }; 42 43 cpu1: cpu@f01 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0xf01>; 47 resets = <&cru SRST_CORE1>; 48 operating-points-v2 = <&cpu_opp_table>; 49 }; 50 51 cpu2: cpu@f02 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf02>; 55 resets = <&cru SRST_CORE2>; 56 operating-points-v2 = <&cpu_opp_table>; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 operating-points-v2 = <&cpu_opp_table>; 65 }; 66 }; 67 68 cpu_opp_table: opp-table-0 { 69 compatible = "operating-points-v2"; 70 opp-shared; 71 72 opp-216000000 { 73 opp-hz = /bits/ 64 <216000000>; 74 opp-microvolt = <950000 950000 1325000>; 75 }; 76 opp-408000000 { 77 opp-hz = /bits/ 64 <408000000>; 78 opp-microvolt = <950000 950000 1325000>; 79 }; 80 opp-600000000 { 81 opp-hz = /bits/ 64 <600000000>; 82 opp-microvolt = <950000 950000 1325000>; 83 }; 84 opp-696000000 { 85 opp-hz = /bits/ 64 <696000000>; 86 opp-microvolt = <975000 975000 1325000>; 87 }; 88 opp-816000000 { 89 opp-hz = /bits/ 64 <816000000>; 90 opp-microvolt = <1075000 1075000 1325000>; 91 opp-suspend; 92 }; 93 opp-1008000000 { 94 opp-hz = /bits/ 64 <1008000000>; 95 opp-microvolt = <1200000 1200000 1325000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <1325000 1325000 1325000>; 100 }; 101 }; 102 103 timer { 104 compatible = "arm,armv7-timer"; 105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 arm,cpu-registers-not-fw-configured; 110 clock-frequency = <24000000>; 111 }; 112 113 xin24m: oscillator { 114 compatible = "fixed-clock"; 115 clock-frequency = <24000000>; 116 clock-output-names = "xin24m"; 117 #clock-cells = <0>; 118 }; 119 120 imem: sram@10080000 { 121 compatible = "mmio-sram"; 122 reg = <0x10080000 0x2000>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0x10080000 0x2000>; 126 127 smp-sram@0 { 128 compatible = "rockchip,rk3066-smp-sram"; 129 reg = <0x00 0x10>; 130 }; 131 }; 132 133 pmu: syscon@100a0000 { 134 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 135 reg = <0x100a0000 0x1000>; 136 }; 137 138 gic: interrupt-controller@10139000 { 139 compatible = "arm,cortex-a7-gic"; 140 reg = <0x10139000 0x1000>, 141 <0x1013a000 0x1000>, 142 <0x1013c000 0x2000>, 143 <0x1013e000 0x2000>; 144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 #address-cells = <0>; 148 }; 149 150 usb_otg: usb@10180000 { 151 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 152 reg = <0x10180000 0x40000>; 153 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&cru HCLK_OTG>; 155 clock-names = "otg"; 156 dr_mode = "otg"; 157 g-np-tx-fifo-size = <16>; 158 g-rx-fifo-size = <280>; 159 g-tx-fifo-size = <256 128 128 64 32 16>; 160 phys = <&usb2phy_otg>; 161 phy-names = "usb2-phy"; 162 status = "disabled"; 163 }; 164 165 usb_host_ehci: usb@101c0000 { 166 compatible = "generic-ehci"; 167 reg = <0x101c0000 0x20000>; 168 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&cru HCLK_HOST2>; 170 phys = <&usb2phy_host>; 171 phy-names = "usb"; 172 status = "disabled"; 173 }; 174 175 usb_host_ohci: usb@101e0000 { 176 compatible = "generic-ohci"; 177 reg = <0x101e0000 0x20000>; 178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru HCLK_HOST2>; 180 phys = <&usb2phy_host>; 181 phy-names = "usb"; 182 status = "disabled"; 183 }; 184 185 sdmmc: mmc@10214000 { 186 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 187 reg = <0x10214000 0x4000>; 188 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 190 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 191 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 192 dmas = <&pdma 10>; 193 dma-names = "rx-tx"; 194 fifo-depth = <256>; 195 max-frequency = <150000000>; 196 resets = <&cru SRST_SDMMC>; 197 reset-names = "reset"; 198 status = "disabled"; 199 }; 200 201 sdio: mmc@10218000 { 202 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 203 reg = <0x10218000 0x4000>; 204 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 206 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 207 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 208 dmas = <&pdma 11>; 209 dma-names = "rx-tx"; 210 fifo-depth = <256>; 211 max-frequency = <150000000>; 212 resets = <&cru SRST_SDIO>; 213 reset-names = "reset"; 214 status = "disabled"; 215 }; 216 217 emmc: mmc@1021c000 { 218 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 219 reg = <0x1021c000 0x4000>; 220 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 222 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 223 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 224 dmas = <&pdma 12>; 225 dma-names = "rx-tx"; 226 fifo-depth = <256>; 227 max-frequency = <150000000>; 228 resets = <&cru SRST_EMMC>; 229 reset-names = "reset"; 230 status = "disabled"; 231 }; 232 233 nfc: nand-controller@10500000 { 234 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 235 reg = <0x10500000 0x4000>; 236 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 238 clock-names = "ahb", "nfc"; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 241 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 242 status = "disabled"; 243 }; 244 245 cru: clock-controller@20000000 { 246 compatible = "rockchip,rk3128-cru"; 247 reg = <0x20000000 0x1000>; 248 clocks = <&xin24m>; 249 clock-names = "xin24m"; 250 rockchip,grf = <&grf>; 251 #clock-cells = <1>; 252 #reset-cells = <1>; 253 assigned-clocks = <&cru PLL_GPLL>; 254 assigned-clock-rates = <594000000>; 255 }; 256 257 grf: syscon@20008000 { 258 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 259 reg = <0x20008000 0x1000>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 263 usb2phy: usb2phy@17c { 264 compatible = "rockchip,rk3128-usb2phy"; 265 reg = <0x017c 0x0c>; 266 clocks = <&cru SCLK_OTGPHY0>; 267 clock-names = "phyclk"; 268 clock-output-names = "usb480m_phy"; 269 assigned-clocks = <&cru SCLK_USB480M>; 270 assigned-clock-parents = <&usb2phy>; 271 #clock-cells = <0>; 272 status = "disabled"; 273 274 usb2phy_host: host-port { 275 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "linestate"; 277 #phy-cells = <0>; 278 status = "disabled"; 279 }; 280 281 usb2phy_otg: otg-port { 282 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-names = "otg-bvalid", "otg-id", 286 "linestate"; 287 #phy-cells = <0>; 288 status = "disabled"; 289 }; 290 }; 291 }; 292 293 timer0: timer@20044000 { 294 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 295 reg = <0x20044000 0x20>; 296 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 298 clock-names = "pclk", "timer"; 299 }; 300 301 timer1: timer@20044020 { 302 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 303 reg = <0x20044020 0x20>; 304 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 306 clock-names = "pclk", "timer"; 307 }; 308 309 timer2: timer@20044040 { 310 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 311 reg = <0x20044040 0x20>; 312 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 314 clock-names = "pclk", "timer"; 315 }; 316 317 timer3: timer@20044060 { 318 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 319 reg = <0x20044060 0x20>; 320 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 322 clock-names = "pclk", "timer"; 323 }; 324 325 timer4: timer@20044080 { 326 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 327 reg = <0x20044080 0x20>; 328 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 330 clock-names = "pclk", "timer"; 331 }; 332 333 timer5: timer@200440a0 { 334 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 335 reg = <0x200440a0 0x20>; 336 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 338 clock-names = "pclk", "timer"; 339 }; 340 341 watchdog: watchdog@2004c000 { 342 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 343 reg = <0x2004c000 0x100>; 344 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&cru PCLK_WDT>; 346 status = "disabled"; 347 }; 348 349 pwm0: pwm@20050000 { 350 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 351 reg = <0x20050000 0x10>; 352 clocks = <&cru PCLK_PWM>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pwm0_pin>; 355 #pwm-cells = <3>; 356 status = "disabled"; 357 }; 358 359 pwm1: pwm@20050010 { 360 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 361 reg = <0x20050010 0x10>; 362 clocks = <&cru PCLK_PWM>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pwm1_pin>; 365 #pwm-cells = <3>; 366 status = "disabled"; 367 }; 368 369 pwm2: pwm@20050020 { 370 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 371 reg = <0x20050020 0x10>; 372 clocks = <&cru PCLK_PWM>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pwm2_pin>; 375 #pwm-cells = <3>; 376 status = "disabled"; 377 }; 378 379 pwm3: pwm@20050030 { 380 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 381 reg = <0x20050030 0x10>; 382 clocks = <&cru PCLK_PWM>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pwm3_pin>; 385 #pwm-cells = <3>; 386 status = "disabled"; 387 }; 388 389 i2c1: i2c@20056000 { 390 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 391 reg = <0x20056000 0x1000>; 392 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 393 clock-names = "i2c"; 394 clocks = <&cru PCLK_I2C1>; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&i2c1_xfer>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 status = "disabled"; 400 }; 401 402 i2c2: i2c@2005a000 { 403 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 404 reg = <0x2005a000 0x1000>; 405 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 406 clock-names = "i2c"; 407 clocks = <&cru PCLK_I2C2>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c2_xfer>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 i2c3: i2c@2005e000 { 416 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 417 reg = <0x2005e000 0x1000>; 418 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 419 clock-names = "i2c"; 420 clocks = <&cru PCLK_I2C3>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&i2c3_xfer>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 uart0: serial@20060000 { 429 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 430 reg = <0x20060000 0x100>; 431 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 432 clock-frequency = <24000000>; 433 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 434 clock-names = "baudclk", "apb_pclk"; 435 dmas = <&pdma 2>, <&pdma 3>; 436 dma-names = "tx", "rx"; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 439 reg-io-width = <4>; 440 reg-shift = <2>; 441 status = "disabled"; 442 }; 443 444 uart1: serial@20064000 { 445 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 446 reg = <0x20064000 0x100>; 447 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 448 clock-frequency = <24000000>; 449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 450 clock-names = "baudclk", "apb_pclk"; 451 dmas = <&pdma 4>, <&pdma 5>; 452 dma-names = "tx", "rx"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&uart1_xfer>; 455 reg-io-width = <4>; 456 reg-shift = <2>; 457 status = "disabled"; 458 }; 459 460 uart2: serial@20068000 { 461 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 462 reg = <0x20068000 0x100>; 463 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 464 clock-frequency = <24000000>; 465 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 466 clock-names = "baudclk", "apb_pclk"; 467 dmas = <&pdma 6>, <&pdma 7>; 468 dma-names = "tx", "rx"; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&uart2_xfer>; 471 reg-io-width = <4>; 472 reg-shift = <2>; 473 status = "disabled"; 474 }; 475 476 saradc: saradc@2006c000 { 477 compatible = "rockchip,saradc"; 478 reg = <0x2006c000 0x100>; 479 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 481 clock-names = "saradc", "apb_pclk"; 482 resets = <&cru SRST_SARADC>; 483 reset-names = "saradc-apb"; 484 #io-channel-cells = <1>; 485 status = "disabled"; 486 }; 487 488 i2c0: i2c@20072000 { 489 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 490 reg = <0x20072000 0x1000>; 491 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 492 clock-names = "i2c"; 493 clocks = <&cru PCLK_I2C0>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&i2c0_xfer>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 spi0: spi@20074000 { 502 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 503 reg = <0x20074000 0x1000>; 504 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 506 clock-names = "spiclk", "apb_pclk"; 507 dmas = <&pdma 8>, <&pdma 9>; 508 dma-names = "tx", "rx"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 status = "disabled"; 514 }; 515 516 pdma: dma-controller@20078000 { 517 compatible = "arm,pl330", "arm,primecell"; 518 reg = <0x20078000 0x4000>; 519 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 521 arm,pl330-broken-no-flushp; 522 arm,pl330-periph-burst; 523 clocks = <&cru ACLK_DMAC>; 524 clock-names = "apb_pclk"; 525 #dma-cells = <1>; 526 }; 527 528 pinctrl: pinctrl { 529 compatible = "rockchip,rk3128-pinctrl"; 530 rockchip,grf = <&grf>; 531 #address-cells = <1>; 532 #size-cells = <1>; 533 ranges; 534 535 gpio0: gpio@2007c000 { 536 compatible = "rockchip,gpio-bank"; 537 reg = <0x2007c000 0x100>; 538 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cru PCLK_GPIO0>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 interrupt-controller; 543 #interrupt-cells = <2>; 544 }; 545 546 gpio1: gpio@20080000 { 547 compatible = "rockchip,gpio-bank"; 548 reg = <0x20080000 0x100>; 549 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&cru PCLK_GPIO1>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 }; 556 557 gpio2: gpio@20084000 { 558 compatible = "rockchip,gpio-bank"; 559 reg = <0x20084000 0x100>; 560 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&cru PCLK_GPIO2>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 }; 567 568 gpio3: gpio@20088000 { 569 compatible = "rockchip,gpio-bank"; 570 reg = <0x20088000 0x100>; 571 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cru PCLK_GPIO3>; 573 gpio-controller; 574 #gpio-cells = <2>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 }; 578 579 pcfg_pull_default: pcfg-pull-default { 580 bias-pull-pin-default; 581 }; 582 583 pcfg_pull_none: pcfg-pull-none { 584 bias-disable; 585 }; 586 587 emmc { 588 emmc_clk: emmc-clk { 589 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 590 }; 591 592 emmc_cmd: emmc-cmd { 593 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 594 }; 595 596 emmc_cmd1: emmc-cmd1 { 597 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 598 }; 599 600 emmc_pwr: emmc-pwr { 601 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 602 }; 603 604 emmc_bus1: emmc-bus1 { 605 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 606 }; 607 608 emmc_bus4: emmc-bus4 { 609 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 610 <1 RK_PD1 2 &pcfg_pull_default>, 611 <1 RK_PD2 2 &pcfg_pull_default>, 612 <1 RK_PD3 2 &pcfg_pull_default>; 613 }; 614 615 emmc_bus8: emmc-bus8 { 616 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 617 <1 RK_PD1 2 &pcfg_pull_default>, 618 <1 RK_PD2 2 &pcfg_pull_default>, 619 <1 RK_PD3 2 &pcfg_pull_default>, 620 <1 RK_PD4 2 &pcfg_pull_default>, 621 <1 RK_PD5 2 &pcfg_pull_default>, 622 <1 RK_PD6 2 &pcfg_pull_default>, 623 <1 RK_PD7 2 &pcfg_pull_default>; 624 }; 625 }; 626 627 gmac { 628 rgmii_pins: rgmii-pins { 629 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 630 <2 RK_PB1 3 &pcfg_pull_default>, 631 <2 RK_PB3 3 &pcfg_pull_default>, 632 <2 RK_PB4 3 &pcfg_pull_default>, 633 <2 RK_PB5 3 &pcfg_pull_default>, 634 <2 RK_PB6 3 &pcfg_pull_default>, 635 <2 RK_PC0 3 &pcfg_pull_default>, 636 <2 RK_PC1 3 &pcfg_pull_default>, 637 <2 RK_PC2 3 &pcfg_pull_default>, 638 <2 RK_PC3 3 &pcfg_pull_default>, 639 <2 RK_PD1 3 &pcfg_pull_default>, 640 <2 RK_PC4 4 &pcfg_pull_default>, 641 <2 RK_PC5 4 &pcfg_pull_default>, 642 <2 RK_PC6 4 &pcfg_pull_default>, 643 <2 RK_PC7 4 &pcfg_pull_default>; 644 }; 645 646 rmii_pins: rmii-pins { 647 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 648 <2 RK_PB4 3 &pcfg_pull_default>, 649 <2 RK_PB5 3 &pcfg_pull_default>, 650 <2 RK_PB6 3 &pcfg_pull_default>, 651 <2 RK_PB7 3 &pcfg_pull_default>, 652 <2 RK_PC0 3 &pcfg_pull_default>, 653 <2 RK_PC1 3 &pcfg_pull_default>, 654 <2 RK_PC2 3 &pcfg_pull_default>, 655 <2 RK_PC3 3 &pcfg_pull_default>, 656 <2 RK_PD1 3 &pcfg_pull_default>; 657 }; 658 }; 659 660 hdmi { 661 hdmii2c_xfer: hdmii2c-xfer { 662 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 663 <0 RK_PA7 2 &pcfg_pull_none>; 664 }; 665 666 hdmi_hpd: hdmi-hpd { 667 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 668 }; 669 670 hdmi_cec: hdmi-cec { 671 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 672 }; 673 }; 674 675 i2c0 { 676 i2c0_xfer: i2c0-xfer { 677 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 678 <0 RK_PA1 1 &pcfg_pull_none>; 679 }; 680 }; 681 682 i2c1 { 683 i2c1_xfer: i2c1-xfer { 684 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 685 <0 RK_PA3 1 &pcfg_pull_none>; 686 }; 687 }; 688 689 i2c2 { 690 i2c2_xfer: i2c2-xfer { 691 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 692 <2 RK_PC5 3 &pcfg_pull_none>; 693 }; 694 }; 695 696 i2c3 { 697 i2c3_xfer: i2c3-xfer { 698 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 699 <0 RK_PA7 1 &pcfg_pull_none>; 700 }; 701 }; 702 703 i2s { 704 i2s_bus: i2s-bus { 705 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 706 <0 RK_PB1 1 &pcfg_pull_none>, 707 <0 RK_PB3 1 &pcfg_pull_none>, 708 <0 RK_PB4 1 &pcfg_pull_none>, 709 <0 RK_PB5 1 &pcfg_pull_none>, 710 <0 RK_PB6 1 &pcfg_pull_none>; 711 }; 712 713 i2s1_bus: i2s1-bus { 714 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 715 <1 RK_PA1 1 &pcfg_pull_none>, 716 <1 RK_PA2 1 &pcfg_pull_none>, 717 <1 RK_PA3 1 &pcfg_pull_none>, 718 <1 RK_PA4 1 &pcfg_pull_none>, 719 <1 RK_PA5 1 &pcfg_pull_none>; 720 }; 721 }; 722 723 lcdc { 724 lcdc_dclk: lcdc-dclk { 725 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 726 }; 727 728 lcdc_den: lcdc-den { 729 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 730 }; 731 732 lcdc_hsync: lcdc-hsync { 733 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 734 }; 735 736 lcdc_vsync: lcdc-vsync { 737 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 738 }; 739 740 lcdc_rgb24: lcdc-rgb24 { 741 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 742 <2 RK_PB5 1 &pcfg_pull_none>, 743 <2 RK_PB6 1 &pcfg_pull_none>, 744 <2 RK_PB7 1 &pcfg_pull_none>, 745 <2 RK_PC0 1 &pcfg_pull_none>, 746 <2 RK_PC1 1 &pcfg_pull_none>, 747 <2 RK_PC2 1 &pcfg_pull_none>, 748 <2 RK_PC3 1 &pcfg_pull_none>, 749 <2 RK_PC4 1 &pcfg_pull_none>, 750 <2 RK_PC5 1 &pcfg_pull_none>, 751 <2 RK_PC6 1 &pcfg_pull_none>, 752 <2 RK_PC7 1 &pcfg_pull_none>, 753 <2 RK_PD0 1 &pcfg_pull_none>, 754 <2 RK_PD1 1 &pcfg_pull_none>; 755 }; 756 }; 757 758 nfc { 759 flash_ale: flash-ale { 760 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 761 }; 762 763 flash_cle: flash-cle { 764 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 765 }; 766 767 flash_wrn: flash-wrn { 768 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 769 }; 770 771 flash_rdn: flash-rdn { 772 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 773 }; 774 775 flash_rdy: flash-rdy { 776 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 777 }; 778 779 flash_cs0: flash-cs0 { 780 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 781 }; 782 783 flash_dqs: flash-dqs { 784 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 785 }; 786 787 flash_bus8: flash-bus8 { 788 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 789 <1 RK_PD1 1 &pcfg_pull_none>, 790 <1 RK_PD2 1 &pcfg_pull_none>, 791 <1 RK_PD3 1 &pcfg_pull_none>, 792 <1 RK_PD4 1 &pcfg_pull_none>, 793 <1 RK_PD5 1 &pcfg_pull_none>, 794 <1 RK_PD6 1 &pcfg_pull_none>, 795 <1 RK_PD7 1 &pcfg_pull_none>; 796 }; 797 }; 798 799 pwm0 { 800 pwm0_pin: pwm0-pin { 801 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 802 }; 803 }; 804 805 pwm1 { 806 pwm1_pin: pwm1-pin { 807 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 808 }; 809 }; 810 811 pwm2 { 812 pwm2_pin: pwm2-pin { 813 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 814 }; 815 }; 816 817 pwm3 { 818 pwm3_pin: pwm3-pin { 819 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 820 }; 821 }; 822 823 sdio { 824 sdio_clk: sdio-clk { 825 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 826 }; 827 828 sdio_cmd: sdio-cmd { 829 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 830 }; 831 832 sdio_pwren: sdio-pwren { 833 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 834 }; 835 836 sdio_bus4: sdio-bus4 { 837 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 838 <1 RK_PA2 2 &pcfg_pull_default>, 839 <1 RK_PA4 2 &pcfg_pull_default>, 840 <1 RK_PA5 2 &pcfg_pull_default>; 841 }; 842 }; 843 844 sdmmc { 845 sdmmc_clk: sdmmc-clk { 846 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 847 }; 848 849 sdmmc_cmd: sdmmc-cmd { 850 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 851 }; 852 853 sdmmc_det: sdmmc-det { 854 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 855 }; 856 857 sdmmc_wp: sdmmc-wp { 858 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 859 }; 860 861 sdmmc_pwren: sdmmc-pwren { 862 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 863 }; 864 865 sdmmc_bus4: sdmmc-bus4 { 866 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 867 <1 RK_PC3 1 &pcfg_pull_default>, 868 <1 RK_PC4 1 &pcfg_pull_default>, 869 <1 RK_PC5 1 &pcfg_pull_default>; 870 }; 871 }; 872 873 spdif { 874 spdif_tx: spdif-tx { 875 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 876 }; 877 }; 878 879 spi0 { 880 spi0_clk: spi0-clk { 881 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 882 }; 883 884 spi0_cs0: spi0-cs0 { 885 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 886 }; 887 888 spi0_tx: spi0-tx { 889 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 890 }; 891 892 spi0_rx: spi0-rx { 893 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 894 }; 895 896 spi0_cs1: spi0-cs1 { 897 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 898 }; 899 900 spi1_clk: spi1-clk { 901 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 902 }; 903 904 spi1_cs0: spi1-cs0 { 905 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 906 }; 907 908 spi1_tx: spi1-tx { 909 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 910 }; 911 912 spi1_rx: spi1-rx { 913 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 914 }; 915 916 spi1_cs1: spi1-cs1 { 917 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 918 }; 919 920 spi2_clk: spi2-clk { 921 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 922 }; 923 924 spi2_cs0: spi2-cs0 { 925 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 926 }; 927 928 spi2_tx: spi2-tx { 929 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 930 }; 931 932 spi2_rx: spi2-rx { 933 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 934 }; 935 }; 936 937 uart0 { 938 uart0_xfer: uart0-xfer { 939 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 940 <2 RK_PD3 2 &pcfg_pull_none>; 941 }; 942 943 uart0_cts: uart0-cts { 944 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 945 }; 946 947 uart0_rts: uart0-rts { 948 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 949 }; 950 }; 951 952 uart1 { 953 uart1_xfer: uart1-xfer { 954 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 955 <1 RK_PB2 2 &pcfg_pull_default>; 956 }; 957 958 uart1_cts: uart1-cts { 959 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 960 }; 961 962 uart1_rts: uart1-rts { 963 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 964 }; 965 }; 966 967 uart2 { 968 uart2_xfer: uart2-xfer { 969 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 970 <1 RK_PC3 2 &pcfg_pull_none>; 971 }; 972 973 uart2_cts: uart2-cts { 974 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 975 }; 976 977 uart2_rts: uart2-rts { 978 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 979 }; 980 }; 981 }; 982}; 983