1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 }; 32 33 arm-pmu { 34 compatible = "arm,cortex-a7-pmu"; 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "rockchip,rk3036-smp"; 46 47 cpu0: cpu@f00 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a7"; 50 reg = <0xf00>; 51 clock-latency = <40000>; 52 clocks = <&cru ARMCLK>; 53 resets = <&cru SRST_CORE0>; 54 operating-points-v2 = <&cpu_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu1: cpu@f01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf01>; 62 resets = <&cru SRST_CORE1>; 63 operating-points-v2 = <&cpu_opp_table>; 64 }; 65 66 cpu2: cpu@f02 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a7"; 69 reg = <0xf02>; 70 resets = <&cru SRST_CORE2>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 cpu3: cpu@f03 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 reg = <0xf03>; 78 resets = <&cru SRST_CORE3>; 79 operating-points-v2 = <&cpu_opp_table>; 80 }; 81 }; 82 83 cpu_opp_table: opp-table-0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-216000000 { 88 opp-hz = /bits/ 64 <216000000>; 89 opp-microvolt = <950000 950000 1325000>; 90 }; 91 opp-408000000 { 92 opp-hz = /bits/ 64 <408000000>; 93 opp-microvolt = <950000 950000 1325000>; 94 }; 95 opp-600000000 { 96 opp-hz = /bits/ 64 <600000000>; 97 opp-microvolt = <950000 950000 1325000>; 98 }; 99 opp-696000000 { 100 opp-hz = /bits/ 64 <696000000>; 101 opp-microvolt = <975000 975000 1325000>; 102 }; 103 opp-816000000 { 104 opp-hz = /bits/ 64 <816000000>; 105 opp-microvolt = <1075000 1075000 1325000>; 106 opp-suspend; 107 }; 108 opp-1008000000 { 109 opp-hz = /bits/ 64 <1008000000>; 110 opp-microvolt = <1200000 1200000 1325000>; 111 }; 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <1325000 1325000 1325000>; 115 }; 116 }; 117 118 display_subsystem: display-subsystem { 119 compatible = "rockchip,display-subsystem"; 120 ports = <&vop_out>; 121 status = "disabled"; 122 }; 123 124 gpu_opp_table: opp-table-1 { 125 compatible = "operating-points-v2"; 126 127 opp-200000000 { 128 opp-hz = /bits/ 64 <200000000>; 129 opp-microvolt = <975000 975000 1250000>; 130 }; 131 opp-300000000 { 132 opp-hz = /bits/ 64 <300000000>; 133 opp-microvolt = <1050000 1050000 1250000>; 134 }; 135 opp-400000000 { 136 opp-hz = /bits/ 64 <400000000>; 137 opp-microvolt = <1150000 1150000 1250000>; 138 }; 139 opp-480000000 { 140 opp-hz = /bits/ 64 <480000000>; 141 opp-microvolt = <1250000 1250000 1250000>; 142 }; 143 }; 144 145 timer { 146 compatible = "arm,armv7-timer"; 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151 arm,cpu-registers-not-fw-configured; 152 clock-frequency = <24000000>; 153 }; 154 155 xin24m: oscillator { 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-output-names = "xin24m"; 159 #clock-cells = <0>; 160 }; 161 162 imem: sram@10080000 { 163 compatible = "mmio-sram"; 164 reg = <0x10080000 0x2000>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0 0x10080000 0x2000>; 168 169 smp-sram@0 { 170 compatible = "rockchip,rk3066-smp-sram"; 171 reg = <0x00 0x10>; 172 }; 173 }; 174 175 gpu: gpu@10090000 { 176 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 177 reg = <0x10090000 0x10000>; 178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "gp", 185 "gpmmu", 186 "pp0", 187 "ppmmu0", 188 "pp1", 189 "ppmmu1"; 190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 191 clock-names = "bus", "core"; 192 operating-points-v2 = <&gpu_opp_table>; 193 resets = <&cru SRST_GPU>; 194 power-domains = <&power RK3128_PD_GPU>; 195 status = "disabled"; 196 }; 197 198 pmu: syscon@100a0000 { 199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 200 reg = <0x100a0000 0x1000>; 201 202 power: power-controller { 203 compatible = "rockchip,rk3128-power-controller"; 204 #power-domain-cells = <1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 power-domain@RK3128_PD_VIO { 209 reg = <RK3128_PD_VIO>; 210 clocks = <&cru ACLK_CIF>, 211 <&cru HCLK_CIF>, 212 <&cru DCLK_EBC>, 213 <&cru HCLK_EBC>, 214 <&cru ACLK_IEP>, 215 <&cru HCLK_IEP>, 216 <&cru ACLK_LCDC0>, 217 <&cru HCLK_LCDC0>, 218 <&cru PCLK_MIPI>, 219 <&cru PCLK_MIPIPHY>, 220 <&cru SCLK_MIPI_24M>, 221 <&cru ACLK_RGA>, 222 <&cru HCLK_RGA>, 223 <&cru ACLK_VIO0>, 224 <&cru ACLK_VIO1>, 225 <&cru HCLK_VIO>, 226 <&cru HCLK_VIO_H2P>, 227 <&cru DCLK_VOP>, 228 <&cru SCLK_VOP>; 229 pm_qos = <&qos_ebc>, 230 <&qos_iep>, 231 <&qos_lcdc>, 232 <&qos_rga>, 233 <&qos_vip>; 234 #power-domain-cells = <0>; 235 }; 236 237 power-domain@RK3128_PD_VIDEO { 238 reg = <RK3128_PD_VIDEO>; 239 clocks = <&cru ACLK_VDPU>, 240 <&cru HCLK_VDPU>, 241 <&cru ACLK_VEPU>, 242 <&cru HCLK_VEPU>, 243 <&cru SCLK_HEVC_CORE>; 244 pm_qos = <&qos_vpu>; 245 #power-domain-cells = <0>; 246 }; 247 248 power-domain@RK3128_PD_GPU { 249 reg = <RK3128_PD_GPU>; 250 clocks = <&cru ACLK_GPU>; 251 pm_qos = <&qos_gpu>; 252 #power-domain-cells = <0>; 253 }; 254 }; 255 }; 256 257 vop: vop@1010e000 { 258 compatible = "rockchip,rk3126-vop"; 259 reg = <0x1010e000 0x300>; 260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, 262 <&cru HCLK_LCDC0>; 263 clock-names = "aclk_vop", "dclk_vop", 264 "hclk_vop"; 265 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, 266 <&cru SRST_VOP_D>; 267 reset-names = "axi", "ahb", 268 "dclk"; 269 power-domains = <&power RK3128_PD_VIO>; 270 status = "disabled"; 271 272 vop_out: port { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 vop_out_hdmi: endpoint@0 { 277 reg = <0>; 278 remote-endpoint = <&hdmi_in_vop>; 279 }; 280 281 vop_out_dsi: endpoint@1 { 282 reg = <1>; 283 remote-endpoint = <&dsi_in_vop>; 284 }; 285 }; 286 }; 287 288 dsi: dsi@10110000 { 289 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; 290 reg = <0x10110000 0x4000>; 291 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru PCLK_MIPI>; 293 clock-names = "pclk"; 294 phys = <&dphy>; 295 phy-names = "dphy"; 296 power-domains = <&power RK3128_PD_VIO>; 297 resets = <&cru SRST_VIO_MIPI_DSI>; 298 reset-names = "apb"; 299 rockchip,grf = <&grf>; 300 status = "disabled"; 301 302 ports { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 306 dsi_in: port@0 { 307 reg = <0>; 308 309 dsi_in_vop: endpoint { 310 remote-endpoint = <&vop_out_dsi>; 311 }; 312 }; 313 314 dsi_out: port@1 { 315 reg = <1>; 316 }; 317 }; 318 }; 319 320 qos_gpu: qos@1012d000 { 321 compatible = "rockchip,rk3128-qos", "syscon"; 322 reg = <0x1012d000 0x20>; 323 }; 324 325 qos_vpu: qos@1012e000 { 326 compatible = "rockchip,rk3128-qos", "syscon"; 327 reg = <0x1012e000 0x20>; 328 }; 329 330 qos_rga: qos@1012f000 { 331 compatible = "rockchip,rk3128-qos", "syscon"; 332 reg = <0x1012f000 0x20>; 333 }; 334 335 qos_ebc: qos@1012f080 { 336 compatible = "rockchip,rk3128-qos", "syscon"; 337 reg = <0x1012f080 0x20>; 338 }; 339 340 qos_iep: qos@1012f100 { 341 compatible = "rockchip,rk3128-qos", "syscon"; 342 reg = <0x1012f100 0x20>; 343 }; 344 345 qos_lcdc: qos@1012f180 { 346 compatible = "rockchip,rk3128-qos", "syscon"; 347 reg = <0x1012f180 0x20>; 348 }; 349 350 qos_vip: qos@1012f200 { 351 compatible = "rockchip,rk3128-qos", "syscon"; 352 reg = <0x1012f200 0x20>; 353 }; 354 355 gic: interrupt-controller@10139000 { 356 compatible = "arm,cortex-a7-gic"; 357 reg = <0x10139000 0x1000>, 358 <0x1013a000 0x1000>, 359 <0x1013c000 0x2000>, 360 <0x1013e000 0x2000>; 361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 362 interrupt-controller; 363 #interrupt-cells = <3>; 364 #address-cells = <0>; 365 }; 366 367 usb_otg: usb@10180000 { 368 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 369 reg = <0x10180000 0x40000>; 370 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&cru HCLK_OTG>; 372 clock-names = "otg"; 373 dr_mode = "otg"; 374 g-np-tx-fifo-size = <16>; 375 g-rx-fifo-size = <280>; 376 g-tx-fifo-size = <256 128 128 64 32 16>; 377 phys = <&usb2phy_otg>; 378 phy-names = "usb2-phy"; 379 status = "disabled"; 380 }; 381 382 usb_host_ehci: usb@101c0000 { 383 compatible = "generic-ehci"; 384 reg = <0x101c0000 0x20000>; 385 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cru HCLK_HOST2>; 387 phys = <&usb2phy_host>; 388 phy-names = "usb"; 389 status = "disabled"; 390 }; 391 392 usb_host_ohci: usb@101e0000 { 393 compatible = "generic-ohci"; 394 reg = <0x101e0000 0x20000>; 395 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&cru HCLK_HOST2>; 397 phys = <&usb2phy_host>; 398 phy-names = "usb"; 399 status = "disabled"; 400 }; 401 402 i2s_8ch: i2s@10200000 { 403 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 404 reg = <0x10200000 0x1000>; 405 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>; 407 clock-names = "i2s_clk", "i2s_hclk"; 408 dmas = <&pdma 14>, <&pdma 15>; 409 dma-names = "tx", "rx"; 410 #sound-dai-cells = <0>; 411 status = "disabled"; 412 }; 413 414 sdmmc: mmc@10214000 { 415 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 416 reg = <0x10214000 0x4000>; 417 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 419 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 420 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 421 dmas = <&pdma 10>; 422 dma-names = "rx-tx"; 423 fifo-depth = <256>; 424 max-frequency = <150000000>; 425 resets = <&cru SRST_SDMMC>; 426 reset-names = "reset"; 427 status = "disabled"; 428 }; 429 430 sdio: mmc@10218000 { 431 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 432 reg = <0x10218000 0x4000>; 433 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 435 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 436 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 437 dmas = <&pdma 11>; 438 dma-names = "rx-tx"; 439 fifo-depth = <256>; 440 max-frequency = <150000000>; 441 resets = <&cru SRST_SDIO>; 442 reset-names = "reset"; 443 status = "disabled"; 444 }; 445 446 emmc: mmc@1021c000 { 447 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 448 reg = <0x1021c000 0x4000>; 449 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 451 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 452 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 453 dmas = <&pdma 12>; 454 dma-names = "rx-tx"; 455 fifo-depth = <256>; 456 max-frequency = <150000000>; 457 resets = <&cru SRST_EMMC>; 458 reset-names = "reset"; 459 status = "disabled"; 460 }; 461 462 i2s_2ch: i2s@10220000 { 463 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 464 reg = <0x10220000 0x1000>; 465 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>; 467 clock-names = "i2s_clk", "i2s_hclk"; 468 dmas = <&pdma 0>, <&pdma 1>; 469 dma-names = "tx", "rx"; 470 rockchip,playback-channels = <2>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&i2s_bus>; 473 #sound-dai-cells = <0>; 474 status = "disabled"; 475 }; 476 477 nfc: nand-controller@10500000 { 478 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 479 reg = <0x10500000 0x4000>; 480 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 482 clock-names = "ahb", "nfc"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 485 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 486 status = "disabled"; 487 }; 488 489 cru: clock-controller@20000000 { 490 compatible = "rockchip,rk3128-cru"; 491 reg = <0x20000000 0x1000>; 492 clocks = <&xin24m>; 493 clock-names = "xin24m"; 494 rockchip,grf = <&grf>; 495 #clock-cells = <1>; 496 #reset-cells = <1>; 497 assigned-clocks = <&cru PLL_GPLL>; 498 assigned-clock-rates = <594000000>; 499 }; 500 501 grf: syscon@20008000 { 502 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 503 reg = <0x20008000 0x1000>; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 507 usb2phy: usb2phy@17c { 508 compatible = "rockchip,rk3128-usb2phy"; 509 reg = <0x017c 0x0c>; 510 clocks = <&cru SCLK_OTGPHY0>; 511 clock-names = "phyclk"; 512 clock-output-names = "usb480m_phy"; 513 assigned-clocks = <&cru SCLK_USB480M>; 514 assigned-clock-parents = <&usb2phy>; 515 #clock-cells = <0>; 516 status = "disabled"; 517 518 usb2phy_host: host-port { 519 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 520 interrupt-names = "linestate"; 521 #phy-cells = <0>; 522 status = "disabled"; 523 }; 524 525 usb2phy_otg: otg-port { 526 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 529 interrupt-names = "otg-bvalid", "otg-id", 530 "linestate"; 531 #phy-cells = <0>; 532 status = "disabled"; 533 }; 534 }; 535 }; 536 537 hdmi: hdmi@20034000 { 538 compatible = "rockchip,rk3128-inno-hdmi"; 539 reg = <0x20034000 0x4000>; 540 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; 542 clock-names = "pclk", "ref"; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 545 power-domains = <&power RK3128_PD_VIO>; 546 status = "disabled"; 547 548 ports { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 552 hdmi_in: port@0 { 553 reg = <0>; 554 hdmi_in_vop: endpoint { 555 remote-endpoint = <&vop_out_hdmi>; 556 }; 557 }; 558 559 hdmi_out: port@1 { 560 reg = <1>; 561 }; 562 }; 563 }; 564 565 dphy: phy@20038000 { 566 compatible = "rockchip,rk3128-dsi-dphy"; 567 reg = <0x20038000 0x4000>; 568 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; 569 clock-names = "ref", "pclk"; 570 #phy-cells = <0>; 571 power-domains = <&power RK3128_PD_VIO>; 572 resets = <&cru SRST_MIPIPHY_P>; 573 reset-names = "apb"; 574 status = "disabled"; 575 }; 576 577 timer0: timer@20044000 { 578 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 579 reg = <0x20044000 0x20>; 580 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 582 clock-names = "pclk", "timer"; 583 }; 584 585 timer1: timer@20044020 { 586 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 587 reg = <0x20044020 0x20>; 588 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 590 clock-names = "pclk", "timer"; 591 }; 592 593 timer2: timer@20044040 { 594 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 595 reg = <0x20044040 0x20>; 596 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 598 clock-names = "pclk", "timer"; 599 }; 600 601 timer3: timer@20044060 { 602 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 603 reg = <0x20044060 0x20>; 604 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 606 clock-names = "pclk", "timer"; 607 }; 608 609 timer4: timer@20044080 { 610 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 611 reg = <0x20044080 0x20>; 612 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 614 clock-names = "pclk", "timer"; 615 }; 616 617 timer5: timer@200440a0 { 618 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 619 reg = <0x200440a0 0x20>; 620 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 622 clock-names = "pclk", "timer"; 623 }; 624 625 watchdog: watchdog@2004c000 { 626 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 627 reg = <0x2004c000 0x100>; 628 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cru PCLK_WDT>; 630 status = "disabled"; 631 }; 632 633 pwm0: pwm@20050000 { 634 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 635 reg = <0x20050000 0x10>; 636 clocks = <&cru PCLK_PWM>; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pwm0_pin>; 639 #pwm-cells = <3>; 640 status = "disabled"; 641 }; 642 643 pwm1: pwm@20050010 { 644 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 645 reg = <0x20050010 0x10>; 646 clocks = <&cru PCLK_PWM>; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&pwm1_pin>; 649 #pwm-cells = <3>; 650 status = "disabled"; 651 }; 652 653 pwm2: pwm@20050020 { 654 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 655 reg = <0x20050020 0x10>; 656 clocks = <&cru PCLK_PWM>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&pwm2_pin>; 659 #pwm-cells = <3>; 660 status = "disabled"; 661 }; 662 663 pwm3: pwm@20050030 { 664 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 665 reg = <0x20050030 0x10>; 666 clocks = <&cru PCLK_PWM>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pwm3_pin>; 669 #pwm-cells = <3>; 670 status = "disabled"; 671 }; 672 673 i2c1: i2c@20056000 { 674 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 675 reg = <0x20056000 0x1000>; 676 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 677 clock-names = "i2c"; 678 clocks = <&cru PCLK_I2C1>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&i2c1_xfer>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 status = "disabled"; 684 }; 685 686 i2c2: i2c@2005a000 { 687 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 688 reg = <0x2005a000 0x1000>; 689 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 690 clock-names = "i2c"; 691 clocks = <&cru PCLK_I2C2>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&i2c2_xfer>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 status = "disabled"; 697 }; 698 699 i2c3: i2c@2005e000 { 700 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 701 reg = <0x2005e000 0x1000>; 702 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 703 clock-names = "i2c"; 704 clocks = <&cru PCLK_I2C3>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&i2c3_xfer>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 status = "disabled"; 710 }; 711 712 uart0: serial@20060000 { 713 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 714 reg = <0x20060000 0x100>; 715 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 716 clock-frequency = <24000000>; 717 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 718 clock-names = "baudclk", "apb_pclk"; 719 dmas = <&pdma 2>, <&pdma 3>; 720 dma-names = "tx", "rx"; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 723 reg-io-width = <4>; 724 reg-shift = <2>; 725 status = "disabled"; 726 }; 727 728 uart1: serial@20064000 { 729 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 730 reg = <0x20064000 0x100>; 731 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 732 clock-frequency = <24000000>; 733 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 734 clock-names = "baudclk", "apb_pclk"; 735 dmas = <&pdma 4>, <&pdma 5>; 736 dma-names = "tx", "rx"; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&uart1_xfer>; 739 reg-io-width = <4>; 740 reg-shift = <2>; 741 status = "disabled"; 742 }; 743 744 uart2: serial@20068000 { 745 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 746 reg = <0x20068000 0x100>; 747 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 748 clock-frequency = <24000000>; 749 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 750 clock-names = "baudclk", "apb_pclk"; 751 dmas = <&pdma 6>, <&pdma 7>; 752 dma-names = "tx", "rx"; 753 pinctrl-names = "default"; 754 pinctrl-0 = <&uart2_xfer>; 755 reg-io-width = <4>; 756 reg-shift = <2>; 757 status = "disabled"; 758 }; 759 760 saradc: saradc@2006c000 { 761 compatible = "rockchip,saradc"; 762 reg = <0x2006c000 0x100>; 763 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 765 clock-names = "saradc", "apb_pclk"; 766 resets = <&cru SRST_SARADC>; 767 reset-names = "saradc-apb"; 768 #io-channel-cells = <1>; 769 status = "disabled"; 770 }; 771 772 i2c0: i2c@20072000 { 773 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 774 reg = <0x20072000 0x1000>; 775 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 776 clock-names = "i2c"; 777 clocks = <&cru PCLK_I2C0>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&i2c0_xfer>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 status = "disabled"; 783 }; 784 785 spi0: spi@20074000 { 786 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 787 reg = <0x20074000 0x1000>; 788 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 790 clock-names = "spiclk", "apb_pclk"; 791 dmas = <&pdma 8>, <&pdma 9>; 792 dma-names = "tx", "rx"; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 status = "disabled"; 798 }; 799 800 pdma: dma-controller@20078000 { 801 compatible = "arm,pl330", "arm,primecell"; 802 reg = <0x20078000 0x4000>; 803 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 805 arm,pl330-broken-no-flushp; 806 arm,pl330-periph-burst; 807 clocks = <&cru ACLK_DMAC>; 808 clock-names = "apb_pclk"; 809 #dma-cells = <1>; 810 }; 811 812 gmac: ethernet@2008c000 { 813 compatible = "rockchip,rk3128-gmac"; 814 reg = <0x2008c000 0x4000>; 815 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "macirq", "eth_wake_irq"; 818 clocks = <&cru SCLK_MAC>, 819 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 820 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 821 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 822 clock-names = "stmmaceth", 823 "mac_clk_rx", "mac_clk_tx", 824 "clk_mac_ref", "clk_mac_refout", 825 "aclk_mac", "pclk_mac"; 826 resets = <&cru SRST_GMAC>; 827 reset-names = "stmmaceth"; 828 rockchip,grf = <&grf>; 829 rx-fifo-depth = <4096>; 830 tx-fifo-depth = <2048>; 831 status = "disabled"; 832 833 mdio: mdio { 834 compatible = "snps,dwmac-mdio"; 835 #address-cells = <0x1>; 836 #size-cells = <0x0>; 837 }; 838 }; 839 840 pinctrl: pinctrl { 841 compatible = "rockchip,rk3128-pinctrl"; 842 rockchip,grf = <&grf>; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 ranges; 846 847 gpio0: gpio@2007c000 { 848 compatible = "rockchip,gpio-bank"; 849 reg = <0x2007c000 0x100>; 850 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&cru PCLK_GPIO0>; 852 gpio-controller; 853 #gpio-cells = <2>; 854 interrupt-controller; 855 #interrupt-cells = <2>; 856 }; 857 858 gpio1: gpio@20080000 { 859 compatible = "rockchip,gpio-bank"; 860 reg = <0x20080000 0x100>; 861 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&cru PCLK_GPIO1>; 863 gpio-controller; 864 #gpio-cells = <2>; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 }; 868 869 gpio2: gpio@20084000 { 870 compatible = "rockchip,gpio-bank"; 871 reg = <0x20084000 0x100>; 872 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cru PCLK_GPIO2>; 874 gpio-controller; 875 #gpio-cells = <2>; 876 interrupt-controller; 877 #interrupt-cells = <2>; 878 }; 879 880 gpio3: gpio@20088000 { 881 compatible = "rockchip,gpio-bank"; 882 reg = <0x20088000 0x100>; 883 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&cru PCLK_GPIO3>; 885 gpio-controller; 886 #gpio-cells = <2>; 887 interrupt-controller; 888 #interrupt-cells = <2>; 889 }; 890 891 pcfg_pull_default: pcfg-pull-default { 892 bias-pull-pin-default; 893 }; 894 895 pcfg_pull_none: pcfg-pull-none { 896 bias-disable; 897 }; 898 899 emmc { 900 emmc_clk: emmc-clk { 901 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 902 }; 903 904 emmc_cmd: emmc-cmd { 905 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 906 }; 907 908 emmc_cmd1: emmc-cmd1 { 909 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 910 }; 911 912 emmc_pwr: emmc-pwr { 913 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 914 }; 915 916 emmc_bus1: emmc-bus1 { 917 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 918 }; 919 920 emmc_bus4: emmc-bus4 { 921 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 922 <1 RK_PD1 2 &pcfg_pull_default>, 923 <1 RK_PD2 2 &pcfg_pull_default>, 924 <1 RK_PD3 2 &pcfg_pull_default>; 925 }; 926 927 emmc_bus8: emmc-bus8 { 928 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 929 <1 RK_PD1 2 &pcfg_pull_default>, 930 <1 RK_PD2 2 &pcfg_pull_default>, 931 <1 RK_PD3 2 &pcfg_pull_default>, 932 <1 RK_PD4 2 &pcfg_pull_default>, 933 <1 RK_PD5 2 &pcfg_pull_default>, 934 <1 RK_PD6 2 &pcfg_pull_default>, 935 <1 RK_PD7 2 &pcfg_pull_default>; 936 }; 937 }; 938 939 gmac { 940 rgmii_pins: rgmii-pins { 941 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 942 <2 RK_PB1 3 &pcfg_pull_default>, 943 <2 RK_PB3 3 &pcfg_pull_default>, 944 <2 RK_PB4 3 &pcfg_pull_default>, 945 <2 RK_PB5 3 &pcfg_pull_default>, 946 <2 RK_PB6 3 &pcfg_pull_default>, 947 <2 RK_PC0 3 &pcfg_pull_default>, 948 <2 RK_PC1 3 &pcfg_pull_default>, 949 <2 RK_PC2 3 &pcfg_pull_default>, 950 <2 RK_PC3 3 &pcfg_pull_default>, 951 <2 RK_PD1 3 &pcfg_pull_default>, 952 <2 RK_PC4 4 &pcfg_pull_default>, 953 <2 RK_PC5 4 &pcfg_pull_default>, 954 <2 RK_PC6 4 &pcfg_pull_default>, 955 <2 RK_PC7 4 &pcfg_pull_default>; 956 }; 957 958 rmii_pins: rmii-pins { 959 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 960 <2 RK_PB4 3 &pcfg_pull_default>, 961 <2 RK_PB5 3 &pcfg_pull_default>, 962 <2 RK_PB6 3 &pcfg_pull_default>, 963 <2 RK_PB7 3 &pcfg_pull_default>, 964 <2 RK_PC0 3 &pcfg_pull_default>, 965 <2 RK_PC1 3 &pcfg_pull_default>, 966 <2 RK_PC2 3 &pcfg_pull_default>, 967 <2 RK_PC3 3 &pcfg_pull_default>, 968 <2 RK_PD1 3 &pcfg_pull_default>; 969 }; 970 }; 971 972 hdmi { 973 hdmii2c_xfer: hdmii2c-xfer { 974 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 975 <0 RK_PA7 2 &pcfg_pull_none>; 976 }; 977 978 hdmi_hpd: hdmi-hpd { 979 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 980 }; 981 982 hdmi_cec: hdmi-cec { 983 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 984 }; 985 }; 986 987 i2c0 { 988 i2c0_xfer: i2c0-xfer { 989 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 990 <0 RK_PA1 1 &pcfg_pull_none>; 991 }; 992 }; 993 994 i2c1 { 995 i2c1_xfer: i2c1-xfer { 996 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 997 <0 RK_PA3 1 &pcfg_pull_none>; 998 }; 999 }; 1000 1001 i2c2 { 1002 i2c2_xfer: i2c2-xfer { 1003 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 1004 <2 RK_PC5 3 &pcfg_pull_none>; 1005 }; 1006 }; 1007 1008 i2c3 { 1009 i2c3_xfer: i2c3-xfer { 1010 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1011 <0 RK_PA7 1 &pcfg_pull_none>; 1012 }; 1013 }; 1014 1015 i2s { 1016 i2s_bus: i2s-bus { 1017 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1018 <0 RK_PB1 1 &pcfg_pull_none>, 1019 <0 RK_PB3 1 &pcfg_pull_none>, 1020 <0 RK_PB4 1 &pcfg_pull_none>, 1021 <0 RK_PB5 1 &pcfg_pull_none>, 1022 <0 RK_PB6 1 &pcfg_pull_none>; 1023 }; 1024 1025 i2s1_bus: i2s1-bus { 1026 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 1027 <1 RK_PA1 1 &pcfg_pull_none>, 1028 <1 RK_PA2 1 &pcfg_pull_none>, 1029 <1 RK_PA3 1 &pcfg_pull_none>, 1030 <1 RK_PA4 1 &pcfg_pull_none>, 1031 <1 RK_PA5 1 &pcfg_pull_none>; 1032 }; 1033 }; 1034 1035 lcdc { 1036 lcdc_dclk: lcdc-dclk { 1037 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 1038 }; 1039 1040 lcdc_den: lcdc-den { 1041 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 1042 }; 1043 1044 lcdc_hsync: lcdc-hsync { 1045 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1046 }; 1047 1048 lcdc_vsync: lcdc-vsync { 1049 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 1050 }; 1051 1052 lcdc_rgb24: lcdc-rgb24 { 1053 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 1054 <2 RK_PB5 1 &pcfg_pull_none>, 1055 <2 RK_PB6 1 &pcfg_pull_none>, 1056 <2 RK_PB7 1 &pcfg_pull_none>, 1057 <2 RK_PC0 1 &pcfg_pull_none>, 1058 <2 RK_PC1 1 &pcfg_pull_none>, 1059 <2 RK_PC2 1 &pcfg_pull_none>, 1060 <2 RK_PC3 1 &pcfg_pull_none>, 1061 <2 RK_PC4 1 &pcfg_pull_none>, 1062 <2 RK_PC5 1 &pcfg_pull_none>, 1063 <2 RK_PC6 1 &pcfg_pull_none>, 1064 <2 RK_PC7 1 &pcfg_pull_none>, 1065 <2 RK_PD0 1 &pcfg_pull_none>, 1066 <2 RK_PD1 1 &pcfg_pull_none>; 1067 }; 1068 }; 1069 1070 nfc { 1071 flash_ale: flash-ale { 1072 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 1073 }; 1074 1075 flash_cle: flash-cle { 1076 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 1077 }; 1078 1079 flash_wrn: flash-wrn { 1080 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1081 }; 1082 1083 flash_rdn: flash-rdn { 1084 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 1085 }; 1086 1087 flash_rdy: flash-rdy { 1088 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1089 }; 1090 1091 flash_cs0: flash-cs0 { 1092 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1093 }; 1094 1095 flash_dqs: flash-dqs { 1096 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 1097 }; 1098 1099 flash_bus8: flash-bus8 { 1100 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1101 <1 RK_PD1 1 &pcfg_pull_none>, 1102 <1 RK_PD2 1 &pcfg_pull_none>, 1103 <1 RK_PD3 1 &pcfg_pull_none>, 1104 <1 RK_PD4 1 &pcfg_pull_none>, 1105 <1 RK_PD5 1 &pcfg_pull_none>, 1106 <1 RK_PD6 1 &pcfg_pull_none>, 1107 <1 RK_PD7 1 &pcfg_pull_none>; 1108 }; 1109 }; 1110 1111 pwm0 { 1112 pwm0_pin: pwm0-pin { 1113 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 1114 }; 1115 }; 1116 1117 pwm1 { 1118 pwm1_pin: pwm1-pin { 1119 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1120 }; 1121 }; 1122 1123 pwm2 { 1124 pwm2_pin: pwm2-pin { 1125 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1126 }; 1127 }; 1128 1129 pwm3 { 1130 pwm3_pin: pwm3-pin { 1131 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 1132 }; 1133 }; 1134 1135 sdio { 1136 sdio_clk: sdio-clk { 1137 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1138 }; 1139 1140 sdio_cmd: sdio-cmd { 1141 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1142 }; 1143 1144 sdio_pwren: sdio-pwren { 1145 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1146 }; 1147 1148 sdio_bus4: sdio-bus4 { 1149 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1150 <1 RK_PA2 2 &pcfg_pull_default>, 1151 <1 RK_PA4 2 &pcfg_pull_default>, 1152 <1 RK_PA5 2 &pcfg_pull_default>; 1153 }; 1154 }; 1155 1156 sdmmc { 1157 sdmmc_clk: sdmmc-clk { 1158 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1159 }; 1160 1161 sdmmc_cmd: sdmmc-cmd { 1162 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1163 }; 1164 1165 sdmmc_det: sdmmc-det { 1166 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1167 }; 1168 1169 sdmmc_wp: sdmmc-wp { 1170 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1171 }; 1172 1173 sdmmc_pwren: sdmmc-pwren { 1174 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 1175 }; 1176 1177 sdmmc_bus4: sdmmc-bus4 { 1178 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1179 <1 RK_PC3 1 &pcfg_pull_default>, 1180 <1 RK_PC4 1 &pcfg_pull_default>, 1181 <1 RK_PC5 1 &pcfg_pull_default>; 1182 }; 1183 }; 1184 1185 spdif { 1186 spdif_tx: spdif-tx { 1187 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1188 }; 1189 }; 1190 1191 spi0 { 1192 spi0_clk: spi0-clk { 1193 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1194 }; 1195 1196 spi0_cs0: spi0-cs0 { 1197 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1198 }; 1199 1200 spi0_tx: spi0-tx { 1201 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1202 }; 1203 1204 spi0_rx: spi0-rx { 1205 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1206 }; 1207 1208 spi0_cs1: spi0-cs1 { 1209 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1210 }; 1211 1212 spi1_clk: spi1-clk { 1213 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1214 }; 1215 1216 spi1_cs0: spi1-cs0 { 1217 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1218 }; 1219 1220 spi1_tx: spi1-tx { 1221 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1222 }; 1223 1224 spi1_rx: spi1-rx { 1225 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1226 }; 1227 1228 spi1_cs1: spi1-cs1 { 1229 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1230 }; 1231 1232 spi2_clk: spi2-clk { 1233 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1234 }; 1235 1236 spi2_cs0: spi2-cs0 { 1237 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1238 }; 1239 1240 spi2_tx: spi2-tx { 1241 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1242 }; 1243 1244 spi2_rx: spi2-rx { 1245 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1246 }; 1247 }; 1248 1249 uart0 { 1250 uart0_xfer: uart0-xfer { 1251 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1252 <2 RK_PD3 2 &pcfg_pull_none>; 1253 }; 1254 1255 uart0_cts: uart0-cts { 1256 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1257 }; 1258 1259 uart0_rts: uart0-rts { 1260 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1261 }; 1262 }; 1263 1264 uart1 { 1265 uart1_xfer: uart1-xfer { 1266 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1267 <1 RK_PB2 2 &pcfg_pull_default>; 1268 }; 1269 1270 uart1_cts: uart1-cts { 1271 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1272 }; 1273 1274 uart1_rts: uart1-rts { 1275 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1276 }; 1277 }; 1278 1279 uart2 { 1280 uart2_xfer: uart2-xfer { 1281 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1282 <1 RK_PC3 2 &pcfg_pull_none>; 1283 }; 1284 1285 uart2_cts: uart2-cts { 1286 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1287 }; 1288 1289 uart2_rts: uart2-rts { 1290 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1291 }; 1292 }; 1293 }; 1294}; 1295