1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 arm-pmu { 20 compatible = "arm,cortex-a7-pmu"; 21 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 25 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 enable-method = "rockchip,rk3036-smp"; 32 33 cpu0: cpu@f00 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a7"; 36 reg = <0xf00>; 37 clock-latency = <40000>; 38 clocks = <&cru ARMCLK>; 39 resets = <&cru SRST_CORE0>; 40 operating-points-v2 = <&cpu_opp_table>; 41 #cooling-cells = <2>; /* min followed by max */ 42 }; 43 44 cpu1: cpu@f01 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a7"; 47 reg = <0xf01>; 48 resets = <&cru SRST_CORE1>; 49 operating-points-v2 = <&cpu_opp_table>; 50 }; 51 52 cpu2: cpu@f02 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0xf02>; 56 resets = <&cru SRST_CORE2>; 57 operating-points-v2 = <&cpu_opp_table>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 operating-points-v2 = <&cpu_opp_table>; 66 }; 67 }; 68 69 cpu_opp_table: opp-table-0 { 70 compatible = "operating-points-v2"; 71 opp-shared; 72 73 opp-216000000 { 74 opp-hz = /bits/ 64 <216000000>; 75 opp-microvolt = <950000 950000 1325000>; 76 }; 77 opp-408000000 { 78 opp-hz = /bits/ 64 <408000000>; 79 opp-microvolt = <950000 950000 1325000>; 80 }; 81 opp-600000000 { 82 opp-hz = /bits/ 64 <600000000>; 83 opp-microvolt = <950000 950000 1325000>; 84 }; 85 opp-696000000 { 86 opp-hz = /bits/ 64 <696000000>; 87 opp-microvolt = <975000 975000 1325000>; 88 }; 89 opp-816000000 { 90 opp-hz = /bits/ 64 <816000000>; 91 opp-microvolt = <1075000 1075000 1325000>; 92 opp-suspend; 93 }; 94 opp-1008000000 { 95 opp-hz = /bits/ 64 <1008000000>; 96 opp-microvolt = <1200000 1200000 1325000>; 97 }; 98 opp-1200000000 { 99 opp-hz = /bits/ 64 <1200000000>; 100 opp-microvolt = <1325000 1325000 1325000>; 101 }; 102 }; 103 104 timer { 105 compatible = "arm,armv7-timer"; 106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 arm,cpu-registers-not-fw-configured; 111 clock-frequency = <24000000>; 112 }; 113 114 xin24m: oscillator { 115 compatible = "fixed-clock"; 116 clock-frequency = <24000000>; 117 clock-output-names = "xin24m"; 118 #clock-cells = <0>; 119 }; 120 121 imem: sram@10080000 { 122 compatible = "mmio-sram"; 123 reg = <0x10080000 0x2000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0 0x10080000 0x2000>; 127 128 smp-sram@0 { 129 compatible = "rockchip,rk3066-smp-sram"; 130 reg = <0x00 0x10>; 131 }; 132 }; 133 134 pmu: syscon@100a0000 { 135 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 136 reg = <0x100a0000 0x1000>; 137 138 power: power-controller { 139 compatible = "rockchip,rk3128-power-controller"; 140 #power-domain-cells = <1>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 power-domain@RK3128_PD_VIO { 145 reg = <RK3128_PD_VIO>; 146 clocks = <&cru ACLK_CIF>, 147 <&cru HCLK_CIF>, 148 <&cru DCLK_EBC>, 149 <&cru HCLK_EBC>, 150 <&cru ACLK_IEP>, 151 <&cru HCLK_IEP>, 152 <&cru ACLK_LCDC0>, 153 <&cru HCLK_LCDC0>, 154 <&cru PCLK_MIPI>, 155 <&cru ACLK_RGA>, 156 <&cru HCLK_RGA>, 157 <&cru ACLK_VIO0>, 158 <&cru ACLK_VIO1>, 159 <&cru HCLK_VIO>, 160 <&cru HCLK_VIO_H2P>, 161 <&cru DCLK_VOP>, 162 <&cru SCLK_VOP>; 163 pm_qos = <&qos_ebc>, 164 <&qos_iep>, 165 <&qos_lcdc>, 166 <&qos_rga>, 167 <&qos_vip>; 168 #power-domain-cells = <0>; 169 }; 170 171 power-domain@RK3128_PD_VIDEO { 172 reg = <RK3128_PD_VIDEO>; 173 clocks = <&cru ACLK_VDPU>, 174 <&cru HCLK_VDPU>, 175 <&cru ACLK_VEPU>, 176 <&cru HCLK_VEPU>, 177 <&cru SCLK_HEVC_CORE>; 178 pm_qos = <&qos_vpu>; 179 #power-domain-cells = <0>; 180 }; 181 182 power-domain@RK3128_PD_GPU { 183 reg = <RK3128_PD_GPU>; 184 clocks = <&cru ACLK_GPU>; 185 pm_qos = <&qos_gpu>; 186 #power-domain-cells = <0>; 187 }; 188 }; 189 }; 190 191 qos_gpu: qos@1012d000 { 192 compatible = "rockchip,rk3128-qos", "syscon"; 193 reg = <0x1012d000 0x20>; 194 }; 195 196 qos_vpu: qos@1012e000 { 197 compatible = "rockchip,rk3128-qos", "syscon"; 198 reg = <0x1012e000 0x20>; 199 }; 200 201 qos_rga: qos@1012f000 { 202 compatible = "rockchip,rk3128-qos", "syscon"; 203 reg = <0x1012f000 0x20>; 204 }; 205 206 qos_ebc: qos@1012f080 { 207 compatible = "rockchip,rk3128-qos", "syscon"; 208 reg = <0x1012f080 0x20>; 209 }; 210 211 qos_iep: qos@1012f100 { 212 compatible = "rockchip,rk3128-qos", "syscon"; 213 reg = <0x1012f100 0x20>; 214 }; 215 216 qos_lcdc: qos@1012f180 { 217 compatible = "rockchip,rk3128-qos", "syscon"; 218 reg = <0x1012f180 0x20>; 219 }; 220 221 qos_vip: qos@1012f200 { 222 compatible = "rockchip,rk3128-qos", "syscon"; 223 reg = <0x1012f200 0x20>; 224 }; 225 226 gic: interrupt-controller@10139000 { 227 compatible = "arm,cortex-a7-gic"; 228 reg = <0x10139000 0x1000>, 229 <0x1013a000 0x1000>, 230 <0x1013c000 0x2000>, 231 <0x1013e000 0x2000>; 232 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 233 interrupt-controller; 234 #interrupt-cells = <3>; 235 #address-cells = <0>; 236 }; 237 238 usb_otg: usb@10180000 { 239 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 240 reg = <0x10180000 0x40000>; 241 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cru HCLK_OTG>; 243 clock-names = "otg"; 244 dr_mode = "otg"; 245 g-np-tx-fifo-size = <16>; 246 g-rx-fifo-size = <280>; 247 g-tx-fifo-size = <256 128 128 64 32 16>; 248 phys = <&usb2phy_otg>; 249 phy-names = "usb2-phy"; 250 status = "disabled"; 251 }; 252 253 usb_host_ehci: usb@101c0000 { 254 compatible = "generic-ehci"; 255 reg = <0x101c0000 0x20000>; 256 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&cru HCLK_HOST2>; 258 phys = <&usb2phy_host>; 259 phy-names = "usb"; 260 status = "disabled"; 261 }; 262 263 usb_host_ohci: usb@101e0000 { 264 compatible = "generic-ohci"; 265 reg = <0x101e0000 0x20000>; 266 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cru HCLK_HOST2>; 268 phys = <&usb2phy_host>; 269 phy-names = "usb"; 270 status = "disabled"; 271 }; 272 273 sdmmc: mmc@10214000 { 274 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 275 reg = <0x10214000 0x4000>; 276 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 278 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 279 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 280 dmas = <&pdma 10>; 281 dma-names = "rx-tx"; 282 fifo-depth = <256>; 283 max-frequency = <150000000>; 284 resets = <&cru SRST_SDMMC>; 285 reset-names = "reset"; 286 status = "disabled"; 287 }; 288 289 sdio: mmc@10218000 { 290 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 291 reg = <0x10218000 0x4000>; 292 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 294 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 295 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 296 dmas = <&pdma 11>; 297 dma-names = "rx-tx"; 298 fifo-depth = <256>; 299 max-frequency = <150000000>; 300 resets = <&cru SRST_SDIO>; 301 reset-names = "reset"; 302 status = "disabled"; 303 }; 304 305 emmc: mmc@1021c000 { 306 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 307 reg = <0x1021c000 0x4000>; 308 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 310 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 311 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 312 dmas = <&pdma 12>; 313 dma-names = "rx-tx"; 314 fifo-depth = <256>; 315 max-frequency = <150000000>; 316 resets = <&cru SRST_EMMC>; 317 reset-names = "reset"; 318 status = "disabled"; 319 }; 320 321 nfc: nand-controller@10500000 { 322 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 323 reg = <0x10500000 0x4000>; 324 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 326 clock-names = "ahb", "nfc"; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 329 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 330 status = "disabled"; 331 }; 332 333 cru: clock-controller@20000000 { 334 compatible = "rockchip,rk3128-cru"; 335 reg = <0x20000000 0x1000>; 336 clocks = <&xin24m>; 337 clock-names = "xin24m"; 338 rockchip,grf = <&grf>; 339 #clock-cells = <1>; 340 #reset-cells = <1>; 341 assigned-clocks = <&cru PLL_GPLL>; 342 assigned-clock-rates = <594000000>; 343 }; 344 345 grf: syscon@20008000 { 346 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 347 reg = <0x20008000 0x1000>; 348 #address-cells = <1>; 349 #size-cells = <1>; 350 351 usb2phy: usb2phy@17c { 352 compatible = "rockchip,rk3128-usb2phy"; 353 reg = <0x017c 0x0c>; 354 clocks = <&cru SCLK_OTGPHY0>; 355 clock-names = "phyclk"; 356 clock-output-names = "usb480m_phy"; 357 assigned-clocks = <&cru SCLK_USB480M>; 358 assigned-clock-parents = <&usb2phy>; 359 #clock-cells = <0>; 360 status = "disabled"; 361 362 usb2phy_host: host-port { 363 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 364 interrupt-names = "linestate"; 365 #phy-cells = <0>; 366 status = "disabled"; 367 }; 368 369 usb2phy_otg: otg-port { 370 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 373 interrupt-names = "otg-bvalid", "otg-id", 374 "linestate"; 375 #phy-cells = <0>; 376 status = "disabled"; 377 }; 378 }; 379 }; 380 381 timer0: timer@20044000 { 382 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 383 reg = <0x20044000 0x20>; 384 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 386 clock-names = "pclk", "timer"; 387 }; 388 389 timer1: timer@20044020 { 390 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 391 reg = <0x20044020 0x20>; 392 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 394 clock-names = "pclk", "timer"; 395 }; 396 397 timer2: timer@20044040 { 398 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 399 reg = <0x20044040 0x20>; 400 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 402 clock-names = "pclk", "timer"; 403 }; 404 405 timer3: timer@20044060 { 406 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 407 reg = <0x20044060 0x20>; 408 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 410 clock-names = "pclk", "timer"; 411 }; 412 413 timer4: timer@20044080 { 414 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 415 reg = <0x20044080 0x20>; 416 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 418 clock-names = "pclk", "timer"; 419 }; 420 421 timer5: timer@200440a0 { 422 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 423 reg = <0x200440a0 0x20>; 424 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 426 clock-names = "pclk", "timer"; 427 }; 428 429 watchdog: watchdog@2004c000 { 430 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 431 reg = <0x2004c000 0x100>; 432 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cru PCLK_WDT>; 434 status = "disabled"; 435 }; 436 437 pwm0: pwm@20050000 { 438 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 439 reg = <0x20050000 0x10>; 440 clocks = <&cru PCLK_PWM>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pwm0_pin>; 443 #pwm-cells = <3>; 444 status = "disabled"; 445 }; 446 447 pwm1: pwm@20050010 { 448 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 449 reg = <0x20050010 0x10>; 450 clocks = <&cru PCLK_PWM>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pwm1_pin>; 453 #pwm-cells = <3>; 454 status = "disabled"; 455 }; 456 457 pwm2: pwm@20050020 { 458 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 459 reg = <0x20050020 0x10>; 460 clocks = <&cru PCLK_PWM>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pwm2_pin>; 463 #pwm-cells = <3>; 464 status = "disabled"; 465 }; 466 467 pwm3: pwm@20050030 { 468 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 469 reg = <0x20050030 0x10>; 470 clocks = <&cru PCLK_PWM>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm3_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 i2c1: i2c@20056000 { 478 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 479 reg = <0x20056000 0x1000>; 480 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 481 clock-names = "i2c"; 482 clocks = <&cru PCLK_I2C1>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&i2c1_xfer>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 status = "disabled"; 488 }; 489 490 i2c2: i2c@2005a000 { 491 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 492 reg = <0x2005a000 0x1000>; 493 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 494 clock-names = "i2c"; 495 clocks = <&cru PCLK_I2C2>; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&i2c2_xfer>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 status = "disabled"; 501 }; 502 503 i2c3: i2c@2005e000 { 504 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 505 reg = <0x2005e000 0x1000>; 506 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 507 clock-names = "i2c"; 508 clocks = <&cru PCLK_I2C3>; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&i2c3_xfer>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 status = "disabled"; 514 }; 515 516 uart0: serial@20060000 { 517 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 518 reg = <0x20060000 0x100>; 519 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 520 clock-frequency = <24000000>; 521 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 522 clock-names = "baudclk", "apb_pclk"; 523 dmas = <&pdma 2>, <&pdma 3>; 524 dma-names = "tx", "rx"; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 527 reg-io-width = <4>; 528 reg-shift = <2>; 529 status = "disabled"; 530 }; 531 532 uart1: serial@20064000 { 533 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 534 reg = <0x20064000 0x100>; 535 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 536 clock-frequency = <24000000>; 537 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 538 clock-names = "baudclk", "apb_pclk"; 539 dmas = <&pdma 4>, <&pdma 5>; 540 dma-names = "tx", "rx"; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&uart1_xfer>; 543 reg-io-width = <4>; 544 reg-shift = <2>; 545 status = "disabled"; 546 }; 547 548 uart2: serial@20068000 { 549 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 550 reg = <0x20068000 0x100>; 551 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 552 clock-frequency = <24000000>; 553 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 554 clock-names = "baudclk", "apb_pclk"; 555 dmas = <&pdma 6>, <&pdma 7>; 556 dma-names = "tx", "rx"; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&uart2_xfer>; 559 reg-io-width = <4>; 560 reg-shift = <2>; 561 status = "disabled"; 562 }; 563 564 saradc: saradc@2006c000 { 565 compatible = "rockchip,saradc"; 566 reg = <0x2006c000 0x100>; 567 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 569 clock-names = "saradc", "apb_pclk"; 570 resets = <&cru SRST_SARADC>; 571 reset-names = "saradc-apb"; 572 #io-channel-cells = <1>; 573 status = "disabled"; 574 }; 575 576 i2c0: i2c@20072000 { 577 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 578 reg = <0x20072000 0x1000>; 579 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 580 clock-names = "i2c"; 581 clocks = <&cru PCLK_I2C0>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&i2c0_xfer>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 589 spi0: spi@20074000 { 590 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 591 reg = <0x20074000 0x1000>; 592 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 594 clock-names = "spiclk", "apb_pclk"; 595 dmas = <&pdma 8>, <&pdma 9>; 596 dma-names = "tx", "rx"; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 pdma: dma-controller@20078000 { 605 compatible = "arm,pl330", "arm,primecell"; 606 reg = <0x20078000 0x4000>; 607 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 609 arm,pl330-broken-no-flushp; 610 arm,pl330-periph-burst; 611 clocks = <&cru ACLK_DMAC>; 612 clock-names = "apb_pclk"; 613 #dma-cells = <1>; 614 }; 615 616 gmac: ethernet@2008c000 { 617 compatible = "rockchip,rk3128-gmac"; 618 reg = <0x2008c000 0x4000>; 619 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "macirq", "eth_wake_irq"; 622 clocks = <&cru SCLK_MAC>, 623 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 624 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 625 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 626 clock-names = "stmmaceth", 627 "mac_clk_rx", "mac_clk_tx", 628 "clk_mac_ref", "clk_mac_refout", 629 "aclk_mac", "pclk_mac"; 630 resets = <&cru SRST_GMAC>; 631 reset-names = "stmmaceth"; 632 rockchip,grf = <&grf>; 633 rx-fifo-depth = <4096>; 634 tx-fifo-depth = <2048>; 635 status = "disabled"; 636 637 mdio: mdio { 638 compatible = "snps,dwmac-mdio"; 639 #address-cells = <0x1>; 640 #size-cells = <0x0>; 641 }; 642 }; 643 644 pinctrl: pinctrl { 645 compatible = "rockchip,rk3128-pinctrl"; 646 rockchip,grf = <&grf>; 647 #address-cells = <1>; 648 #size-cells = <1>; 649 ranges; 650 651 gpio0: gpio@2007c000 { 652 compatible = "rockchip,gpio-bank"; 653 reg = <0x2007c000 0x100>; 654 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&cru PCLK_GPIO0>; 656 gpio-controller; 657 #gpio-cells = <2>; 658 interrupt-controller; 659 #interrupt-cells = <2>; 660 }; 661 662 gpio1: gpio@20080000 { 663 compatible = "rockchip,gpio-bank"; 664 reg = <0x20080000 0x100>; 665 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cru PCLK_GPIO1>; 667 gpio-controller; 668 #gpio-cells = <2>; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 673 gpio2: gpio@20084000 { 674 compatible = "rockchip,gpio-bank"; 675 reg = <0x20084000 0x100>; 676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cru PCLK_GPIO2>; 678 gpio-controller; 679 #gpio-cells = <2>; 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 684 gpio3: gpio@20088000 { 685 compatible = "rockchip,gpio-bank"; 686 reg = <0x20088000 0x100>; 687 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cru PCLK_GPIO3>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 695 pcfg_pull_default: pcfg-pull-default { 696 bias-pull-pin-default; 697 }; 698 699 pcfg_pull_none: pcfg-pull-none { 700 bias-disable; 701 }; 702 703 emmc { 704 emmc_clk: emmc-clk { 705 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 706 }; 707 708 emmc_cmd: emmc-cmd { 709 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 710 }; 711 712 emmc_cmd1: emmc-cmd1 { 713 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 714 }; 715 716 emmc_pwr: emmc-pwr { 717 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 718 }; 719 720 emmc_bus1: emmc-bus1 { 721 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 722 }; 723 724 emmc_bus4: emmc-bus4 { 725 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 726 <1 RK_PD1 2 &pcfg_pull_default>, 727 <1 RK_PD2 2 &pcfg_pull_default>, 728 <1 RK_PD3 2 &pcfg_pull_default>; 729 }; 730 731 emmc_bus8: emmc-bus8 { 732 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 733 <1 RK_PD1 2 &pcfg_pull_default>, 734 <1 RK_PD2 2 &pcfg_pull_default>, 735 <1 RK_PD3 2 &pcfg_pull_default>, 736 <1 RK_PD4 2 &pcfg_pull_default>, 737 <1 RK_PD5 2 &pcfg_pull_default>, 738 <1 RK_PD6 2 &pcfg_pull_default>, 739 <1 RK_PD7 2 &pcfg_pull_default>; 740 }; 741 }; 742 743 gmac { 744 rgmii_pins: rgmii-pins { 745 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 746 <2 RK_PB1 3 &pcfg_pull_default>, 747 <2 RK_PB3 3 &pcfg_pull_default>, 748 <2 RK_PB4 3 &pcfg_pull_default>, 749 <2 RK_PB5 3 &pcfg_pull_default>, 750 <2 RK_PB6 3 &pcfg_pull_default>, 751 <2 RK_PC0 3 &pcfg_pull_default>, 752 <2 RK_PC1 3 &pcfg_pull_default>, 753 <2 RK_PC2 3 &pcfg_pull_default>, 754 <2 RK_PC3 3 &pcfg_pull_default>, 755 <2 RK_PD1 3 &pcfg_pull_default>, 756 <2 RK_PC4 4 &pcfg_pull_default>, 757 <2 RK_PC5 4 &pcfg_pull_default>, 758 <2 RK_PC6 4 &pcfg_pull_default>, 759 <2 RK_PC7 4 &pcfg_pull_default>; 760 }; 761 762 rmii_pins: rmii-pins { 763 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 764 <2 RK_PB4 3 &pcfg_pull_default>, 765 <2 RK_PB5 3 &pcfg_pull_default>, 766 <2 RK_PB6 3 &pcfg_pull_default>, 767 <2 RK_PB7 3 &pcfg_pull_default>, 768 <2 RK_PC0 3 &pcfg_pull_default>, 769 <2 RK_PC1 3 &pcfg_pull_default>, 770 <2 RK_PC2 3 &pcfg_pull_default>, 771 <2 RK_PC3 3 &pcfg_pull_default>, 772 <2 RK_PD1 3 &pcfg_pull_default>; 773 }; 774 }; 775 776 hdmi { 777 hdmii2c_xfer: hdmii2c-xfer { 778 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 779 <0 RK_PA7 2 &pcfg_pull_none>; 780 }; 781 782 hdmi_hpd: hdmi-hpd { 783 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 784 }; 785 786 hdmi_cec: hdmi-cec { 787 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 788 }; 789 }; 790 791 i2c0 { 792 i2c0_xfer: i2c0-xfer { 793 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 794 <0 RK_PA1 1 &pcfg_pull_none>; 795 }; 796 }; 797 798 i2c1 { 799 i2c1_xfer: i2c1-xfer { 800 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 801 <0 RK_PA3 1 &pcfg_pull_none>; 802 }; 803 }; 804 805 i2c2 { 806 i2c2_xfer: i2c2-xfer { 807 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 808 <2 RK_PC5 3 &pcfg_pull_none>; 809 }; 810 }; 811 812 i2c3 { 813 i2c3_xfer: i2c3-xfer { 814 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 815 <0 RK_PA7 1 &pcfg_pull_none>; 816 }; 817 }; 818 819 i2s { 820 i2s_bus: i2s-bus { 821 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 822 <0 RK_PB1 1 &pcfg_pull_none>, 823 <0 RK_PB3 1 &pcfg_pull_none>, 824 <0 RK_PB4 1 &pcfg_pull_none>, 825 <0 RK_PB5 1 &pcfg_pull_none>, 826 <0 RK_PB6 1 &pcfg_pull_none>; 827 }; 828 829 i2s1_bus: i2s1-bus { 830 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 831 <1 RK_PA1 1 &pcfg_pull_none>, 832 <1 RK_PA2 1 &pcfg_pull_none>, 833 <1 RK_PA3 1 &pcfg_pull_none>, 834 <1 RK_PA4 1 &pcfg_pull_none>, 835 <1 RK_PA5 1 &pcfg_pull_none>; 836 }; 837 }; 838 839 lcdc { 840 lcdc_dclk: lcdc-dclk { 841 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 842 }; 843 844 lcdc_den: lcdc-den { 845 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 846 }; 847 848 lcdc_hsync: lcdc-hsync { 849 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 850 }; 851 852 lcdc_vsync: lcdc-vsync { 853 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 854 }; 855 856 lcdc_rgb24: lcdc-rgb24 { 857 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 858 <2 RK_PB5 1 &pcfg_pull_none>, 859 <2 RK_PB6 1 &pcfg_pull_none>, 860 <2 RK_PB7 1 &pcfg_pull_none>, 861 <2 RK_PC0 1 &pcfg_pull_none>, 862 <2 RK_PC1 1 &pcfg_pull_none>, 863 <2 RK_PC2 1 &pcfg_pull_none>, 864 <2 RK_PC3 1 &pcfg_pull_none>, 865 <2 RK_PC4 1 &pcfg_pull_none>, 866 <2 RK_PC5 1 &pcfg_pull_none>, 867 <2 RK_PC6 1 &pcfg_pull_none>, 868 <2 RK_PC7 1 &pcfg_pull_none>, 869 <2 RK_PD0 1 &pcfg_pull_none>, 870 <2 RK_PD1 1 &pcfg_pull_none>; 871 }; 872 }; 873 874 nfc { 875 flash_ale: flash-ale { 876 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 877 }; 878 879 flash_cle: flash-cle { 880 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 881 }; 882 883 flash_wrn: flash-wrn { 884 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 885 }; 886 887 flash_rdn: flash-rdn { 888 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 889 }; 890 891 flash_rdy: flash-rdy { 892 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 893 }; 894 895 flash_cs0: flash-cs0 { 896 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 897 }; 898 899 flash_dqs: flash-dqs { 900 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 901 }; 902 903 flash_bus8: flash-bus8 { 904 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 905 <1 RK_PD1 1 &pcfg_pull_none>, 906 <1 RK_PD2 1 &pcfg_pull_none>, 907 <1 RK_PD3 1 &pcfg_pull_none>, 908 <1 RK_PD4 1 &pcfg_pull_none>, 909 <1 RK_PD5 1 &pcfg_pull_none>, 910 <1 RK_PD6 1 &pcfg_pull_none>, 911 <1 RK_PD7 1 &pcfg_pull_none>; 912 }; 913 }; 914 915 pwm0 { 916 pwm0_pin: pwm0-pin { 917 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 918 }; 919 }; 920 921 pwm1 { 922 pwm1_pin: pwm1-pin { 923 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 924 }; 925 }; 926 927 pwm2 { 928 pwm2_pin: pwm2-pin { 929 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 930 }; 931 }; 932 933 pwm3 { 934 pwm3_pin: pwm3-pin { 935 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 936 }; 937 }; 938 939 sdio { 940 sdio_clk: sdio-clk { 941 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 942 }; 943 944 sdio_cmd: sdio-cmd { 945 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 946 }; 947 948 sdio_pwren: sdio-pwren { 949 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 950 }; 951 952 sdio_bus4: sdio-bus4 { 953 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 954 <1 RK_PA2 2 &pcfg_pull_default>, 955 <1 RK_PA4 2 &pcfg_pull_default>, 956 <1 RK_PA5 2 &pcfg_pull_default>; 957 }; 958 }; 959 960 sdmmc { 961 sdmmc_clk: sdmmc-clk { 962 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 963 }; 964 965 sdmmc_cmd: sdmmc-cmd { 966 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 967 }; 968 969 sdmmc_det: sdmmc-det { 970 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 971 }; 972 973 sdmmc_wp: sdmmc-wp { 974 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 975 }; 976 977 sdmmc_pwren: sdmmc-pwren { 978 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 979 }; 980 981 sdmmc_bus4: sdmmc-bus4 { 982 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 983 <1 RK_PC3 1 &pcfg_pull_default>, 984 <1 RK_PC4 1 &pcfg_pull_default>, 985 <1 RK_PC5 1 &pcfg_pull_default>; 986 }; 987 }; 988 989 spdif { 990 spdif_tx: spdif-tx { 991 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 992 }; 993 }; 994 995 spi0 { 996 spi0_clk: spi0-clk { 997 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 998 }; 999 1000 spi0_cs0: spi0-cs0 { 1001 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1002 }; 1003 1004 spi0_tx: spi0-tx { 1005 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1006 }; 1007 1008 spi0_rx: spi0-rx { 1009 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1010 }; 1011 1012 spi0_cs1: spi0-cs1 { 1013 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1014 }; 1015 1016 spi1_clk: spi1-clk { 1017 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1018 }; 1019 1020 spi1_cs0: spi1-cs0 { 1021 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1022 }; 1023 1024 spi1_tx: spi1-tx { 1025 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1026 }; 1027 1028 spi1_rx: spi1-rx { 1029 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1030 }; 1031 1032 spi1_cs1: spi1-cs1 { 1033 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1034 }; 1035 1036 spi2_clk: spi2-clk { 1037 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1038 }; 1039 1040 spi2_cs0: spi2-cs0 { 1041 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1042 }; 1043 1044 spi2_tx: spi2-tx { 1045 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1046 }; 1047 1048 spi2_rx: spi2-rx { 1049 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1050 }; 1051 }; 1052 1053 uart0 { 1054 uart0_xfer: uart0-xfer { 1055 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1056 <2 RK_PD3 2 &pcfg_pull_none>; 1057 }; 1058 1059 uart0_cts: uart0-cts { 1060 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1061 }; 1062 1063 uart0_rts: uart0-rts { 1064 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1065 }; 1066 }; 1067 1068 uart1 { 1069 uart1_xfer: uart1-xfer { 1070 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1071 <1 RK_PB2 2 &pcfg_pull_default>; 1072 }; 1073 1074 uart1_cts: uart1-cts { 1075 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1076 }; 1077 1078 uart1_rts: uart1-rts { 1079 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1080 }; 1081 }; 1082 1083 uart2 { 1084 uart2_xfer: uart2-xfer { 1085 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1086 <1 RK_PC3 2 &pcfg_pull_none>; 1087 }; 1088 1089 uart2_cts: uart2-cts { 1090 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1091 }; 1092 1093 uart2_rts: uart2-rts { 1094 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1095 }; 1096 }; 1097 }; 1098}; 1099