1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 enable-method = "rockchip,rk3036-smp"; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 resets = <&cru SRST_CORE0>; 39 operating-points = < 40 /* KHz uV */ 41 816000 1000000 42 >; 43 #cooling-cells = <2>; /* min followed by max */ 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 resets = <&cru SRST_CORE1>; 51 }; 52 53 cpu2: cpu@f02 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf02>; 57 resets = <&cru SRST_CORE2>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 }; 66 }; 67 68 timer { 69 compatible = "arm,armv7-timer"; 70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 73 arm,cpu-registers-not-fw-configured; 74 clock-frequency = <24000000>; 75 }; 76 77 xin24m: oscillator { 78 compatible = "fixed-clock"; 79 clock-frequency = <24000000>; 80 clock-output-names = "xin24m"; 81 #clock-cells = <0>; 82 }; 83 84 imem: sram@10080000 { 85 compatible = "mmio-sram"; 86 reg = <0x10080000 0x2000>; 87 #address-cells = <1>; 88 #size-cells = <1>; 89 ranges = <0 0x10080000 0x2000>; 90 91 smp-sram@0 { 92 compatible = "rockchip,rk3066-smp-sram"; 93 reg = <0x00 0x10>; 94 }; 95 }; 96 97 pmu: syscon@100a0000 { 98 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 99 reg = <0x100a0000 0x1000>; 100 }; 101 102 gic: interrupt-controller@10139000 { 103 compatible = "arm,cortex-a7-gic"; 104 reg = <0x10139000 0x1000>, 105 <0x1013a000 0x1000>, 106 <0x1013c000 0x2000>, 107 <0x1013e000 0x2000>; 108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 interrupt-controller; 110 #interrupt-cells = <3>; 111 #address-cells = <0>; 112 }; 113 114 usb_otg: usb@10180000 { 115 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 116 reg = <0x10180000 0x40000>; 117 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&cru HCLK_OTG>; 119 clock-names = "otg"; 120 dr_mode = "otg"; 121 phys = <&usb2phy_otg>; 122 phy-names = "usb2-phy"; 123 status = "disabled"; 124 }; 125 126 usb_host_ehci: usb@101c0000 { 127 compatible = "generic-ehci"; 128 reg = <0x101c0000 0x20000>; 129 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 130 phys = <&usb2phy_host>; 131 phy-names = "usb"; 132 status = "disabled"; 133 }; 134 135 usb_host_ohci: usb@101e0000 { 136 compatible = "generic-ohci"; 137 reg = <0x101e0000 0x20000>; 138 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 139 phys = <&usb2phy_host>; 140 phy-names = "usb"; 141 status = "disabled"; 142 }; 143 144 sdmmc: mmc@10214000 { 145 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 146 reg = <0x10214000 0x4000>; 147 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 149 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 150 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 151 dmas = <&pdma 10>; 152 dma-names = "rx-tx"; 153 fifo-depth = <256>; 154 max-frequency = <150000000>; 155 resets = <&cru SRST_SDMMC>; 156 reset-names = "reset"; 157 status = "disabled"; 158 }; 159 160 sdio: mmc@10218000 { 161 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 162 reg = <0x10218000 0x4000>; 163 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 165 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 166 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 167 dmas = <&pdma 11>; 168 dma-names = "rx-tx"; 169 fifo-depth = <256>; 170 max-frequency = <150000000>; 171 resets = <&cru SRST_SDIO>; 172 reset-names = "reset"; 173 status = "disabled"; 174 }; 175 176 emmc: mmc@1021c000 { 177 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 178 reg = <0x1021c000 0x4000>; 179 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 181 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 182 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 183 dmas = <&pdma 12>; 184 dma-names = "rx-tx"; 185 fifo-depth = <256>; 186 max-frequency = <150000000>; 187 resets = <&cru SRST_EMMC>; 188 reset-names = "reset"; 189 status = "disabled"; 190 }; 191 192 nfc: nand-controller@10500000 { 193 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 194 reg = <0x10500000 0x4000>; 195 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 197 clock-names = "ahb", "nfc"; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 200 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 201 status = "disabled"; 202 }; 203 204 cru: clock-controller@20000000 { 205 compatible = "rockchip,rk3128-cru"; 206 reg = <0x20000000 0x1000>; 207 clocks = <&xin24m>; 208 clock-names = "xin24m"; 209 rockchip,grf = <&grf>; 210 #clock-cells = <1>; 211 #reset-cells = <1>; 212 assigned-clocks = <&cru PLL_GPLL>; 213 assigned-clock-rates = <594000000>; 214 }; 215 216 grf: syscon@20008000 { 217 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 218 reg = <0x20008000 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 222 usb2phy: usb2phy@17c { 223 compatible = "rockchip,rk3128-usb2phy"; 224 reg = <0x017c 0x0c>; 225 clocks = <&cru SCLK_OTGPHY0>; 226 clock-names = "phyclk"; 227 clock-output-names = "usb480m_phy"; 228 #clock-cells = <0>; 229 status = "disabled"; 230 231 usb2phy_host: host-port { 232 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-names = "linestate"; 234 #phy-cells = <0>; 235 status = "disabled"; 236 }; 237 238 usb2phy_otg: otg-port { 239 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 242 interrupt-names = "otg-bvalid", "otg-id", 243 "linestate"; 244 #phy-cells = <0>; 245 status = "disabled"; 246 }; 247 }; 248 }; 249 250 timer0: timer@20044000 { 251 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 252 reg = <0x20044000 0x20>; 253 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru PCLK_TIMER>, <&xin24m>; 255 clock-names = "pclk", "timer"; 256 }; 257 258 timer1: timer@20044020 { 259 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 260 reg = <0x20044020 0x20>; 261 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cru PCLK_TIMER>, <&xin24m>; 263 clock-names = "pclk", "timer"; 264 }; 265 266 timer2: timer@20044040 { 267 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 268 reg = <0x20044040 0x20>; 269 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cru PCLK_TIMER>, <&xin24m>; 271 clock-names = "pclk", "timer"; 272 }; 273 274 timer3: timer@20044060 { 275 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 276 reg = <0x20044060 0x20>; 277 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&cru PCLK_TIMER>, <&xin24m>; 279 clock-names = "pclk", "timer"; 280 }; 281 282 timer4: timer@20044080 { 283 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 284 reg = <0x20044080 0x20>; 285 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cru PCLK_TIMER>, <&xin24m>; 287 clock-names = "pclk", "timer"; 288 }; 289 290 timer5: timer@200440a0 { 291 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 292 reg = <0x200440a0 0x20>; 293 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cru PCLK_TIMER>, <&xin24m>; 295 clock-names = "pclk", "timer"; 296 }; 297 298 watchdog: watchdog@2004c000 { 299 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 300 reg = <0x2004c000 0x100>; 301 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cru PCLK_WDT>; 303 status = "disabled"; 304 }; 305 306 pwm0: pwm@20050000 { 307 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 308 reg = <0x20050000 0x10>; 309 clocks = <&cru PCLK_PWM>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pwm0_pin>; 312 #pwm-cells = <3>; 313 status = "disabled"; 314 }; 315 316 pwm1: pwm@20050010 { 317 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 318 reg = <0x20050010 0x10>; 319 clocks = <&cru PCLK_PWM>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pwm1_pin>; 322 #pwm-cells = <3>; 323 status = "disabled"; 324 }; 325 326 pwm2: pwm@20050020 { 327 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 328 reg = <0x20050020 0x10>; 329 clocks = <&cru PCLK_PWM>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pwm2_pin>; 332 #pwm-cells = <3>; 333 status = "disabled"; 334 }; 335 336 pwm3: pwm@20050030 { 337 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 338 reg = <0x20050030 0x10>; 339 clocks = <&cru PCLK_PWM>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pwm3_pin>; 342 #pwm-cells = <3>; 343 status = "disabled"; 344 }; 345 346 i2c1: i2c@20056000 { 347 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 348 reg = <0x20056000 0x1000>; 349 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 350 clock-names = "i2c"; 351 clocks = <&cru PCLK_I2C1>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&i2c1_xfer>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 359 i2c2: i2c@2005a000 { 360 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 361 reg = <0x2005a000 0x1000>; 362 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 363 clock-names = "i2c"; 364 clocks = <&cru PCLK_I2C2>; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&i2c2_xfer>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 i2c3: i2c@2005e000 { 373 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 374 reg = <0x2005e000 0x1000>; 375 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 376 clock-names = "i2c"; 377 clocks = <&cru PCLK_I2C3>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&i2c3_xfer>; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 status = "disabled"; 383 }; 384 385 uart0: serial@20060000 { 386 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 387 reg = <0x20060000 0x100>; 388 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 389 clock-frequency = <24000000>; 390 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 391 clock-names = "baudclk", "apb_pclk"; 392 dmas = <&pdma 2>, <&pdma 3>; 393 dma-names = "tx", "rx"; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 396 reg-io-width = <4>; 397 reg-shift = <2>; 398 status = "disabled"; 399 }; 400 401 uart1: serial@20064000 { 402 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 403 reg = <0x20064000 0x100>; 404 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 405 clock-frequency = <24000000>; 406 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 407 clock-names = "baudclk", "apb_pclk"; 408 dmas = <&pdma 4>, <&pdma 5>; 409 dma-names = "tx", "rx"; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&uart1_xfer>; 412 reg-io-width = <4>; 413 reg-shift = <2>; 414 status = "disabled"; 415 }; 416 417 uart2: serial@20068000 { 418 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 419 reg = <0x20068000 0x100>; 420 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <24000000>; 422 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 423 clock-names = "baudclk", "apb_pclk"; 424 dmas = <&pdma 6>, <&pdma 7>; 425 dma-names = "tx", "rx"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&uart2_xfer>; 428 reg-io-width = <4>; 429 reg-shift = <2>; 430 status = "disabled"; 431 }; 432 433 saradc: saradc@2006c000 { 434 compatible = "rockchip,saradc"; 435 reg = <0x2006c000 0x100>; 436 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 438 clock-names = "saradc", "apb_pclk"; 439 resets = <&cru SRST_SARADC>; 440 reset-names = "saradc-apb"; 441 #io-channel-cells = <1>; 442 status = "disabled"; 443 }; 444 445 i2c0: i2c@20072000 { 446 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 447 reg = <20072000 0x1000>; 448 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 449 clock-names = "i2c"; 450 clocks = <&cru PCLK_I2C0>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&i2c0_xfer>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 status = "disabled"; 456 }; 457 458 spi0: spi@20074000 { 459 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 460 reg = <0x20074000 0x1000>; 461 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 463 clock-names = "spiclk", "apb_pclk"; 464 dmas = <&pdma 8>, <&pdma 9>; 465 dma-names = "tx", "rx"; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 status = "disabled"; 471 }; 472 473 pdma: dma-controller@20078000 { 474 compatible = "arm,pl330", "arm,primecell"; 475 reg = <0x20078000 0x4000>; 476 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 478 arm,pl330-broken-no-flushp; 479 clocks = <&cru ACLK_DMAC>; 480 clock-names = "apb_pclk"; 481 #dma-cells = <1>; 482 }; 483 484 pinctrl: pinctrl { 485 compatible = "rockchip,rk3128-pinctrl"; 486 rockchip,grf = <&grf>; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 ranges; 490 491 gpio0: gpio@2007c000 { 492 compatible = "rockchip,gpio-bank"; 493 reg = <0x2007c000 0x100>; 494 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&cru PCLK_GPIO0>; 496 gpio-controller; 497 #gpio-cells = <2>; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 }; 501 502 gpio1: gpio@20080000 { 503 compatible = "rockchip,gpio-bank"; 504 reg = <0x20080000 0x100>; 505 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cru PCLK_GPIO1>; 507 gpio-controller; 508 #gpio-cells = <2>; 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 }; 512 513 gpio2: gpio@20084000 { 514 compatible = "rockchip,gpio-bank"; 515 reg = <0x20084000 0x100>; 516 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cru PCLK_GPIO2>; 518 gpio-controller; 519 #gpio-cells = <2>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 }; 523 524 gpio3: gpio@20088000 { 525 compatible = "rockchip,gpio-bank"; 526 reg = <0x20088000 0x100>; 527 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&cru PCLK_GPIO3>; 529 gpio-controller; 530 #gpio-cells = <2>; 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 }; 534 535 pcfg_pull_default: pcfg-pull-default { 536 bias-pull-pin-default; 537 }; 538 539 pcfg_pull_none: pcfg-pull-none { 540 bias-disable; 541 }; 542 543 emmc { 544 emmc_clk: emmc-clk { 545 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 546 }; 547 548 emmc_cmd: emmc-cmd { 549 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 550 }; 551 552 emmc_cmd1: emmc-cmd1 { 553 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 554 }; 555 556 emmc_pwr: emmc-pwr { 557 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 558 }; 559 560 emmc_bus1: emmc-bus1 { 561 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 562 }; 563 564 emmc_bus4: emmc-bus4 { 565 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 566 <1 RK_PD1 2 &pcfg_pull_default>, 567 <1 RK_PD2 2 &pcfg_pull_default>, 568 <1 RK_PD3 2 &pcfg_pull_default>; 569 }; 570 571 emmc_bus8: emmc-bus8 { 572 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 573 <1 RK_PD1 2 &pcfg_pull_default>, 574 <1 RK_PD2 2 &pcfg_pull_default>, 575 <1 RK_PD3 2 &pcfg_pull_default>, 576 <1 RK_PD4 2 &pcfg_pull_default>, 577 <1 RK_PD5 2 &pcfg_pull_default>, 578 <1 RK_PD6 2 &pcfg_pull_default>, 579 <1 RK_PD7 2 &pcfg_pull_default>; 580 }; 581 }; 582 583 gmac { 584 rgmii_pins: rgmii-pins { 585 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 586 <2 RK_PB1 3 &pcfg_pull_default>, 587 <2 RK_PB3 3 &pcfg_pull_default>, 588 <2 RK_PB4 3 &pcfg_pull_default>, 589 <2 RK_PB5 3 &pcfg_pull_default>, 590 <2 RK_PB6 3 &pcfg_pull_default>, 591 <2 RK_PC0 3 &pcfg_pull_default>, 592 <2 RK_PC1 3 &pcfg_pull_default>, 593 <2 RK_PC2 3 &pcfg_pull_default>, 594 <2 RK_PC3 3 &pcfg_pull_default>, 595 <2 RK_PD1 3 &pcfg_pull_default>, 596 <2 RK_PC4 4 &pcfg_pull_default>, 597 <2 RK_PC5 4 &pcfg_pull_default>, 598 <2 RK_PC6 4 &pcfg_pull_default>, 599 <2 RK_PC7 4 &pcfg_pull_default>; 600 }; 601 602 rmii_pins: rmii-pins { 603 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 604 <2 RK_PB4 3 &pcfg_pull_default>, 605 <2 RK_PB5 3 &pcfg_pull_default>, 606 <2 RK_PB6 3 &pcfg_pull_default>, 607 <2 RK_PB7 3 &pcfg_pull_default>, 608 <2 RK_PC0 3 &pcfg_pull_default>, 609 <2 RK_PC1 3 &pcfg_pull_default>, 610 <2 RK_PC2 3 &pcfg_pull_default>, 611 <2 RK_PC3 3 &pcfg_pull_default>, 612 <2 RK_PD1 3 &pcfg_pull_default>; 613 }; 614 }; 615 616 hdmi { 617 hdmii2c_xfer: hdmii2c-xfer { 618 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 619 <0 RK_PA7 2 &pcfg_pull_none>; 620 }; 621 622 hdmi_hpd: hdmi-hpd { 623 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 624 }; 625 626 hdmi_cec: hdmi-cec { 627 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 628 }; 629 }; 630 631 i2c0 { 632 i2c0_xfer: i2c0-xfer { 633 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 634 <0 RK_PA1 1 &pcfg_pull_none>; 635 }; 636 }; 637 638 i2c1 { 639 i2c1_xfer: i2c1-xfer { 640 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 641 <0 RK_PA3 1 &pcfg_pull_none>; 642 }; 643 }; 644 645 i2c2 { 646 i2c2_xfer: i2c2-xfer { 647 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 648 <2 RK_PC5 3 &pcfg_pull_none>; 649 }; 650 }; 651 652 i2c3 { 653 i2c3_xfer: i2c3-xfer { 654 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 655 <0 RK_PA7 1 &pcfg_pull_none>; 656 }; 657 }; 658 659 i2s { 660 i2s_bus: i2s-bus { 661 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 662 <0 RK_PB1 1 &pcfg_pull_none>, 663 <0 RK_PB3 1 &pcfg_pull_none>, 664 <0 RK_PB4 1 &pcfg_pull_none>, 665 <0 RK_PB5 1 &pcfg_pull_none>, 666 <0 RK_PB6 1 &pcfg_pull_none>; 667 }; 668 669 i2s1_bus: i2s1-bus { 670 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 671 <1 RK_PA1 1 &pcfg_pull_none>, 672 <1 RK_PA2 1 &pcfg_pull_none>, 673 <1 RK_PA3 1 &pcfg_pull_none>, 674 <1 RK_PA4 1 &pcfg_pull_none>, 675 <1 RK_PA5 1 &pcfg_pull_none>; 676 }; 677 }; 678 679 lcdc { 680 lcdc_dclk: lcdc-dclk { 681 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 682 }; 683 684 lcdc_den: lcdc-den { 685 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 686 }; 687 688 lcdc_hsync: lcdc-hsync { 689 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 690 }; 691 692 lcdc_vsync: lcdc-vsync { 693 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 694 }; 695 696 lcdc_rgb24: lcdc-rgb24 { 697 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 698 <2 RK_PB5 1 &pcfg_pull_none>, 699 <2 RK_PB6 1 &pcfg_pull_none>, 700 <2 RK_PB7 1 &pcfg_pull_none>, 701 <2 RK_PC0 1 &pcfg_pull_none>, 702 <2 RK_PC1 1 &pcfg_pull_none>, 703 <2 RK_PC2 1 &pcfg_pull_none>, 704 <2 RK_PC3 1 &pcfg_pull_none>, 705 <2 RK_PC4 1 &pcfg_pull_none>, 706 <2 RK_PC5 1 &pcfg_pull_none>, 707 <2 RK_PC6 1 &pcfg_pull_none>, 708 <2 RK_PC7 1 &pcfg_pull_none>, 709 <2 RK_PD0 1 &pcfg_pull_none>, 710 <2 RK_PD1 1 &pcfg_pull_none>; 711 }; 712 }; 713 714 nfc { 715 flash_ale: flash-ale { 716 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 717 }; 718 719 flash_cle: flash-cle { 720 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 721 }; 722 723 flash_wrn: flash-wrn { 724 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 725 }; 726 727 flash_rdn: flash-rdn { 728 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 729 }; 730 731 flash_rdy: flash-rdy { 732 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 733 }; 734 735 flash_cs0: flash-cs0 { 736 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 737 }; 738 739 flash_dqs: flash-dqs { 740 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 741 }; 742 743 flash_bus8: flash-bus8 { 744 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 745 <1 RK_PD1 1 &pcfg_pull_none>, 746 <1 RK_PD2 1 &pcfg_pull_none>, 747 <1 RK_PD3 1 &pcfg_pull_none>, 748 <1 RK_PD4 1 &pcfg_pull_none>, 749 <1 RK_PD5 1 &pcfg_pull_none>, 750 <1 RK_PD6 1 &pcfg_pull_none>, 751 <1 RK_PD7 1 &pcfg_pull_none>; 752 }; 753 }; 754 755 pwm0 { 756 pwm0_pin: pwm0-pin { 757 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 758 }; 759 }; 760 761 pwm1 { 762 pwm1_pin: pwm1-pin { 763 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 764 }; 765 }; 766 767 pwm2 { 768 pwm2_pin: pwm2-pin { 769 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 770 }; 771 }; 772 773 pwm3 { 774 pwm3_pin: pwm3-pin { 775 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 776 }; 777 }; 778 779 sdio { 780 sdio_clk: sdio-clk { 781 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 782 }; 783 784 sdio_cmd: sdio-cmd { 785 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 786 }; 787 788 sdio_pwren: sdio-pwren { 789 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 790 }; 791 792 sdio_bus4: sdio-bus4 { 793 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 794 <1 RK_PA2 2 &pcfg_pull_default>, 795 <1 RK_PA4 2 &pcfg_pull_default>, 796 <1 RK_PA5 2 &pcfg_pull_default>; 797 }; 798 }; 799 800 sdmmc { 801 sdmmc_clk: sdmmc-clk { 802 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 803 }; 804 805 sdmmc_cmd: sdmmc-cmd { 806 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 807 }; 808 809 sdmmc_wp: sdmmc-wp { 810 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 811 }; 812 813 sdmmc_pwren: sdmmc-pwren { 814 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 815 }; 816 817 sdmmc_bus4: sdmmc-bus4 { 818 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 819 <1 RK_PC3 1 &pcfg_pull_default>, 820 <1 RK_PC4 1 &pcfg_pull_default>, 821 <1 RK_PC5 1 &pcfg_pull_default>; 822 }; 823 }; 824 825 spdif { 826 spdif_tx: spdif-tx { 827 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 828 }; 829 }; 830 831 spi0 { 832 spi0_clk: spi0-clk { 833 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 834 }; 835 836 spi0_cs0: spi0-cs0 { 837 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 838 }; 839 840 spi0_tx: spi0-tx { 841 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 842 }; 843 844 spi0_rx: spi0-rx { 845 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 846 }; 847 848 spi0_cs1: spi0-cs1 { 849 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 850 }; 851 852 spi1_clk: spi1-clk { 853 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 854 }; 855 856 spi1_cs0: spi1-cs0 { 857 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 858 }; 859 860 spi1_tx: spi1-tx { 861 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 862 }; 863 864 spi1_rx: spi1-rx { 865 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 866 }; 867 868 spi1_cs1: spi1-cs1 { 869 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 870 }; 871 872 spi2_clk: spi2-clk { 873 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 874 }; 875 876 spi2_cs0: spi2-cs0 { 877 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 878 }; 879 880 spi2_tx: spi2-tx { 881 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 882 }; 883 884 spi2_rx: spi2-rx { 885 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 886 }; 887 }; 888 889 uart0 { 890 uart0_xfer: uart0-xfer { 891 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 892 <2 RK_PD3 2 &pcfg_pull_none>; 893 }; 894 895 uart0_cts: uart0-cts { 896 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 897 }; 898 899 uart0_rts: uart0-rts { 900 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 901 }; 902 }; 903 904 uart1 { 905 uart1_xfer: uart1-xfer { 906 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 907 <1 RK_PB2 2 &pcfg_pull_default>; 908 }; 909 910 uart1_cts: uart1-cts { 911 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 912 }; 913 914 uart1_rts: uart1-rts { 915 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 916 }; 917 }; 918 919 uart2 { 920 uart2_xfer: uart2-xfer { 921 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 922 <1 RK_PC3 2 &pcfg_pull_none>; 923 }; 924 925 uart2_cts: uart2-cts { 926 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 927 }; 928 929 uart2_rts: uart2-rts { 930 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 931 }; 932 }; 933 }; 934}; 935