1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 }; 32 33 arm-pmu { 34 compatible = "arm,cortex-a7-pmu"; 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "rockchip,rk3036-smp"; 46 47 cpu0: cpu@f00 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a7"; 50 reg = <0xf00>; 51 clock-latency = <40000>; 52 clocks = <&cru ARMCLK>; 53 resets = <&cru SRST_CORE0>; 54 operating-points-v2 = <&cpu_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu1: cpu@f01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf01>; 62 resets = <&cru SRST_CORE1>; 63 operating-points-v2 = <&cpu_opp_table>; 64 }; 65 66 cpu2: cpu@f02 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a7"; 69 reg = <0xf02>; 70 resets = <&cru SRST_CORE2>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 cpu3: cpu@f03 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 reg = <0xf03>; 78 resets = <&cru SRST_CORE3>; 79 operating-points-v2 = <&cpu_opp_table>; 80 }; 81 }; 82 83 cpu_opp_table: opp-table-0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-216000000 { 88 opp-hz = /bits/ 64 <216000000>; 89 opp-microvolt = <950000 950000 1325000>; 90 }; 91 opp-408000000 { 92 opp-hz = /bits/ 64 <408000000>; 93 opp-microvolt = <950000 950000 1325000>; 94 }; 95 opp-600000000 { 96 opp-hz = /bits/ 64 <600000000>; 97 opp-microvolt = <950000 950000 1325000>; 98 }; 99 opp-696000000 { 100 opp-hz = /bits/ 64 <696000000>; 101 opp-microvolt = <975000 975000 1325000>; 102 }; 103 opp-816000000 { 104 opp-hz = /bits/ 64 <816000000>; 105 opp-microvolt = <1075000 1075000 1325000>; 106 opp-suspend; 107 }; 108 opp-1008000000 { 109 opp-hz = /bits/ 64 <1008000000>; 110 opp-microvolt = <1200000 1200000 1325000>; 111 }; 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <1325000 1325000 1325000>; 115 }; 116 }; 117 118 display_subsystem: display-subsystem { 119 compatible = "rockchip,display-subsystem"; 120 ports = <&vop_out>; 121 status = "disabled"; 122 }; 123 124 gpu_opp_table: opp-table-1 { 125 compatible = "operating-points-v2"; 126 127 opp-200000000 { 128 opp-hz = /bits/ 64 <200000000>; 129 opp-microvolt = <975000 975000 1250000>; 130 }; 131 opp-300000000 { 132 opp-hz = /bits/ 64 <300000000>; 133 opp-microvolt = <1050000 1050000 1250000>; 134 }; 135 opp-400000000 { 136 opp-hz = /bits/ 64 <400000000>; 137 opp-microvolt = <1150000 1150000 1250000>; 138 }; 139 opp-480000000 { 140 opp-hz = /bits/ 64 <480000000>; 141 opp-microvolt = <1250000 1250000 1250000>; 142 }; 143 }; 144 145 timer { 146 compatible = "arm,armv7-timer"; 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151 arm,cpu-registers-not-fw-configured; 152 clock-frequency = <24000000>; 153 }; 154 155 xin24m: oscillator { 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-output-names = "xin24m"; 159 #clock-cells = <0>; 160 }; 161 162 imem: sram@10080000 { 163 compatible = "mmio-sram"; 164 reg = <0x10080000 0x2000>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0 0x10080000 0x2000>; 168 169 smp-sram@0 { 170 compatible = "rockchip,rk3066-smp-sram"; 171 reg = <0x00 0x10>; 172 }; 173 }; 174 175 gpu: gpu@10090000 { 176 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 177 reg = <0x10090000 0x10000>; 178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "gp", 185 "gpmmu", 186 "pp0", 187 "ppmmu0", 188 "pp1", 189 "ppmmu1"; 190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 191 clock-names = "bus", "core"; 192 operating-points-v2 = <&gpu_opp_table>; 193 resets = <&cru SRST_GPU>; 194 power-domains = <&power RK3128_PD_GPU>; 195 status = "disabled"; 196 }; 197 198 pmu: syscon@100a0000 { 199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 200 reg = <0x100a0000 0x1000>; 201 202 power: power-controller { 203 compatible = "rockchip,rk3128-power-controller"; 204 #power-domain-cells = <1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 power-domain@RK3128_PD_VIO { 209 reg = <RK3128_PD_VIO>; 210 clocks = <&cru ACLK_CIF>, 211 <&cru HCLK_CIF>, 212 <&cru DCLK_EBC>, 213 <&cru HCLK_EBC>, 214 <&cru ACLK_IEP>, 215 <&cru HCLK_IEP>, 216 <&cru ACLK_LCDC0>, 217 <&cru HCLK_LCDC0>, 218 <&cru PCLK_MIPI>, 219 <&cru PCLK_MIPIPHY>, 220 <&cru SCLK_MIPI_24M>, 221 <&cru ACLK_RGA>, 222 <&cru HCLK_RGA>, 223 <&cru ACLK_VIO0>, 224 <&cru ACLK_VIO1>, 225 <&cru HCLK_VIO>, 226 <&cru HCLK_VIO_H2P>, 227 <&cru DCLK_VOP>, 228 <&cru SCLK_VOP>; 229 pm_qos = <&qos_ebc>, 230 <&qos_iep>, 231 <&qos_lcdc>, 232 <&qos_rga>, 233 <&qos_vip>; 234 #power-domain-cells = <0>; 235 }; 236 237 power-domain@RK3128_PD_VIDEO { 238 reg = <RK3128_PD_VIDEO>; 239 clocks = <&cru ACLK_VDPU>, 240 <&cru HCLK_VDPU>, 241 <&cru ACLK_VEPU>, 242 <&cru HCLK_VEPU>, 243 <&cru SCLK_HEVC_CORE>; 244 pm_qos = <&qos_vpu>; 245 #power-domain-cells = <0>; 246 }; 247 248 power-domain@RK3128_PD_GPU { 249 reg = <RK3128_PD_GPU>; 250 clocks = <&cru ACLK_GPU>; 251 pm_qos = <&qos_gpu>; 252 #power-domain-cells = <0>; 253 }; 254 }; 255 }; 256 257 vop: vop@1010e000 { 258 compatible = "rockchip,rk3126-vop"; 259 reg = <0x1010e000 0x300>; 260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, 262 <&cru HCLK_LCDC0>; 263 clock-names = "aclk_vop", "dclk_vop", 264 "hclk_vop"; 265 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, 266 <&cru SRST_VOP_D>; 267 reset-names = "axi", "ahb", 268 "dclk"; 269 power-domains = <&power RK3128_PD_VIO>; 270 status = "disabled"; 271 272 vop_out: port { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 vop_out_hdmi: endpoint@0 { 277 reg = <0>; 278 remote-endpoint = <&hdmi_in_vop>; 279 }; 280 281 vop_out_dsi: endpoint@1 { 282 reg = <1>; 283 remote-endpoint = <&dsi_in_vop>; 284 }; 285 }; 286 }; 287 288 dsi: dsi@10110000 { 289 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; 290 reg = <0x10110000 0x4000>; 291 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru PCLK_MIPI>; 293 clock-names = "pclk"; 294 phys = <&dphy>; 295 phy-names = "dphy"; 296 power-domains = <&power RK3128_PD_VIO>; 297 resets = <&cru SRST_VIO_MIPI_DSI>; 298 reset-names = "apb"; 299 rockchip,grf = <&grf>; 300 status = "disabled"; 301 302 ports { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 306 dsi_in: port@0 { 307 reg = <0>; 308 309 dsi_in_vop: endpoint { 310 remote-endpoint = <&vop_out_dsi>; 311 }; 312 }; 313 314 dsi_out: port@1 { 315 reg = <1>; 316 }; 317 }; 318 }; 319 320 qos_gpu: qos@1012d000 { 321 compatible = "rockchip,rk3128-qos", "syscon"; 322 reg = <0x1012d000 0x20>; 323 }; 324 325 qos_vpu: qos@1012e000 { 326 compatible = "rockchip,rk3128-qos", "syscon"; 327 reg = <0x1012e000 0x20>; 328 }; 329 330 qos_rga: qos@1012f000 { 331 compatible = "rockchip,rk3128-qos", "syscon"; 332 reg = <0x1012f000 0x20>; 333 }; 334 335 qos_ebc: qos@1012f080 { 336 compatible = "rockchip,rk3128-qos", "syscon"; 337 reg = <0x1012f080 0x20>; 338 }; 339 340 qos_iep: qos@1012f100 { 341 compatible = "rockchip,rk3128-qos", "syscon"; 342 reg = <0x1012f100 0x20>; 343 }; 344 345 qos_lcdc: qos@1012f180 { 346 compatible = "rockchip,rk3128-qos", "syscon"; 347 reg = <0x1012f180 0x20>; 348 }; 349 350 qos_vip: qos@1012f200 { 351 compatible = "rockchip,rk3128-qos", "syscon"; 352 reg = <0x1012f200 0x20>; 353 }; 354 355 gic: interrupt-controller@10139000 { 356 compatible = "arm,cortex-a7-gic"; 357 reg = <0x10139000 0x1000>, 358 <0x1013a000 0x1000>, 359 <0x1013c000 0x2000>, 360 <0x1013e000 0x2000>; 361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 362 interrupt-controller; 363 #interrupt-cells = <3>; 364 #address-cells = <0>; 365 }; 366 367 usb_otg: usb@10180000 { 368 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 369 reg = <0x10180000 0x40000>; 370 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&cru HCLK_OTG>; 372 clock-names = "otg"; 373 dr_mode = "otg"; 374 g-np-tx-fifo-size = <16>; 375 g-rx-fifo-size = <280>; 376 g-tx-fifo-size = <256 128 128 64 32 16>; 377 phys = <&usb2phy_otg>; 378 phy-names = "usb2-phy"; 379 status = "disabled"; 380 }; 381 382 usb_host_ehci: usb@101c0000 { 383 compatible = "generic-ehci"; 384 reg = <0x101c0000 0x20000>; 385 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cru HCLK_HOST2>; 387 phys = <&usb2phy_host>; 388 phy-names = "usb"; 389 status = "disabled"; 390 }; 391 392 usb_host_ohci: usb@101e0000 { 393 compatible = "generic-ohci"; 394 reg = <0x101e0000 0x20000>; 395 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&cru HCLK_HOST2>; 397 phys = <&usb2phy_host>; 398 phy-names = "usb"; 399 status = "disabled"; 400 }; 401 402 i2s_8ch: i2s@10200000 { 403 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 404 reg = <0x10200000 0x1000>; 405 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>; 407 clock-names = "i2s_clk", "i2s_hclk"; 408 dmas = <&pdma 14>, <&pdma 15>; 409 dma-names = "tx", "rx"; 410 #sound-dai-cells = <0>; 411 status = "disabled"; 412 }; 413 414 spdif: spdif@10204000 { 415 compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif"; 416 reg = <0x10204000 0x1000>; 417 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 419 clock-names = "mclk", "hclk"; 420 dmas = <&pdma 13>; 421 dma-names = "tx"; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&spdif_tx>; 424 #sound-dai-cells = <0>; 425 status = "disabled"; 426 }; 427 428 sdmmc: mmc@10214000 { 429 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 430 reg = <0x10214000 0x4000>; 431 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 433 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 434 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 435 dmas = <&pdma 10>; 436 dma-names = "rx-tx"; 437 fifo-depth = <256>; 438 max-frequency = <150000000>; 439 resets = <&cru SRST_SDMMC>; 440 reset-names = "reset"; 441 status = "disabled"; 442 }; 443 444 sdio: mmc@10218000 { 445 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 446 reg = <0x10218000 0x4000>; 447 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 449 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 450 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 451 dmas = <&pdma 11>; 452 dma-names = "rx-tx"; 453 fifo-depth = <256>; 454 max-frequency = <150000000>; 455 resets = <&cru SRST_SDIO>; 456 reset-names = "reset"; 457 status = "disabled"; 458 }; 459 460 emmc: mmc@1021c000 { 461 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 462 reg = <0x1021c000 0x4000>; 463 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 465 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 466 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 467 dmas = <&pdma 12>; 468 dma-names = "rx-tx"; 469 fifo-depth = <256>; 470 max-frequency = <150000000>; 471 resets = <&cru SRST_EMMC>; 472 reset-names = "reset"; 473 status = "disabled"; 474 }; 475 476 i2s_2ch: i2s@10220000 { 477 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 478 reg = <0x10220000 0x1000>; 479 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>; 481 clock-names = "i2s_clk", "i2s_hclk"; 482 dmas = <&pdma 0>, <&pdma 1>; 483 dma-names = "tx", "rx"; 484 rockchip,playback-channels = <2>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&i2s_bus>; 487 #sound-dai-cells = <0>; 488 status = "disabled"; 489 }; 490 491 nfc: nand-controller@10500000 { 492 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 493 reg = <0x10500000 0x4000>; 494 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 496 clock-names = "ahb", "nfc"; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 499 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 500 status = "disabled"; 501 }; 502 503 cru: clock-controller@20000000 { 504 compatible = "rockchip,rk3128-cru"; 505 reg = <0x20000000 0x1000>; 506 clocks = <&xin24m>; 507 clock-names = "xin24m"; 508 rockchip,grf = <&grf>; 509 #clock-cells = <1>; 510 #reset-cells = <1>; 511 assigned-clocks = <&cru PLL_GPLL>; 512 assigned-clock-rates = <594000000>; 513 }; 514 515 grf: syscon@20008000 { 516 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 517 reg = <0x20008000 0x1000>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 521 usb2phy: usb2phy@17c { 522 compatible = "rockchip,rk3128-usb2phy"; 523 reg = <0x017c 0x0c>; 524 clocks = <&cru SCLK_OTGPHY0>; 525 clock-names = "phyclk"; 526 clock-output-names = "usb480m_phy"; 527 assigned-clocks = <&cru SCLK_USB480M>; 528 assigned-clock-parents = <&usb2phy>; 529 #clock-cells = <0>; 530 status = "disabled"; 531 532 usb2phy_host: host-port { 533 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 534 interrupt-names = "linestate"; 535 #phy-cells = <0>; 536 status = "disabled"; 537 }; 538 539 usb2phy_otg: otg-port { 540 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 543 interrupt-names = "otg-bvalid", "otg-id", 544 "linestate"; 545 #phy-cells = <0>; 546 status = "disabled"; 547 }; 548 }; 549 }; 550 551 hdmi: hdmi@20034000 { 552 compatible = "rockchip,rk3128-inno-hdmi"; 553 reg = <0x20034000 0x4000>; 554 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; 556 clock-names = "pclk", "ref"; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 559 power-domains = <&power RK3128_PD_VIO>; 560 status = "disabled"; 561 562 ports { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 hdmi_in: port@0 { 567 reg = <0>; 568 hdmi_in_vop: endpoint { 569 remote-endpoint = <&vop_out_hdmi>; 570 }; 571 }; 572 573 hdmi_out: port@1 { 574 reg = <1>; 575 }; 576 }; 577 }; 578 579 dphy: phy@20038000 { 580 compatible = "rockchip,rk3128-dsi-dphy"; 581 reg = <0x20038000 0x4000>; 582 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; 583 clock-names = "ref", "pclk"; 584 #phy-cells = <0>; 585 power-domains = <&power RK3128_PD_VIO>; 586 resets = <&cru SRST_MIPIPHY_P>; 587 reset-names = "apb"; 588 status = "disabled"; 589 }; 590 591 timer0: timer@20044000 { 592 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 593 reg = <0x20044000 0x20>; 594 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 596 clock-names = "pclk", "timer"; 597 }; 598 599 timer1: timer@20044020 { 600 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 601 reg = <0x20044020 0x20>; 602 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 604 clock-names = "pclk", "timer"; 605 }; 606 607 timer2: timer@20044040 { 608 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 609 reg = <0x20044040 0x20>; 610 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 612 clock-names = "pclk", "timer"; 613 }; 614 615 timer3: timer@20044060 { 616 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 617 reg = <0x20044060 0x20>; 618 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 620 clock-names = "pclk", "timer"; 621 }; 622 623 timer4: timer@20044080 { 624 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 625 reg = <0x20044080 0x20>; 626 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 628 clock-names = "pclk", "timer"; 629 }; 630 631 timer5: timer@200440a0 { 632 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 633 reg = <0x200440a0 0x20>; 634 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 636 clock-names = "pclk", "timer"; 637 }; 638 639 watchdog: watchdog@2004c000 { 640 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 641 reg = <0x2004c000 0x100>; 642 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru PCLK_WDT>; 644 status = "disabled"; 645 }; 646 647 pwm0: pwm@20050000 { 648 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 649 reg = <0x20050000 0x10>; 650 clocks = <&cru PCLK_PWM>; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pwm0_pin>; 653 #pwm-cells = <3>; 654 status = "disabled"; 655 }; 656 657 pwm1: pwm@20050010 { 658 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 659 reg = <0x20050010 0x10>; 660 clocks = <&cru PCLK_PWM>; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pwm1_pin>; 663 #pwm-cells = <3>; 664 status = "disabled"; 665 }; 666 667 pwm2: pwm@20050020 { 668 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 669 reg = <0x20050020 0x10>; 670 clocks = <&cru PCLK_PWM>; 671 pinctrl-names = "default"; 672 pinctrl-0 = <&pwm2_pin>; 673 #pwm-cells = <3>; 674 status = "disabled"; 675 }; 676 677 pwm3: pwm@20050030 { 678 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 679 reg = <0x20050030 0x10>; 680 clocks = <&cru PCLK_PWM>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pwm3_pin>; 683 #pwm-cells = <3>; 684 status = "disabled"; 685 }; 686 687 i2c1: i2c@20056000 { 688 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 689 reg = <0x20056000 0x1000>; 690 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 691 clock-names = "i2c"; 692 clocks = <&cru PCLK_I2C1>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&i2c1_xfer>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 i2c2: i2c@2005a000 { 701 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 702 reg = <0x2005a000 0x1000>; 703 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 704 clock-names = "i2c"; 705 clocks = <&cru PCLK_I2C2>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&i2c2_xfer>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 status = "disabled"; 711 }; 712 713 i2c3: i2c@2005e000 { 714 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 715 reg = <0x2005e000 0x1000>; 716 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 717 clock-names = "i2c"; 718 clocks = <&cru PCLK_I2C3>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&i2c3_xfer>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 uart0: serial@20060000 { 727 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 728 reg = <0x20060000 0x100>; 729 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 730 clock-frequency = <24000000>; 731 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 732 clock-names = "baudclk", "apb_pclk"; 733 dmas = <&pdma 2>, <&pdma 3>; 734 dma-names = "tx", "rx"; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 737 reg-io-width = <4>; 738 reg-shift = <2>; 739 status = "disabled"; 740 }; 741 742 uart1: serial@20064000 { 743 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 744 reg = <0x20064000 0x100>; 745 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 746 clock-frequency = <24000000>; 747 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 748 clock-names = "baudclk", "apb_pclk"; 749 dmas = <&pdma 4>, <&pdma 5>; 750 dma-names = "tx", "rx"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&uart1_xfer>; 753 reg-io-width = <4>; 754 reg-shift = <2>; 755 status = "disabled"; 756 }; 757 758 uart2: serial@20068000 { 759 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 760 reg = <0x20068000 0x100>; 761 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 762 clock-frequency = <24000000>; 763 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 764 clock-names = "baudclk", "apb_pclk"; 765 dmas = <&pdma 6>, <&pdma 7>; 766 dma-names = "tx", "rx"; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&uart2_xfer>; 769 reg-io-width = <4>; 770 reg-shift = <2>; 771 status = "disabled"; 772 }; 773 774 saradc: saradc@2006c000 { 775 compatible = "rockchip,saradc"; 776 reg = <0x2006c000 0x100>; 777 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 779 clock-names = "saradc", "apb_pclk"; 780 resets = <&cru SRST_SARADC>; 781 reset-names = "saradc-apb"; 782 #io-channel-cells = <1>; 783 status = "disabled"; 784 }; 785 786 i2c0: i2c@20072000 { 787 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 788 reg = <0x20072000 0x1000>; 789 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 790 clock-names = "i2c"; 791 clocks = <&cru PCLK_I2C0>; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&i2c0_xfer>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 status = "disabled"; 797 }; 798 799 spi0: spi@20074000 { 800 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 801 reg = <0x20074000 0x1000>; 802 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 804 clock-names = "spiclk", "apb_pclk"; 805 dmas = <&pdma 8>, <&pdma 9>; 806 dma-names = "tx", "rx"; 807 pinctrl-names = "default"; 808 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 status = "disabled"; 812 }; 813 814 pdma: dma-controller@20078000 { 815 compatible = "arm,pl330", "arm,primecell"; 816 reg = <0x20078000 0x4000>; 817 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 819 arm,pl330-broken-no-flushp; 820 arm,pl330-periph-burst; 821 clocks = <&cru ACLK_DMAC>; 822 clock-names = "apb_pclk"; 823 #dma-cells = <1>; 824 }; 825 826 gmac: ethernet@2008c000 { 827 compatible = "rockchip,rk3128-gmac"; 828 reg = <0x2008c000 0x4000>; 829 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "macirq", "eth_wake_irq"; 832 clocks = <&cru SCLK_MAC>, 833 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 834 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 835 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 836 clock-names = "stmmaceth", 837 "mac_clk_rx", "mac_clk_tx", 838 "clk_mac_ref", "clk_mac_refout", 839 "aclk_mac", "pclk_mac"; 840 resets = <&cru SRST_GMAC>; 841 reset-names = "stmmaceth"; 842 rockchip,grf = <&grf>; 843 rx-fifo-depth = <4096>; 844 tx-fifo-depth = <2048>; 845 status = "disabled"; 846 847 mdio: mdio { 848 compatible = "snps,dwmac-mdio"; 849 #address-cells = <0x1>; 850 #size-cells = <0x0>; 851 }; 852 }; 853 854 pinctrl: pinctrl { 855 compatible = "rockchip,rk3128-pinctrl"; 856 rockchip,grf = <&grf>; 857 #address-cells = <1>; 858 #size-cells = <1>; 859 ranges; 860 861 gpio0: gpio@2007c000 { 862 compatible = "rockchip,gpio-bank"; 863 reg = <0x2007c000 0x100>; 864 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&cru PCLK_GPIO0>; 866 gpio-controller; 867 #gpio-cells = <2>; 868 interrupt-controller; 869 #interrupt-cells = <2>; 870 }; 871 872 gpio1: gpio@20080000 { 873 compatible = "rockchip,gpio-bank"; 874 reg = <0x20080000 0x100>; 875 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&cru PCLK_GPIO1>; 877 gpio-controller; 878 #gpio-cells = <2>; 879 interrupt-controller; 880 #interrupt-cells = <2>; 881 }; 882 883 gpio2: gpio@20084000 { 884 compatible = "rockchip,gpio-bank"; 885 reg = <0x20084000 0x100>; 886 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cru PCLK_GPIO2>; 888 gpio-controller; 889 #gpio-cells = <2>; 890 interrupt-controller; 891 #interrupt-cells = <2>; 892 }; 893 894 gpio3: gpio@20088000 { 895 compatible = "rockchip,gpio-bank"; 896 reg = <0x20088000 0x100>; 897 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&cru PCLK_GPIO3>; 899 gpio-controller; 900 #gpio-cells = <2>; 901 interrupt-controller; 902 #interrupt-cells = <2>; 903 }; 904 905 pcfg_pull_default: pcfg-pull-default { 906 bias-pull-pin-default; 907 }; 908 909 pcfg_pull_none: pcfg-pull-none { 910 bias-disable; 911 }; 912 913 emmc { 914 emmc_clk: emmc-clk { 915 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 916 }; 917 918 emmc_cmd: emmc-cmd { 919 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 920 }; 921 922 emmc_cmd1: emmc-cmd1 { 923 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 924 }; 925 926 emmc_pwr: emmc-pwr { 927 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 928 }; 929 930 emmc_bus1: emmc-bus1 { 931 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 932 }; 933 934 emmc_bus4: emmc-bus4 { 935 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 936 <1 RK_PD1 2 &pcfg_pull_default>, 937 <1 RK_PD2 2 &pcfg_pull_default>, 938 <1 RK_PD3 2 &pcfg_pull_default>; 939 }; 940 941 emmc_bus8: emmc-bus8 { 942 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 943 <1 RK_PD1 2 &pcfg_pull_default>, 944 <1 RK_PD2 2 &pcfg_pull_default>, 945 <1 RK_PD3 2 &pcfg_pull_default>, 946 <1 RK_PD4 2 &pcfg_pull_default>, 947 <1 RK_PD5 2 &pcfg_pull_default>, 948 <1 RK_PD6 2 &pcfg_pull_default>, 949 <1 RK_PD7 2 &pcfg_pull_default>; 950 }; 951 }; 952 953 gmac { 954 rgmii_pins: rgmii-pins { 955 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 956 <2 RK_PB1 3 &pcfg_pull_default>, 957 <2 RK_PB3 3 &pcfg_pull_default>, 958 <2 RK_PB4 3 &pcfg_pull_default>, 959 <2 RK_PB5 3 &pcfg_pull_default>, 960 <2 RK_PB6 3 &pcfg_pull_default>, 961 <2 RK_PC0 3 &pcfg_pull_default>, 962 <2 RK_PC1 3 &pcfg_pull_default>, 963 <2 RK_PC2 3 &pcfg_pull_default>, 964 <2 RK_PC3 3 &pcfg_pull_default>, 965 <2 RK_PD1 3 &pcfg_pull_default>, 966 <2 RK_PC4 4 &pcfg_pull_default>, 967 <2 RK_PC5 4 &pcfg_pull_default>, 968 <2 RK_PC6 4 &pcfg_pull_default>, 969 <2 RK_PC7 4 &pcfg_pull_default>; 970 }; 971 972 rmii_pins: rmii-pins { 973 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 974 <2 RK_PB4 3 &pcfg_pull_default>, 975 <2 RK_PB5 3 &pcfg_pull_default>, 976 <2 RK_PB6 3 &pcfg_pull_default>, 977 <2 RK_PB7 3 &pcfg_pull_default>, 978 <2 RK_PC0 3 &pcfg_pull_default>, 979 <2 RK_PC1 3 &pcfg_pull_default>, 980 <2 RK_PC2 3 &pcfg_pull_default>, 981 <2 RK_PC3 3 &pcfg_pull_default>, 982 <2 RK_PD1 3 &pcfg_pull_default>; 983 }; 984 }; 985 986 hdmi { 987 hdmii2c_xfer: hdmii2c-xfer { 988 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 989 <0 RK_PA7 2 &pcfg_pull_none>; 990 }; 991 992 hdmi_hpd: hdmi-hpd { 993 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 994 }; 995 996 hdmi_cec: hdmi-cec { 997 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 998 }; 999 }; 1000 1001 i2c0 { 1002 i2c0_xfer: i2c0-xfer { 1003 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1004 <0 RK_PA1 1 &pcfg_pull_none>; 1005 }; 1006 }; 1007 1008 i2c1 { 1009 i2c1_xfer: i2c1-xfer { 1010 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1011 <0 RK_PA3 1 &pcfg_pull_none>; 1012 }; 1013 }; 1014 1015 i2c2 { 1016 i2c2_xfer: i2c2-xfer { 1017 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 1018 <2 RK_PC5 3 &pcfg_pull_none>; 1019 }; 1020 }; 1021 1022 i2c3 { 1023 i2c3_xfer: i2c3-xfer { 1024 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1025 <0 RK_PA7 1 &pcfg_pull_none>; 1026 }; 1027 }; 1028 1029 i2s { 1030 i2s_bus: i2s-bus { 1031 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1032 <0 RK_PB1 1 &pcfg_pull_none>, 1033 <0 RK_PB3 1 &pcfg_pull_none>, 1034 <0 RK_PB4 1 &pcfg_pull_none>, 1035 <0 RK_PB5 1 &pcfg_pull_none>, 1036 <0 RK_PB6 1 &pcfg_pull_none>; 1037 }; 1038 1039 i2s1_bus: i2s1-bus { 1040 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 1041 <1 RK_PA1 1 &pcfg_pull_none>, 1042 <1 RK_PA2 1 &pcfg_pull_none>, 1043 <1 RK_PA3 1 &pcfg_pull_none>, 1044 <1 RK_PA4 1 &pcfg_pull_none>, 1045 <1 RK_PA5 1 &pcfg_pull_none>; 1046 }; 1047 }; 1048 1049 lcdc { 1050 lcdc_dclk: lcdc-dclk { 1051 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 1052 }; 1053 1054 lcdc_den: lcdc-den { 1055 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 1056 }; 1057 1058 lcdc_hsync: lcdc-hsync { 1059 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1060 }; 1061 1062 lcdc_vsync: lcdc-vsync { 1063 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 1064 }; 1065 1066 lcdc_rgb24: lcdc-rgb24 { 1067 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 1068 <2 RK_PB5 1 &pcfg_pull_none>, 1069 <2 RK_PB6 1 &pcfg_pull_none>, 1070 <2 RK_PB7 1 &pcfg_pull_none>, 1071 <2 RK_PC0 1 &pcfg_pull_none>, 1072 <2 RK_PC1 1 &pcfg_pull_none>, 1073 <2 RK_PC2 1 &pcfg_pull_none>, 1074 <2 RK_PC3 1 &pcfg_pull_none>, 1075 <2 RK_PC4 1 &pcfg_pull_none>, 1076 <2 RK_PC5 1 &pcfg_pull_none>, 1077 <2 RK_PC6 1 &pcfg_pull_none>, 1078 <2 RK_PC7 1 &pcfg_pull_none>, 1079 <2 RK_PD0 1 &pcfg_pull_none>, 1080 <2 RK_PD1 1 &pcfg_pull_none>; 1081 }; 1082 }; 1083 1084 nfc { 1085 flash_ale: flash-ale { 1086 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 1087 }; 1088 1089 flash_cle: flash-cle { 1090 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 1091 }; 1092 1093 flash_wrn: flash-wrn { 1094 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1095 }; 1096 1097 flash_rdn: flash-rdn { 1098 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 1099 }; 1100 1101 flash_rdy: flash-rdy { 1102 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1103 }; 1104 1105 flash_cs0: flash-cs0 { 1106 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1107 }; 1108 1109 flash_dqs: flash-dqs { 1110 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 1111 }; 1112 1113 flash_bus8: flash-bus8 { 1114 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1115 <1 RK_PD1 1 &pcfg_pull_none>, 1116 <1 RK_PD2 1 &pcfg_pull_none>, 1117 <1 RK_PD3 1 &pcfg_pull_none>, 1118 <1 RK_PD4 1 &pcfg_pull_none>, 1119 <1 RK_PD5 1 &pcfg_pull_none>, 1120 <1 RK_PD6 1 &pcfg_pull_none>, 1121 <1 RK_PD7 1 &pcfg_pull_none>; 1122 }; 1123 }; 1124 1125 pwm0 { 1126 pwm0_pin: pwm0-pin { 1127 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 1128 }; 1129 }; 1130 1131 pwm1 { 1132 pwm1_pin: pwm1-pin { 1133 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1134 }; 1135 }; 1136 1137 pwm2 { 1138 pwm2_pin: pwm2-pin { 1139 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1140 }; 1141 }; 1142 1143 pwm3 { 1144 pwm3_pin: pwm3-pin { 1145 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 1146 }; 1147 }; 1148 1149 sdio { 1150 sdio_clk: sdio-clk { 1151 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1152 }; 1153 1154 sdio_cmd: sdio-cmd { 1155 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1156 }; 1157 1158 sdio_pwren: sdio-pwren { 1159 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1160 }; 1161 1162 sdio_bus4: sdio-bus4 { 1163 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1164 <1 RK_PA2 2 &pcfg_pull_default>, 1165 <1 RK_PA4 2 &pcfg_pull_default>, 1166 <1 RK_PA5 2 &pcfg_pull_default>; 1167 }; 1168 }; 1169 1170 sdmmc { 1171 sdmmc_clk: sdmmc-clk { 1172 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1173 }; 1174 1175 sdmmc_cmd: sdmmc-cmd { 1176 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1177 }; 1178 1179 sdmmc_det: sdmmc-det { 1180 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1181 }; 1182 1183 sdmmc_wp: sdmmc-wp { 1184 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1185 }; 1186 1187 sdmmc_pwren: sdmmc-pwren { 1188 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 1189 }; 1190 1191 sdmmc_bus4: sdmmc-bus4 { 1192 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1193 <1 RK_PC3 1 &pcfg_pull_default>, 1194 <1 RK_PC4 1 &pcfg_pull_default>, 1195 <1 RK_PC5 1 &pcfg_pull_default>; 1196 }; 1197 }; 1198 1199 spdif { 1200 spdif_tx: spdif-tx { 1201 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1202 }; 1203 }; 1204 1205 spi0 { 1206 spi0_clk: spi0-clk { 1207 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1208 }; 1209 1210 spi0_cs0: spi0-cs0 { 1211 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1212 }; 1213 1214 spi0_tx: spi0-tx { 1215 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1216 }; 1217 1218 spi0_rx: spi0-rx { 1219 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1220 }; 1221 1222 spi0_cs1: spi0-cs1 { 1223 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1224 }; 1225 1226 spi1_clk: spi1-clk { 1227 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1228 }; 1229 1230 spi1_cs0: spi1-cs0 { 1231 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1232 }; 1233 1234 spi1_tx: spi1-tx { 1235 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1236 }; 1237 1238 spi1_rx: spi1-rx { 1239 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1240 }; 1241 1242 spi1_cs1: spi1-cs1 { 1243 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1244 }; 1245 1246 spi2_clk: spi2-clk { 1247 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1248 }; 1249 1250 spi2_cs0: spi2-cs0 { 1251 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1252 }; 1253 1254 spi2_tx: spi2-tx { 1255 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1256 }; 1257 1258 spi2_rx: spi2-rx { 1259 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1260 }; 1261 }; 1262 1263 uart0 { 1264 uart0_xfer: uart0-xfer { 1265 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1266 <2 RK_PD3 2 &pcfg_pull_none>; 1267 }; 1268 1269 uart0_cts: uart0-cts { 1270 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1271 }; 1272 1273 uart0_rts: uart0-rts { 1274 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1275 }; 1276 }; 1277 1278 uart1 { 1279 uart1_xfer: uart1-xfer { 1280 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1281 <1 RK_PB2 2 &pcfg_pull_default>; 1282 }; 1283 1284 uart1_cts: uart1-cts { 1285 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1286 }; 1287 1288 uart1_rts: uart1-rts { 1289 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1290 }; 1291 }; 1292 1293 uart2 { 1294 uart2_xfer: uart2-xfer { 1295 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1296 <1 RK_PC3 2 &pcfg_pull_none>; 1297 }; 1298 1299 uart2_cts: uart2-cts { 1300 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1301 }; 1302 1303 uart2_rts: uart2-rts { 1304 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1305 }; 1306 }; 1307 }; 1308}; 1309