1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 enable-method = "rockchip,rk3036-smp"; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 resets = <&cru SRST_CORE0>; 39 operating-points-v2 = <&cpu_opp_table>; 40 #cooling-cells = <2>; /* min followed by max */ 41 }; 42 43 cpu1: cpu@f01 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0xf01>; 47 resets = <&cru SRST_CORE1>; 48 operating-points-v2 = <&cpu_opp_table>; 49 }; 50 51 cpu2: cpu@f02 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf02>; 55 resets = <&cru SRST_CORE2>; 56 operating-points-v2 = <&cpu_opp_table>; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 operating-points-v2 = <&cpu_opp_table>; 65 }; 66 }; 67 68 cpu_opp_table: opp-table-0 { 69 compatible = "operating-points-v2"; 70 opp-shared; 71 72 opp-216000000 { 73 opp-hz = /bits/ 64 <216000000>; 74 opp-microvolt = <950000 950000 1325000>; 75 }; 76 opp-408000000 { 77 opp-hz = /bits/ 64 <408000000>; 78 opp-microvolt = <950000 950000 1325000>; 79 }; 80 opp-600000000 { 81 opp-hz = /bits/ 64 <600000000>; 82 opp-microvolt = <950000 950000 1325000>; 83 }; 84 opp-696000000 { 85 opp-hz = /bits/ 64 <696000000>; 86 opp-microvolt = <975000 975000 1325000>; 87 }; 88 opp-816000000 { 89 opp-hz = /bits/ 64 <816000000>; 90 opp-microvolt = <1075000 1075000 1325000>; 91 opp-suspend; 92 }; 93 opp-1008000000 { 94 opp-hz = /bits/ 64 <1008000000>; 95 opp-microvolt = <1200000 1200000 1325000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <1325000 1325000 1325000>; 100 }; 101 }; 102 103 timer { 104 compatible = "arm,armv7-timer"; 105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 arm,cpu-registers-not-fw-configured; 109 clock-frequency = <24000000>; 110 }; 111 112 xin24m: oscillator { 113 compatible = "fixed-clock"; 114 clock-frequency = <24000000>; 115 clock-output-names = "xin24m"; 116 #clock-cells = <0>; 117 }; 118 119 imem: sram@10080000 { 120 compatible = "mmio-sram"; 121 reg = <0x10080000 0x2000>; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0 0x10080000 0x2000>; 125 126 smp-sram@0 { 127 compatible = "rockchip,rk3066-smp-sram"; 128 reg = <0x00 0x10>; 129 }; 130 }; 131 132 pmu: syscon@100a0000 { 133 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 134 reg = <0x100a0000 0x1000>; 135 }; 136 137 gic: interrupt-controller@10139000 { 138 compatible = "arm,cortex-a7-gic"; 139 reg = <0x10139000 0x1000>, 140 <0x1013a000 0x1000>, 141 <0x1013c000 0x2000>, 142 <0x1013e000 0x2000>; 143 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 144 interrupt-controller; 145 #interrupt-cells = <3>; 146 #address-cells = <0>; 147 }; 148 149 usb_otg: usb@10180000 { 150 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 151 reg = <0x10180000 0x40000>; 152 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&cru HCLK_OTG>; 154 clock-names = "otg"; 155 dr_mode = "otg"; 156 phys = <&usb2phy_otg>; 157 phy-names = "usb2-phy"; 158 status = "disabled"; 159 }; 160 161 usb_host_ehci: usb@101c0000 { 162 compatible = "generic-ehci"; 163 reg = <0x101c0000 0x20000>; 164 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 165 phys = <&usb2phy_host>; 166 phy-names = "usb"; 167 status = "disabled"; 168 }; 169 170 usb_host_ohci: usb@101e0000 { 171 compatible = "generic-ohci"; 172 reg = <0x101e0000 0x20000>; 173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 174 phys = <&usb2phy_host>; 175 phy-names = "usb"; 176 status = "disabled"; 177 }; 178 179 sdmmc: mmc@10214000 { 180 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 181 reg = <0x10214000 0x4000>; 182 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 185 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 186 dmas = <&pdma 10>; 187 dma-names = "rx-tx"; 188 fifo-depth = <256>; 189 max-frequency = <150000000>; 190 resets = <&cru SRST_SDMMC>; 191 reset-names = "reset"; 192 status = "disabled"; 193 }; 194 195 sdio: mmc@10218000 { 196 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 197 reg = <0x10218000 0x4000>; 198 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 200 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 201 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 202 dmas = <&pdma 11>; 203 dma-names = "rx-tx"; 204 fifo-depth = <256>; 205 max-frequency = <150000000>; 206 resets = <&cru SRST_SDIO>; 207 reset-names = "reset"; 208 status = "disabled"; 209 }; 210 211 emmc: mmc@1021c000 { 212 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 213 reg = <0x1021c000 0x4000>; 214 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 216 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 217 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 218 dmas = <&pdma 12>; 219 dma-names = "rx-tx"; 220 fifo-depth = <256>; 221 max-frequency = <150000000>; 222 resets = <&cru SRST_EMMC>; 223 reset-names = "reset"; 224 status = "disabled"; 225 }; 226 227 nfc: nand-controller@10500000 { 228 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 229 reg = <0x10500000 0x4000>; 230 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 232 clock-names = "ahb", "nfc"; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 235 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 236 status = "disabled"; 237 }; 238 239 cru: clock-controller@20000000 { 240 compatible = "rockchip,rk3128-cru"; 241 reg = <0x20000000 0x1000>; 242 clocks = <&xin24m>; 243 clock-names = "xin24m"; 244 rockchip,grf = <&grf>; 245 #clock-cells = <1>; 246 #reset-cells = <1>; 247 assigned-clocks = <&cru PLL_GPLL>; 248 assigned-clock-rates = <594000000>; 249 }; 250 251 grf: syscon@20008000 { 252 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 253 reg = <0x20008000 0x1000>; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 257 usb2phy: usb2phy@17c { 258 compatible = "rockchip,rk3128-usb2phy"; 259 reg = <0x017c 0x0c>; 260 clocks = <&cru SCLK_OTGPHY0>; 261 clock-names = "phyclk"; 262 clock-output-names = "usb480m_phy"; 263 #clock-cells = <0>; 264 status = "disabled"; 265 266 usb2phy_host: host-port { 267 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-names = "linestate"; 269 #phy-cells = <0>; 270 status = "disabled"; 271 }; 272 273 usb2phy_otg: otg-port { 274 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "otg-bvalid", "otg-id", 278 "linestate"; 279 #phy-cells = <0>; 280 status = "disabled"; 281 }; 282 }; 283 }; 284 285 timer0: timer@20044000 { 286 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 287 reg = <0x20044000 0x20>; 288 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&cru PCLK_TIMER>, <&xin24m>; 290 clock-names = "pclk", "timer"; 291 }; 292 293 timer1: timer@20044020 { 294 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 295 reg = <0x20044020 0x20>; 296 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru PCLK_TIMER>, <&xin24m>; 298 clock-names = "pclk", "timer"; 299 }; 300 301 timer2: timer@20044040 { 302 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 303 reg = <0x20044040 0x20>; 304 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cru PCLK_TIMER>, <&xin24m>; 306 clock-names = "pclk", "timer"; 307 }; 308 309 timer3: timer@20044060 { 310 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 311 reg = <0x20044060 0x20>; 312 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru PCLK_TIMER>, <&xin24m>; 314 clock-names = "pclk", "timer"; 315 }; 316 317 timer4: timer@20044080 { 318 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 319 reg = <0x20044080 0x20>; 320 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cru PCLK_TIMER>, <&xin24m>; 322 clock-names = "pclk", "timer"; 323 }; 324 325 timer5: timer@200440a0 { 326 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 327 reg = <0x200440a0 0x20>; 328 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cru PCLK_TIMER>, <&xin24m>; 330 clock-names = "pclk", "timer"; 331 }; 332 333 watchdog: watchdog@2004c000 { 334 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 335 reg = <0x2004c000 0x100>; 336 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&cru PCLK_WDT>; 338 status = "disabled"; 339 }; 340 341 pwm0: pwm@20050000 { 342 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 343 reg = <0x20050000 0x10>; 344 clocks = <&cru PCLK_PWM>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pwm0_pin>; 347 #pwm-cells = <3>; 348 status = "disabled"; 349 }; 350 351 pwm1: pwm@20050010 { 352 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 353 reg = <0x20050010 0x10>; 354 clocks = <&cru PCLK_PWM>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pwm1_pin>; 357 #pwm-cells = <3>; 358 status = "disabled"; 359 }; 360 361 pwm2: pwm@20050020 { 362 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 363 reg = <0x20050020 0x10>; 364 clocks = <&cru PCLK_PWM>; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pwm2_pin>; 367 #pwm-cells = <3>; 368 status = "disabled"; 369 }; 370 371 pwm3: pwm@20050030 { 372 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 373 reg = <0x20050030 0x10>; 374 clocks = <&cru PCLK_PWM>; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pwm3_pin>; 377 #pwm-cells = <3>; 378 status = "disabled"; 379 }; 380 381 i2c1: i2c@20056000 { 382 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 383 reg = <0x20056000 0x1000>; 384 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 385 clock-names = "i2c"; 386 clocks = <&cru PCLK_I2C1>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&i2c1_xfer>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 status = "disabled"; 392 }; 393 394 i2c2: i2c@2005a000 { 395 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 396 reg = <0x2005a000 0x1000>; 397 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 398 clock-names = "i2c"; 399 clocks = <&cru PCLK_I2C2>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c2_xfer>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 status = "disabled"; 405 }; 406 407 i2c3: i2c@2005e000 { 408 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 409 reg = <0x2005e000 0x1000>; 410 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 411 clock-names = "i2c"; 412 clocks = <&cru PCLK_I2C3>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c3_xfer>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 uart0: serial@20060000 { 421 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 422 reg = <0x20060000 0x100>; 423 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 424 clock-frequency = <24000000>; 425 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 426 clock-names = "baudclk", "apb_pclk"; 427 dmas = <&pdma 2>, <&pdma 3>; 428 dma-names = "tx", "rx"; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 431 reg-io-width = <4>; 432 reg-shift = <2>; 433 status = "disabled"; 434 }; 435 436 uart1: serial@20064000 { 437 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 438 reg = <0x20064000 0x100>; 439 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 440 clock-frequency = <24000000>; 441 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 442 clock-names = "baudclk", "apb_pclk"; 443 dmas = <&pdma 4>, <&pdma 5>; 444 dma-names = "tx", "rx"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&uart1_xfer>; 447 reg-io-width = <4>; 448 reg-shift = <2>; 449 status = "disabled"; 450 }; 451 452 uart2: serial@20068000 { 453 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 454 reg = <0x20068000 0x100>; 455 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 456 clock-frequency = <24000000>; 457 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 458 clock-names = "baudclk", "apb_pclk"; 459 dmas = <&pdma 6>, <&pdma 7>; 460 dma-names = "tx", "rx"; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&uart2_xfer>; 463 reg-io-width = <4>; 464 reg-shift = <2>; 465 status = "disabled"; 466 }; 467 468 saradc: saradc@2006c000 { 469 compatible = "rockchip,saradc"; 470 reg = <0x2006c000 0x100>; 471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 473 clock-names = "saradc", "apb_pclk"; 474 resets = <&cru SRST_SARADC>; 475 reset-names = "saradc-apb"; 476 #io-channel-cells = <1>; 477 status = "disabled"; 478 }; 479 480 i2c0: i2c@20072000 { 481 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 482 reg = <20072000 0x1000>; 483 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 484 clock-names = "i2c"; 485 clocks = <&cru PCLK_I2C0>; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&i2c0_xfer>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 status = "disabled"; 491 }; 492 493 spi0: spi@20074000 { 494 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 495 reg = <0x20074000 0x1000>; 496 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 498 clock-names = "spiclk", "apb_pclk"; 499 dmas = <&pdma 8>, <&pdma 9>; 500 dma-names = "tx", "rx"; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 508 pdma: dma-controller@20078000 { 509 compatible = "arm,pl330", "arm,primecell"; 510 reg = <0x20078000 0x4000>; 511 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 513 arm,pl330-broken-no-flushp; 514 clocks = <&cru ACLK_DMAC>; 515 clock-names = "apb_pclk"; 516 #dma-cells = <1>; 517 }; 518 519 pinctrl: pinctrl { 520 compatible = "rockchip,rk3128-pinctrl"; 521 rockchip,grf = <&grf>; 522 #address-cells = <1>; 523 #size-cells = <1>; 524 ranges; 525 526 gpio0: gpio@2007c000 { 527 compatible = "rockchip,gpio-bank"; 528 reg = <0x2007c000 0x100>; 529 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cru PCLK_GPIO0>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 }; 536 537 gpio1: gpio@20080000 { 538 compatible = "rockchip,gpio-bank"; 539 reg = <0x20080000 0x100>; 540 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cru PCLK_GPIO1>; 542 gpio-controller; 543 #gpio-cells = <2>; 544 interrupt-controller; 545 #interrupt-cells = <2>; 546 }; 547 548 gpio2: gpio@20084000 { 549 compatible = "rockchip,gpio-bank"; 550 reg = <0x20084000 0x100>; 551 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cru PCLK_GPIO2>; 553 gpio-controller; 554 #gpio-cells = <2>; 555 interrupt-controller; 556 #interrupt-cells = <2>; 557 }; 558 559 gpio3: gpio@20088000 { 560 compatible = "rockchip,gpio-bank"; 561 reg = <0x20088000 0x100>; 562 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&cru PCLK_GPIO3>; 564 gpio-controller; 565 #gpio-cells = <2>; 566 interrupt-controller; 567 #interrupt-cells = <2>; 568 }; 569 570 pcfg_pull_default: pcfg-pull-default { 571 bias-pull-pin-default; 572 }; 573 574 pcfg_pull_none: pcfg-pull-none { 575 bias-disable; 576 }; 577 578 emmc { 579 emmc_clk: emmc-clk { 580 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 581 }; 582 583 emmc_cmd: emmc-cmd { 584 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 585 }; 586 587 emmc_cmd1: emmc-cmd1 { 588 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 589 }; 590 591 emmc_pwr: emmc-pwr { 592 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 593 }; 594 595 emmc_bus1: emmc-bus1 { 596 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 597 }; 598 599 emmc_bus4: emmc-bus4 { 600 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 601 <1 RK_PD1 2 &pcfg_pull_default>, 602 <1 RK_PD2 2 &pcfg_pull_default>, 603 <1 RK_PD3 2 &pcfg_pull_default>; 604 }; 605 606 emmc_bus8: emmc-bus8 { 607 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 608 <1 RK_PD1 2 &pcfg_pull_default>, 609 <1 RK_PD2 2 &pcfg_pull_default>, 610 <1 RK_PD3 2 &pcfg_pull_default>, 611 <1 RK_PD4 2 &pcfg_pull_default>, 612 <1 RK_PD5 2 &pcfg_pull_default>, 613 <1 RK_PD6 2 &pcfg_pull_default>, 614 <1 RK_PD7 2 &pcfg_pull_default>; 615 }; 616 }; 617 618 gmac { 619 rgmii_pins: rgmii-pins { 620 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 621 <2 RK_PB1 3 &pcfg_pull_default>, 622 <2 RK_PB3 3 &pcfg_pull_default>, 623 <2 RK_PB4 3 &pcfg_pull_default>, 624 <2 RK_PB5 3 &pcfg_pull_default>, 625 <2 RK_PB6 3 &pcfg_pull_default>, 626 <2 RK_PC0 3 &pcfg_pull_default>, 627 <2 RK_PC1 3 &pcfg_pull_default>, 628 <2 RK_PC2 3 &pcfg_pull_default>, 629 <2 RK_PC3 3 &pcfg_pull_default>, 630 <2 RK_PD1 3 &pcfg_pull_default>, 631 <2 RK_PC4 4 &pcfg_pull_default>, 632 <2 RK_PC5 4 &pcfg_pull_default>, 633 <2 RK_PC6 4 &pcfg_pull_default>, 634 <2 RK_PC7 4 &pcfg_pull_default>; 635 }; 636 637 rmii_pins: rmii-pins { 638 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 639 <2 RK_PB4 3 &pcfg_pull_default>, 640 <2 RK_PB5 3 &pcfg_pull_default>, 641 <2 RK_PB6 3 &pcfg_pull_default>, 642 <2 RK_PB7 3 &pcfg_pull_default>, 643 <2 RK_PC0 3 &pcfg_pull_default>, 644 <2 RK_PC1 3 &pcfg_pull_default>, 645 <2 RK_PC2 3 &pcfg_pull_default>, 646 <2 RK_PC3 3 &pcfg_pull_default>, 647 <2 RK_PD1 3 &pcfg_pull_default>; 648 }; 649 }; 650 651 hdmi { 652 hdmii2c_xfer: hdmii2c-xfer { 653 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 654 <0 RK_PA7 2 &pcfg_pull_none>; 655 }; 656 657 hdmi_hpd: hdmi-hpd { 658 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 659 }; 660 661 hdmi_cec: hdmi-cec { 662 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 663 }; 664 }; 665 666 i2c0 { 667 i2c0_xfer: i2c0-xfer { 668 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 669 <0 RK_PA1 1 &pcfg_pull_none>; 670 }; 671 }; 672 673 i2c1 { 674 i2c1_xfer: i2c1-xfer { 675 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 676 <0 RK_PA3 1 &pcfg_pull_none>; 677 }; 678 }; 679 680 i2c2 { 681 i2c2_xfer: i2c2-xfer { 682 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 683 <2 RK_PC5 3 &pcfg_pull_none>; 684 }; 685 }; 686 687 i2c3 { 688 i2c3_xfer: i2c3-xfer { 689 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 690 <0 RK_PA7 1 &pcfg_pull_none>; 691 }; 692 }; 693 694 i2s { 695 i2s_bus: i2s-bus { 696 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 697 <0 RK_PB1 1 &pcfg_pull_none>, 698 <0 RK_PB3 1 &pcfg_pull_none>, 699 <0 RK_PB4 1 &pcfg_pull_none>, 700 <0 RK_PB5 1 &pcfg_pull_none>, 701 <0 RK_PB6 1 &pcfg_pull_none>; 702 }; 703 704 i2s1_bus: i2s1-bus { 705 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 706 <1 RK_PA1 1 &pcfg_pull_none>, 707 <1 RK_PA2 1 &pcfg_pull_none>, 708 <1 RK_PA3 1 &pcfg_pull_none>, 709 <1 RK_PA4 1 &pcfg_pull_none>, 710 <1 RK_PA5 1 &pcfg_pull_none>; 711 }; 712 }; 713 714 lcdc { 715 lcdc_dclk: lcdc-dclk { 716 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 717 }; 718 719 lcdc_den: lcdc-den { 720 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 721 }; 722 723 lcdc_hsync: lcdc-hsync { 724 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 725 }; 726 727 lcdc_vsync: lcdc-vsync { 728 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 729 }; 730 731 lcdc_rgb24: lcdc-rgb24 { 732 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 733 <2 RK_PB5 1 &pcfg_pull_none>, 734 <2 RK_PB6 1 &pcfg_pull_none>, 735 <2 RK_PB7 1 &pcfg_pull_none>, 736 <2 RK_PC0 1 &pcfg_pull_none>, 737 <2 RK_PC1 1 &pcfg_pull_none>, 738 <2 RK_PC2 1 &pcfg_pull_none>, 739 <2 RK_PC3 1 &pcfg_pull_none>, 740 <2 RK_PC4 1 &pcfg_pull_none>, 741 <2 RK_PC5 1 &pcfg_pull_none>, 742 <2 RK_PC6 1 &pcfg_pull_none>, 743 <2 RK_PC7 1 &pcfg_pull_none>, 744 <2 RK_PD0 1 &pcfg_pull_none>, 745 <2 RK_PD1 1 &pcfg_pull_none>; 746 }; 747 }; 748 749 nfc { 750 flash_ale: flash-ale { 751 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 752 }; 753 754 flash_cle: flash-cle { 755 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 756 }; 757 758 flash_wrn: flash-wrn { 759 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 760 }; 761 762 flash_rdn: flash-rdn { 763 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 764 }; 765 766 flash_rdy: flash-rdy { 767 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 768 }; 769 770 flash_cs0: flash-cs0 { 771 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 772 }; 773 774 flash_dqs: flash-dqs { 775 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 776 }; 777 778 flash_bus8: flash-bus8 { 779 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 780 <1 RK_PD1 1 &pcfg_pull_none>, 781 <1 RK_PD2 1 &pcfg_pull_none>, 782 <1 RK_PD3 1 &pcfg_pull_none>, 783 <1 RK_PD4 1 &pcfg_pull_none>, 784 <1 RK_PD5 1 &pcfg_pull_none>, 785 <1 RK_PD6 1 &pcfg_pull_none>, 786 <1 RK_PD7 1 &pcfg_pull_none>; 787 }; 788 }; 789 790 pwm0 { 791 pwm0_pin: pwm0-pin { 792 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 793 }; 794 }; 795 796 pwm1 { 797 pwm1_pin: pwm1-pin { 798 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 799 }; 800 }; 801 802 pwm2 { 803 pwm2_pin: pwm2-pin { 804 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 805 }; 806 }; 807 808 pwm3 { 809 pwm3_pin: pwm3-pin { 810 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 811 }; 812 }; 813 814 sdio { 815 sdio_clk: sdio-clk { 816 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 817 }; 818 819 sdio_cmd: sdio-cmd { 820 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 821 }; 822 823 sdio_pwren: sdio-pwren { 824 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 825 }; 826 827 sdio_bus4: sdio-bus4 { 828 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 829 <1 RK_PA2 2 &pcfg_pull_default>, 830 <1 RK_PA4 2 &pcfg_pull_default>, 831 <1 RK_PA5 2 &pcfg_pull_default>; 832 }; 833 }; 834 835 sdmmc { 836 sdmmc_clk: sdmmc-clk { 837 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 838 }; 839 840 sdmmc_cmd: sdmmc-cmd { 841 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 842 }; 843 844 sdmmc_wp: sdmmc-wp { 845 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 846 }; 847 848 sdmmc_pwren: sdmmc-pwren { 849 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 850 }; 851 852 sdmmc_bus4: sdmmc-bus4 { 853 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 854 <1 RK_PC3 1 &pcfg_pull_default>, 855 <1 RK_PC4 1 &pcfg_pull_default>, 856 <1 RK_PC5 1 &pcfg_pull_default>; 857 }; 858 }; 859 860 spdif { 861 spdif_tx: spdif-tx { 862 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 863 }; 864 }; 865 866 spi0 { 867 spi0_clk: spi0-clk { 868 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 869 }; 870 871 spi0_cs0: spi0-cs0 { 872 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 873 }; 874 875 spi0_tx: spi0-tx { 876 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 877 }; 878 879 spi0_rx: spi0-rx { 880 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 881 }; 882 883 spi0_cs1: spi0-cs1 { 884 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 885 }; 886 887 spi1_clk: spi1-clk { 888 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 889 }; 890 891 spi1_cs0: spi1-cs0 { 892 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 893 }; 894 895 spi1_tx: spi1-tx { 896 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 897 }; 898 899 spi1_rx: spi1-rx { 900 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 901 }; 902 903 spi1_cs1: spi1-cs1 { 904 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 905 }; 906 907 spi2_clk: spi2-clk { 908 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 909 }; 910 911 spi2_cs0: spi2-cs0 { 912 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 913 }; 914 915 spi2_tx: spi2-tx { 916 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 917 }; 918 919 spi2_rx: spi2-rx { 920 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 921 }; 922 }; 923 924 uart0 { 925 uart0_xfer: uart0-xfer { 926 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 927 <2 RK_PD3 2 &pcfg_pull_none>; 928 }; 929 930 uart0_cts: uart0-cts { 931 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 932 }; 933 934 uart0_rts: uart0-rts { 935 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 936 }; 937 }; 938 939 uart1 { 940 uart1_xfer: uart1-xfer { 941 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 942 <1 RK_PB2 2 &pcfg_pull_default>; 943 }; 944 945 uart1_cts: uart1-cts { 946 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 947 }; 948 949 uart1_rts: uart1-rts { 950 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 951 }; 952 }; 953 954 uart2 { 955 uart2_xfer: uart2-xfer { 956 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 957 <1 RK_PC3 2 &pcfg_pull_none>; 958 }; 959 960 uart2_cts: uart2-cts { 961 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 962 }; 963 964 uart2_rts: uart2-rts { 965 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 966 }; 967 }; 968 }; 969}; 970