1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 arm-pmu { 20 compatible = "arm,cortex-a7-pmu"; 21 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 25 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 enable-method = "rockchip,rk3036-smp"; 32 33 cpu0: cpu@f00 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a7"; 36 reg = <0xf00>; 37 clock-latency = <40000>; 38 clocks = <&cru ARMCLK>; 39 resets = <&cru SRST_CORE0>; 40 operating-points-v2 = <&cpu_opp_table>; 41 #cooling-cells = <2>; /* min followed by max */ 42 }; 43 44 cpu1: cpu@f01 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a7"; 47 reg = <0xf01>; 48 resets = <&cru SRST_CORE1>; 49 operating-points-v2 = <&cpu_opp_table>; 50 }; 51 52 cpu2: cpu@f02 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0xf02>; 56 resets = <&cru SRST_CORE2>; 57 operating-points-v2 = <&cpu_opp_table>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 operating-points-v2 = <&cpu_opp_table>; 66 }; 67 }; 68 69 cpu_opp_table: opp-table-0 { 70 compatible = "operating-points-v2"; 71 opp-shared; 72 73 opp-216000000 { 74 opp-hz = /bits/ 64 <216000000>; 75 opp-microvolt = <950000 950000 1325000>; 76 }; 77 opp-408000000 { 78 opp-hz = /bits/ 64 <408000000>; 79 opp-microvolt = <950000 950000 1325000>; 80 }; 81 opp-600000000 { 82 opp-hz = /bits/ 64 <600000000>; 83 opp-microvolt = <950000 950000 1325000>; 84 }; 85 opp-696000000 { 86 opp-hz = /bits/ 64 <696000000>; 87 opp-microvolt = <975000 975000 1325000>; 88 }; 89 opp-816000000 { 90 opp-hz = /bits/ 64 <816000000>; 91 opp-microvolt = <1075000 1075000 1325000>; 92 opp-suspend; 93 }; 94 opp-1008000000 { 95 opp-hz = /bits/ 64 <1008000000>; 96 opp-microvolt = <1200000 1200000 1325000>; 97 }; 98 opp-1200000000 { 99 opp-hz = /bits/ 64 <1200000000>; 100 opp-microvolt = <1325000 1325000 1325000>; 101 }; 102 }; 103 104 gpu_opp_table: opp-table-1 { 105 compatible = "operating-points-v2"; 106 107 opp-200000000 { 108 opp-hz = /bits/ 64 <200000000>; 109 opp-microvolt = <975000 975000 1250000>; 110 }; 111 opp-300000000 { 112 opp-hz = /bits/ 64 <300000000>; 113 opp-microvolt = <1050000 1050000 1250000>; 114 }; 115 opp-400000000 { 116 opp-hz = /bits/ 64 <400000000>; 117 opp-microvolt = <1150000 1150000 1250000>; 118 }; 119 opp-480000000 { 120 opp-hz = /bits/ 64 <480000000>; 121 opp-microvolt = <1250000 1250000 1250000>; 122 }; 123 }; 124 125 timer { 126 compatible = "arm,armv7-timer"; 127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 131 arm,cpu-registers-not-fw-configured; 132 clock-frequency = <24000000>; 133 }; 134 135 xin24m: oscillator { 136 compatible = "fixed-clock"; 137 clock-frequency = <24000000>; 138 clock-output-names = "xin24m"; 139 #clock-cells = <0>; 140 }; 141 142 imem: sram@10080000 { 143 compatible = "mmio-sram"; 144 reg = <0x10080000 0x2000>; 145 #address-cells = <1>; 146 #size-cells = <1>; 147 ranges = <0 0x10080000 0x2000>; 148 149 smp-sram@0 { 150 compatible = "rockchip,rk3066-smp-sram"; 151 reg = <0x00 0x10>; 152 }; 153 }; 154 155 gpu: gpu@10090000 { 156 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 157 reg = <0x10090000 0x10000>; 158 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-names = "gp", 165 "gpmmu", 166 "pp0", 167 "ppmmu0", 168 "pp1", 169 "ppmmu1"; 170 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 171 clock-names = "bus", "core"; 172 operating-points-v2 = <&gpu_opp_table>; 173 resets = <&cru SRST_GPU>; 174 power-domains = <&power RK3128_PD_GPU>; 175 status = "disabled"; 176 }; 177 178 pmu: syscon@100a0000 { 179 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 180 reg = <0x100a0000 0x1000>; 181 182 power: power-controller { 183 compatible = "rockchip,rk3128-power-controller"; 184 #power-domain-cells = <1>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 power-domain@RK3128_PD_VIO { 189 reg = <RK3128_PD_VIO>; 190 clocks = <&cru ACLK_CIF>, 191 <&cru HCLK_CIF>, 192 <&cru DCLK_EBC>, 193 <&cru HCLK_EBC>, 194 <&cru ACLK_IEP>, 195 <&cru HCLK_IEP>, 196 <&cru ACLK_LCDC0>, 197 <&cru HCLK_LCDC0>, 198 <&cru PCLK_MIPI>, 199 <&cru ACLK_RGA>, 200 <&cru HCLK_RGA>, 201 <&cru ACLK_VIO0>, 202 <&cru ACLK_VIO1>, 203 <&cru HCLK_VIO>, 204 <&cru HCLK_VIO_H2P>, 205 <&cru DCLK_VOP>, 206 <&cru SCLK_VOP>; 207 pm_qos = <&qos_ebc>, 208 <&qos_iep>, 209 <&qos_lcdc>, 210 <&qos_rga>, 211 <&qos_vip>; 212 #power-domain-cells = <0>; 213 }; 214 215 power-domain@RK3128_PD_VIDEO { 216 reg = <RK3128_PD_VIDEO>; 217 clocks = <&cru ACLK_VDPU>, 218 <&cru HCLK_VDPU>, 219 <&cru ACLK_VEPU>, 220 <&cru HCLK_VEPU>, 221 <&cru SCLK_HEVC_CORE>; 222 pm_qos = <&qos_vpu>; 223 #power-domain-cells = <0>; 224 }; 225 226 power-domain@RK3128_PD_GPU { 227 reg = <RK3128_PD_GPU>; 228 clocks = <&cru ACLK_GPU>; 229 pm_qos = <&qos_gpu>; 230 #power-domain-cells = <0>; 231 }; 232 }; 233 }; 234 235 qos_gpu: qos@1012d000 { 236 compatible = "rockchip,rk3128-qos", "syscon"; 237 reg = <0x1012d000 0x20>; 238 }; 239 240 qos_vpu: qos@1012e000 { 241 compatible = "rockchip,rk3128-qos", "syscon"; 242 reg = <0x1012e000 0x20>; 243 }; 244 245 qos_rga: qos@1012f000 { 246 compatible = "rockchip,rk3128-qos", "syscon"; 247 reg = <0x1012f000 0x20>; 248 }; 249 250 qos_ebc: qos@1012f080 { 251 compatible = "rockchip,rk3128-qos", "syscon"; 252 reg = <0x1012f080 0x20>; 253 }; 254 255 qos_iep: qos@1012f100 { 256 compatible = "rockchip,rk3128-qos", "syscon"; 257 reg = <0x1012f100 0x20>; 258 }; 259 260 qos_lcdc: qos@1012f180 { 261 compatible = "rockchip,rk3128-qos", "syscon"; 262 reg = <0x1012f180 0x20>; 263 }; 264 265 qos_vip: qos@1012f200 { 266 compatible = "rockchip,rk3128-qos", "syscon"; 267 reg = <0x1012f200 0x20>; 268 }; 269 270 gic: interrupt-controller@10139000 { 271 compatible = "arm,cortex-a7-gic"; 272 reg = <0x10139000 0x1000>, 273 <0x1013a000 0x1000>, 274 <0x1013c000 0x2000>, 275 <0x1013e000 0x2000>; 276 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 277 interrupt-controller; 278 #interrupt-cells = <3>; 279 #address-cells = <0>; 280 }; 281 282 usb_otg: usb@10180000 { 283 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 284 reg = <0x10180000 0x40000>; 285 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cru HCLK_OTG>; 287 clock-names = "otg"; 288 dr_mode = "otg"; 289 g-np-tx-fifo-size = <16>; 290 g-rx-fifo-size = <280>; 291 g-tx-fifo-size = <256 128 128 64 32 16>; 292 phys = <&usb2phy_otg>; 293 phy-names = "usb2-phy"; 294 status = "disabled"; 295 }; 296 297 usb_host_ehci: usb@101c0000 { 298 compatible = "generic-ehci"; 299 reg = <0x101c0000 0x20000>; 300 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cru HCLK_HOST2>; 302 phys = <&usb2phy_host>; 303 phy-names = "usb"; 304 status = "disabled"; 305 }; 306 307 usb_host_ohci: usb@101e0000 { 308 compatible = "generic-ohci"; 309 reg = <0x101e0000 0x20000>; 310 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cru HCLK_HOST2>; 312 phys = <&usb2phy_host>; 313 phy-names = "usb"; 314 status = "disabled"; 315 }; 316 317 sdmmc: mmc@10214000 { 318 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 319 reg = <0x10214000 0x4000>; 320 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 322 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 323 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 324 dmas = <&pdma 10>; 325 dma-names = "rx-tx"; 326 fifo-depth = <256>; 327 max-frequency = <150000000>; 328 resets = <&cru SRST_SDMMC>; 329 reset-names = "reset"; 330 status = "disabled"; 331 }; 332 333 sdio: mmc@10218000 { 334 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 335 reg = <0x10218000 0x4000>; 336 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 338 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 339 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 340 dmas = <&pdma 11>; 341 dma-names = "rx-tx"; 342 fifo-depth = <256>; 343 max-frequency = <150000000>; 344 resets = <&cru SRST_SDIO>; 345 reset-names = "reset"; 346 status = "disabled"; 347 }; 348 349 emmc: mmc@1021c000 { 350 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 351 reg = <0x1021c000 0x4000>; 352 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 354 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 355 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 356 dmas = <&pdma 12>; 357 dma-names = "rx-tx"; 358 fifo-depth = <256>; 359 max-frequency = <150000000>; 360 resets = <&cru SRST_EMMC>; 361 reset-names = "reset"; 362 status = "disabled"; 363 }; 364 365 nfc: nand-controller@10500000 { 366 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 367 reg = <0x10500000 0x4000>; 368 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 370 clock-names = "ahb", "nfc"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 373 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 374 status = "disabled"; 375 }; 376 377 cru: clock-controller@20000000 { 378 compatible = "rockchip,rk3128-cru"; 379 reg = <0x20000000 0x1000>; 380 clocks = <&xin24m>; 381 clock-names = "xin24m"; 382 rockchip,grf = <&grf>; 383 #clock-cells = <1>; 384 #reset-cells = <1>; 385 assigned-clocks = <&cru PLL_GPLL>; 386 assigned-clock-rates = <594000000>; 387 }; 388 389 grf: syscon@20008000 { 390 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 391 reg = <0x20008000 0x1000>; 392 #address-cells = <1>; 393 #size-cells = <1>; 394 395 usb2phy: usb2phy@17c { 396 compatible = "rockchip,rk3128-usb2phy"; 397 reg = <0x017c 0x0c>; 398 clocks = <&cru SCLK_OTGPHY0>; 399 clock-names = "phyclk"; 400 clock-output-names = "usb480m_phy"; 401 assigned-clocks = <&cru SCLK_USB480M>; 402 assigned-clock-parents = <&usb2phy>; 403 #clock-cells = <0>; 404 status = "disabled"; 405 406 usb2phy_host: host-port { 407 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 408 interrupt-names = "linestate"; 409 #phy-cells = <0>; 410 status = "disabled"; 411 }; 412 413 usb2phy_otg: otg-port { 414 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-names = "otg-bvalid", "otg-id", 418 "linestate"; 419 #phy-cells = <0>; 420 status = "disabled"; 421 }; 422 }; 423 }; 424 425 timer0: timer@20044000 { 426 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 427 reg = <0x20044000 0x20>; 428 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 430 clock-names = "pclk", "timer"; 431 }; 432 433 timer1: timer@20044020 { 434 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 435 reg = <0x20044020 0x20>; 436 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 438 clock-names = "pclk", "timer"; 439 }; 440 441 timer2: timer@20044040 { 442 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 443 reg = <0x20044040 0x20>; 444 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 446 clock-names = "pclk", "timer"; 447 }; 448 449 timer3: timer@20044060 { 450 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 451 reg = <0x20044060 0x20>; 452 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 454 clock-names = "pclk", "timer"; 455 }; 456 457 timer4: timer@20044080 { 458 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 459 reg = <0x20044080 0x20>; 460 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 462 clock-names = "pclk", "timer"; 463 }; 464 465 timer5: timer@200440a0 { 466 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 467 reg = <0x200440a0 0x20>; 468 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 470 clock-names = "pclk", "timer"; 471 }; 472 473 watchdog: watchdog@2004c000 { 474 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 475 reg = <0x2004c000 0x100>; 476 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&cru PCLK_WDT>; 478 status = "disabled"; 479 }; 480 481 pwm0: pwm@20050000 { 482 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 483 reg = <0x20050000 0x10>; 484 clocks = <&cru PCLK_PWM>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pwm0_pin>; 487 #pwm-cells = <3>; 488 status = "disabled"; 489 }; 490 491 pwm1: pwm@20050010 { 492 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 493 reg = <0x20050010 0x10>; 494 clocks = <&cru PCLK_PWM>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pwm1_pin>; 497 #pwm-cells = <3>; 498 status = "disabled"; 499 }; 500 501 pwm2: pwm@20050020 { 502 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 503 reg = <0x20050020 0x10>; 504 clocks = <&cru PCLK_PWM>; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pwm2_pin>; 507 #pwm-cells = <3>; 508 status = "disabled"; 509 }; 510 511 pwm3: pwm@20050030 { 512 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 513 reg = <0x20050030 0x10>; 514 clocks = <&cru PCLK_PWM>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pwm3_pin>; 517 #pwm-cells = <3>; 518 status = "disabled"; 519 }; 520 521 i2c1: i2c@20056000 { 522 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 523 reg = <0x20056000 0x1000>; 524 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 525 clock-names = "i2c"; 526 clocks = <&cru PCLK_I2C1>; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&i2c1_xfer>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 status = "disabled"; 532 }; 533 534 i2c2: i2c@2005a000 { 535 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 536 reg = <0x2005a000 0x1000>; 537 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 538 clock-names = "i2c"; 539 clocks = <&cru PCLK_I2C2>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&i2c2_xfer>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 status = "disabled"; 545 }; 546 547 i2c3: i2c@2005e000 { 548 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 549 reg = <0x2005e000 0x1000>; 550 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 551 clock-names = "i2c"; 552 clocks = <&cru PCLK_I2C3>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&i2c3_xfer>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 status = "disabled"; 558 }; 559 560 uart0: serial@20060000 { 561 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 562 reg = <0x20060000 0x100>; 563 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 564 clock-frequency = <24000000>; 565 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 566 clock-names = "baudclk", "apb_pclk"; 567 dmas = <&pdma 2>, <&pdma 3>; 568 dma-names = "tx", "rx"; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 571 reg-io-width = <4>; 572 reg-shift = <2>; 573 status = "disabled"; 574 }; 575 576 uart1: serial@20064000 { 577 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 578 reg = <0x20064000 0x100>; 579 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 580 clock-frequency = <24000000>; 581 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 582 clock-names = "baudclk", "apb_pclk"; 583 dmas = <&pdma 4>, <&pdma 5>; 584 dma-names = "tx", "rx"; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&uart1_xfer>; 587 reg-io-width = <4>; 588 reg-shift = <2>; 589 status = "disabled"; 590 }; 591 592 uart2: serial@20068000 { 593 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 594 reg = <0x20068000 0x100>; 595 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 596 clock-frequency = <24000000>; 597 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 598 clock-names = "baudclk", "apb_pclk"; 599 dmas = <&pdma 6>, <&pdma 7>; 600 dma-names = "tx", "rx"; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&uart2_xfer>; 603 reg-io-width = <4>; 604 reg-shift = <2>; 605 status = "disabled"; 606 }; 607 608 saradc: saradc@2006c000 { 609 compatible = "rockchip,saradc"; 610 reg = <0x2006c000 0x100>; 611 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 613 clock-names = "saradc", "apb_pclk"; 614 resets = <&cru SRST_SARADC>; 615 reset-names = "saradc-apb"; 616 #io-channel-cells = <1>; 617 status = "disabled"; 618 }; 619 620 i2c0: i2c@20072000 { 621 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 622 reg = <0x20072000 0x1000>; 623 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 624 clock-names = "i2c"; 625 clocks = <&cru PCLK_I2C0>; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&i2c0_xfer>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 spi0: spi@20074000 { 634 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 635 reg = <0x20074000 0x1000>; 636 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 638 clock-names = "spiclk", "apb_pclk"; 639 dmas = <&pdma 8>, <&pdma 9>; 640 dma-names = "tx", "rx"; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 648 pdma: dma-controller@20078000 { 649 compatible = "arm,pl330", "arm,primecell"; 650 reg = <0x20078000 0x4000>; 651 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 653 arm,pl330-broken-no-flushp; 654 arm,pl330-periph-burst; 655 clocks = <&cru ACLK_DMAC>; 656 clock-names = "apb_pclk"; 657 #dma-cells = <1>; 658 }; 659 660 gmac: ethernet@2008c000 { 661 compatible = "rockchip,rk3128-gmac"; 662 reg = <0x2008c000 0x4000>; 663 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 665 interrupt-names = "macirq", "eth_wake_irq"; 666 clocks = <&cru SCLK_MAC>, 667 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 668 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 669 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 670 clock-names = "stmmaceth", 671 "mac_clk_rx", "mac_clk_tx", 672 "clk_mac_ref", "clk_mac_refout", 673 "aclk_mac", "pclk_mac"; 674 resets = <&cru SRST_GMAC>; 675 reset-names = "stmmaceth"; 676 rockchip,grf = <&grf>; 677 rx-fifo-depth = <4096>; 678 tx-fifo-depth = <2048>; 679 status = "disabled"; 680 681 mdio: mdio { 682 compatible = "snps,dwmac-mdio"; 683 #address-cells = <0x1>; 684 #size-cells = <0x0>; 685 }; 686 }; 687 688 pinctrl: pinctrl { 689 compatible = "rockchip,rk3128-pinctrl"; 690 rockchip,grf = <&grf>; 691 #address-cells = <1>; 692 #size-cells = <1>; 693 ranges; 694 695 gpio0: gpio@2007c000 { 696 compatible = "rockchip,gpio-bank"; 697 reg = <0x2007c000 0x100>; 698 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru PCLK_GPIO0>; 700 gpio-controller; 701 #gpio-cells = <2>; 702 interrupt-controller; 703 #interrupt-cells = <2>; 704 }; 705 706 gpio1: gpio@20080000 { 707 compatible = "rockchip,gpio-bank"; 708 reg = <0x20080000 0x100>; 709 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&cru PCLK_GPIO1>; 711 gpio-controller; 712 #gpio-cells = <2>; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 717 gpio2: gpio@20084000 { 718 compatible = "rockchip,gpio-bank"; 719 reg = <0x20084000 0x100>; 720 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cru PCLK_GPIO2>; 722 gpio-controller; 723 #gpio-cells = <2>; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 728 gpio3: gpio@20088000 { 729 compatible = "rockchip,gpio-bank"; 730 reg = <0x20088000 0x100>; 731 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&cru PCLK_GPIO3>; 733 gpio-controller; 734 #gpio-cells = <2>; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 739 pcfg_pull_default: pcfg-pull-default { 740 bias-pull-pin-default; 741 }; 742 743 pcfg_pull_none: pcfg-pull-none { 744 bias-disable; 745 }; 746 747 emmc { 748 emmc_clk: emmc-clk { 749 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 750 }; 751 752 emmc_cmd: emmc-cmd { 753 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 754 }; 755 756 emmc_cmd1: emmc-cmd1 { 757 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 758 }; 759 760 emmc_pwr: emmc-pwr { 761 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 762 }; 763 764 emmc_bus1: emmc-bus1 { 765 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 766 }; 767 768 emmc_bus4: emmc-bus4 { 769 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 770 <1 RK_PD1 2 &pcfg_pull_default>, 771 <1 RK_PD2 2 &pcfg_pull_default>, 772 <1 RK_PD3 2 &pcfg_pull_default>; 773 }; 774 775 emmc_bus8: emmc-bus8 { 776 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 777 <1 RK_PD1 2 &pcfg_pull_default>, 778 <1 RK_PD2 2 &pcfg_pull_default>, 779 <1 RK_PD3 2 &pcfg_pull_default>, 780 <1 RK_PD4 2 &pcfg_pull_default>, 781 <1 RK_PD5 2 &pcfg_pull_default>, 782 <1 RK_PD6 2 &pcfg_pull_default>, 783 <1 RK_PD7 2 &pcfg_pull_default>; 784 }; 785 }; 786 787 gmac { 788 rgmii_pins: rgmii-pins { 789 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 790 <2 RK_PB1 3 &pcfg_pull_default>, 791 <2 RK_PB3 3 &pcfg_pull_default>, 792 <2 RK_PB4 3 &pcfg_pull_default>, 793 <2 RK_PB5 3 &pcfg_pull_default>, 794 <2 RK_PB6 3 &pcfg_pull_default>, 795 <2 RK_PC0 3 &pcfg_pull_default>, 796 <2 RK_PC1 3 &pcfg_pull_default>, 797 <2 RK_PC2 3 &pcfg_pull_default>, 798 <2 RK_PC3 3 &pcfg_pull_default>, 799 <2 RK_PD1 3 &pcfg_pull_default>, 800 <2 RK_PC4 4 &pcfg_pull_default>, 801 <2 RK_PC5 4 &pcfg_pull_default>, 802 <2 RK_PC6 4 &pcfg_pull_default>, 803 <2 RK_PC7 4 &pcfg_pull_default>; 804 }; 805 806 rmii_pins: rmii-pins { 807 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 808 <2 RK_PB4 3 &pcfg_pull_default>, 809 <2 RK_PB5 3 &pcfg_pull_default>, 810 <2 RK_PB6 3 &pcfg_pull_default>, 811 <2 RK_PB7 3 &pcfg_pull_default>, 812 <2 RK_PC0 3 &pcfg_pull_default>, 813 <2 RK_PC1 3 &pcfg_pull_default>, 814 <2 RK_PC2 3 &pcfg_pull_default>, 815 <2 RK_PC3 3 &pcfg_pull_default>, 816 <2 RK_PD1 3 &pcfg_pull_default>; 817 }; 818 }; 819 820 hdmi { 821 hdmii2c_xfer: hdmii2c-xfer { 822 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 823 <0 RK_PA7 2 &pcfg_pull_none>; 824 }; 825 826 hdmi_hpd: hdmi-hpd { 827 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 828 }; 829 830 hdmi_cec: hdmi-cec { 831 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 832 }; 833 }; 834 835 i2c0 { 836 i2c0_xfer: i2c0-xfer { 837 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 838 <0 RK_PA1 1 &pcfg_pull_none>; 839 }; 840 }; 841 842 i2c1 { 843 i2c1_xfer: i2c1-xfer { 844 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 845 <0 RK_PA3 1 &pcfg_pull_none>; 846 }; 847 }; 848 849 i2c2 { 850 i2c2_xfer: i2c2-xfer { 851 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 852 <2 RK_PC5 3 &pcfg_pull_none>; 853 }; 854 }; 855 856 i2c3 { 857 i2c3_xfer: i2c3-xfer { 858 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 859 <0 RK_PA7 1 &pcfg_pull_none>; 860 }; 861 }; 862 863 i2s { 864 i2s_bus: i2s-bus { 865 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 866 <0 RK_PB1 1 &pcfg_pull_none>, 867 <0 RK_PB3 1 &pcfg_pull_none>, 868 <0 RK_PB4 1 &pcfg_pull_none>, 869 <0 RK_PB5 1 &pcfg_pull_none>, 870 <0 RK_PB6 1 &pcfg_pull_none>; 871 }; 872 873 i2s1_bus: i2s1-bus { 874 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 875 <1 RK_PA1 1 &pcfg_pull_none>, 876 <1 RK_PA2 1 &pcfg_pull_none>, 877 <1 RK_PA3 1 &pcfg_pull_none>, 878 <1 RK_PA4 1 &pcfg_pull_none>, 879 <1 RK_PA5 1 &pcfg_pull_none>; 880 }; 881 }; 882 883 lcdc { 884 lcdc_dclk: lcdc-dclk { 885 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 886 }; 887 888 lcdc_den: lcdc-den { 889 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 890 }; 891 892 lcdc_hsync: lcdc-hsync { 893 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 894 }; 895 896 lcdc_vsync: lcdc-vsync { 897 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 898 }; 899 900 lcdc_rgb24: lcdc-rgb24 { 901 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 902 <2 RK_PB5 1 &pcfg_pull_none>, 903 <2 RK_PB6 1 &pcfg_pull_none>, 904 <2 RK_PB7 1 &pcfg_pull_none>, 905 <2 RK_PC0 1 &pcfg_pull_none>, 906 <2 RK_PC1 1 &pcfg_pull_none>, 907 <2 RK_PC2 1 &pcfg_pull_none>, 908 <2 RK_PC3 1 &pcfg_pull_none>, 909 <2 RK_PC4 1 &pcfg_pull_none>, 910 <2 RK_PC5 1 &pcfg_pull_none>, 911 <2 RK_PC6 1 &pcfg_pull_none>, 912 <2 RK_PC7 1 &pcfg_pull_none>, 913 <2 RK_PD0 1 &pcfg_pull_none>, 914 <2 RK_PD1 1 &pcfg_pull_none>; 915 }; 916 }; 917 918 nfc { 919 flash_ale: flash-ale { 920 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 921 }; 922 923 flash_cle: flash-cle { 924 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 925 }; 926 927 flash_wrn: flash-wrn { 928 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 929 }; 930 931 flash_rdn: flash-rdn { 932 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 933 }; 934 935 flash_rdy: flash-rdy { 936 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 937 }; 938 939 flash_cs0: flash-cs0 { 940 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 941 }; 942 943 flash_dqs: flash-dqs { 944 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 945 }; 946 947 flash_bus8: flash-bus8 { 948 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 949 <1 RK_PD1 1 &pcfg_pull_none>, 950 <1 RK_PD2 1 &pcfg_pull_none>, 951 <1 RK_PD3 1 &pcfg_pull_none>, 952 <1 RK_PD4 1 &pcfg_pull_none>, 953 <1 RK_PD5 1 &pcfg_pull_none>, 954 <1 RK_PD6 1 &pcfg_pull_none>, 955 <1 RK_PD7 1 &pcfg_pull_none>; 956 }; 957 }; 958 959 pwm0 { 960 pwm0_pin: pwm0-pin { 961 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 962 }; 963 }; 964 965 pwm1 { 966 pwm1_pin: pwm1-pin { 967 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 968 }; 969 }; 970 971 pwm2 { 972 pwm2_pin: pwm2-pin { 973 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 974 }; 975 }; 976 977 pwm3 { 978 pwm3_pin: pwm3-pin { 979 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 980 }; 981 }; 982 983 sdio { 984 sdio_clk: sdio-clk { 985 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 986 }; 987 988 sdio_cmd: sdio-cmd { 989 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 990 }; 991 992 sdio_pwren: sdio-pwren { 993 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 994 }; 995 996 sdio_bus4: sdio-bus4 { 997 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 998 <1 RK_PA2 2 &pcfg_pull_default>, 999 <1 RK_PA4 2 &pcfg_pull_default>, 1000 <1 RK_PA5 2 &pcfg_pull_default>; 1001 }; 1002 }; 1003 1004 sdmmc { 1005 sdmmc_clk: sdmmc-clk { 1006 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1007 }; 1008 1009 sdmmc_cmd: sdmmc-cmd { 1010 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1011 }; 1012 1013 sdmmc_det: sdmmc-det { 1014 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1015 }; 1016 1017 sdmmc_wp: sdmmc-wp { 1018 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1019 }; 1020 1021 sdmmc_pwren: sdmmc-pwren { 1022 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 1023 }; 1024 1025 sdmmc_bus4: sdmmc-bus4 { 1026 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1027 <1 RK_PC3 1 &pcfg_pull_default>, 1028 <1 RK_PC4 1 &pcfg_pull_default>, 1029 <1 RK_PC5 1 &pcfg_pull_default>; 1030 }; 1031 }; 1032 1033 spdif { 1034 spdif_tx: spdif-tx { 1035 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1036 }; 1037 }; 1038 1039 spi0 { 1040 spi0_clk: spi0-clk { 1041 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1042 }; 1043 1044 spi0_cs0: spi0-cs0 { 1045 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1046 }; 1047 1048 spi0_tx: spi0-tx { 1049 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1050 }; 1051 1052 spi0_rx: spi0-rx { 1053 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1054 }; 1055 1056 spi0_cs1: spi0-cs1 { 1057 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1058 }; 1059 1060 spi1_clk: spi1-clk { 1061 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1062 }; 1063 1064 spi1_cs0: spi1-cs0 { 1065 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1066 }; 1067 1068 spi1_tx: spi1-tx { 1069 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1070 }; 1071 1072 spi1_rx: spi1-rx { 1073 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1074 }; 1075 1076 spi1_cs1: spi1-cs1 { 1077 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1078 }; 1079 1080 spi2_clk: spi2-clk { 1081 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1082 }; 1083 1084 spi2_cs0: spi2-cs0 { 1085 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1086 }; 1087 1088 spi2_tx: spi2-tx { 1089 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1090 }; 1091 1092 spi2_rx: spi2-rx { 1093 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1094 }; 1095 }; 1096 1097 uart0 { 1098 uart0_xfer: uart0-xfer { 1099 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1100 <2 RK_PD3 2 &pcfg_pull_none>; 1101 }; 1102 1103 uart0_cts: uart0-cts { 1104 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1105 }; 1106 1107 uart0_rts: uart0-rts { 1108 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1109 }; 1110 }; 1111 1112 uart1 { 1113 uart1_xfer: uart1-xfer { 1114 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1115 <1 RK_PB2 2 &pcfg_pull_default>; 1116 }; 1117 1118 uart1_cts: uart1-cts { 1119 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1120 }; 1121 1122 uart1_rts: uart1-rts { 1123 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1124 }; 1125 }; 1126 1127 uart2 { 1128 uart2_xfer: uart2-xfer { 1129 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1130 <1 RK_PC3 2 &pcfg_pull_none>; 1131 }; 1132 1133 uart2_cts: uart2-cts { 1134 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1135 }; 1136 1137 uart2_rts: uart2-rts { 1138 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1139 }; 1140 }; 1141 }; 1142}; 1143