1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@f00 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0xf00>; 35 clock-latency = <40000>; 36 clocks = <&cru ARMCLK>; 37 operating-points = < 38 /* KHz uV */ 39 816000 1000000 40 >; 41 #cooling-cells = <2>; /* min followed by max */ 42 }; 43 44 cpu1: cpu@f01 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a7"; 47 reg = <0xf01>; 48 }; 49 50 cpu2: cpu@f02 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a7"; 53 reg = <0xf02>; 54 }; 55 56 cpu3: cpu@f03 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a7"; 59 reg = <0xf03>; 60 }; 61 }; 62 63 timer { 64 compatible = "arm,armv7-timer"; 65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 68 arm,cpu-registers-not-fw-configured; 69 clock-frequency = <24000000>; 70 }; 71 72 xin24m: oscillator { 73 compatible = "fixed-clock"; 74 clock-frequency = <24000000>; 75 clock-output-names = "xin24m"; 76 #clock-cells = <0>; 77 }; 78 79 imem: sram@10080000 { 80 compatible = "mmio-sram"; 81 reg = <0x10080000 0x2000>; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges = <0 0x10080000 0x2000>; 85 }; 86 87 pmu: syscon@100a0000 { 88 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 89 reg = <0x100a0000 0x1000>; 90 }; 91 92 gic: interrupt-controller@10139000 { 93 compatible = "arm,cortex-a7-gic"; 94 reg = <0x10139000 0x1000>, 95 <0x1013a000 0x1000>, 96 <0x1013c000 0x2000>, 97 <0x1013e000 0x2000>; 98 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 99 interrupt-controller; 100 #interrupt-cells = <3>; 101 #address-cells = <0>; 102 }; 103 104 usb_otg: usb@10180000 { 105 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 106 reg = <0x10180000 0x40000>; 107 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&cru HCLK_OTG>; 109 clock-names = "otg"; 110 dr_mode = "otg"; 111 phys = <&usb2phy_otg>; 112 phy-names = "usb2-phy"; 113 status = "disabled"; 114 }; 115 116 usb_host_ehci: usb@101c0000 { 117 compatible = "generic-ehci"; 118 reg = <0x101c0000 0x20000>; 119 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 120 phys = <&usb2phy_host>; 121 phy-names = "usb"; 122 status = "disabled"; 123 }; 124 125 usb_host_ohci: usb@101e0000 { 126 compatible = "generic-ohci"; 127 reg = <0x101e0000 0x20000>; 128 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 129 phys = <&usb2phy_host>; 130 phy-names = "usb"; 131 status = "disabled"; 132 }; 133 134 sdmmc: mmc@10214000 { 135 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 136 reg = <0x10214000 0x4000>; 137 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 139 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 140 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 141 dmas = <&pdma 10>; 142 dma-names = "rx-tx"; 143 fifo-depth = <256>; 144 max-frequency = <150000000>; 145 resets = <&cru SRST_SDMMC>; 146 reset-names = "reset"; 147 status = "disabled"; 148 }; 149 150 sdio: mmc@10218000 { 151 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 152 reg = <0x10218000 0x4000>; 153 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 155 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 156 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 157 dmas = <&pdma 11>; 158 dma-names = "rx-tx"; 159 fifo-depth = <256>; 160 max-frequency = <150000000>; 161 resets = <&cru SRST_SDIO>; 162 reset-names = "reset"; 163 status = "disabled"; 164 }; 165 166 emmc: mmc@1021c000 { 167 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 168 reg = <0x1021c000 0x4000>; 169 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 171 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 172 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 173 dmas = <&pdma 12>; 174 dma-names = "rx-tx"; 175 fifo-depth = <256>; 176 max-frequency = <150000000>; 177 resets = <&cru SRST_EMMC>; 178 reset-names = "reset"; 179 status = "disabled"; 180 }; 181 182 nfc: nand-controller@10500000 { 183 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 184 reg = <0x10500000 0x4000>; 185 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 187 clock-names = "ahb", "nfc"; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 190 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 191 status = "disabled"; 192 }; 193 194 cru: clock-controller@20000000 { 195 compatible = "rockchip,rk3128-cru"; 196 reg = <0x20000000 0x1000>; 197 clocks = <&xin24m>; 198 clock-names = "xin24m"; 199 rockchip,grf = <&grf>; 200 #clock-cells = <1>; 201 #reset-cells = <1>; 202 assigned-clocks = <&cru PLL_GPLL>; 203 assigned-clock-rates = <594000000>; 204 }; 205 206 grf: syscon@20008000 { 207 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 208 reg = <0x20008000 0x1000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 212 usb2phy: usb2phy@17c { 213 compatible = "rockchip,rk3128-usb2phy"; 214 reg = <0x017c 0x0c>; 215 clocks = <&cru SCLK_OTGPHY0>; 216 clock-names = "phyclk"; 217 clock-output-names = "usb480m_phy"; 218 #clock-cells = <0>; 219 status = "disabled"; 220 221 usb2phy_host: host-port { 222 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 223 interrupt-names = "linestate"; 224 #phy-cells = <0>; 225 status = "disabled"; 226 }; 227 228 usb2phy_otg: otg-port { 229 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 232 interrupt-names = "otg-bvalid", "otg-id", 233 "linestate"; 234 #phy-cells = <0>; 235 status = "disabled"; 236 }; 237 }; 238 }; 239 240 timer0: timer@20044000 { 241 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 242 reg = <0x20044000 0x20>; 243 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cru PCLK_TIMER>, <&xin24m>; 245 clock-names = "pclk", "timer"; 246 }; 247 248 timer1: timer@20044020 { 249 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 250 reg = <0x20044020 0x20>; 251 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&cru PCLK_TIMER>, <&xin24m>; 253 clock-names = "pclk", "timer"; 254 }; 255 256 timer2: timer@20044040 { 257 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 258 reg = <0x20044040 0x20>; 259 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&cru PCLK_TIMER>, <&xin24m>; 261 clock-names = "pclk", "timer"; 262 }; 263 264 timer3: timer@20044060 { 265 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 266 reg = <0x20044060 0x20>; 267 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cru PCLK_TIMER>, <&xin24m>; 269 clock-names = "pclk", "timer"; 270 }; 271 272 timer4: timer@20044080 { 273 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 274 reg = <0x20044080 0x20>; 275 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cru PCLK_TIMER>, <&xin24m>; 277 clock-names = "pclk", "timer"; 278 }; 279 280 timer5: timer@200440a0 { 281 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 282 reg = <0x200440a0 0x20>; 283 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&cru PCLK_TIMER>, <&xin24m>; 285 clock-names = "pclk", "timer"; 286 }; 287 288 watchdog: watchdog@2004c000 { 289 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 290 reg = <0x2004c000 0x100>; 291 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru PCLK_WDT>; 293 status = "disabled"; 294 }; 295 296 pwm0: pwm@20050000 { 297 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 298 reg = <0x20050000 0x10>; 299 clocks = <&cru PCLK_PWM>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pwm0_pin>; 302 #pwm-cells = <3>; 303 status = "disabled"; 304 }; 305 306 pwm1: pwm@20050010 { 307 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 308 reg = <0x20050010 0x10>; 309 clocks = <&cru PCLK_PWM>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pwm1_pin>; 312 #pwm-cells = <3>; 313 status = "disabled"; 314 }; 315 316 pwm2: pwm@20050020 { 317 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 318 reg = <0x20050020 0x10>; 319 clocks = <&cru PCLK_PWM>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pwm2_pin>; 322 #pwm-cells = <3>; 323 status = "disabled"; 324 }; 325 326 pwm3: pwm@20050030 { 327 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 328 reg = <0x20050030 0x10>; 329 clocks = <&cru PCLK_PWM>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pwm3_pin>; 332 #pwm-cells = <3>; 333 status = "disabled"; 334 }; 335 336 i2c1: i2c@20056000 { 337 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 338 reg = <0x20056000 0x1000>; 339 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 340 clock-names = "i2c"; 341 clocks = <&cru PCLK_I2C1>; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&i2c1_xfer>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 status = "disabled"; 347 }; 348 349 i2c2: i2c@2005a000 { 350 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 351 reg = <0x2005a000 0x1000>; 352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 353 clock-names = "i2c"; 354 clocks = <&cru PCLK_I2C2>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&i2c2_xfer>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 status = "disabled"; 360 }; 361 362 i2c3: i2c@2005e000 { 363 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 364 reg = <0x2005e000 0x1000>; 365 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 366 clock-names = "i2c"; 367 clocks = <&cru PCLK_I2C3>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2c3_xfer>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 uart0: serial@20060000 { 376 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 377 reg = <0x20060000 0x100>; 378 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 379 clock-frequency = <24000000>; 380 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 381 clock-names = "baudclk", "apb_pclk"; 382 dmas = <&pdma 2>, <&pdma 3>; 383 dma-names = "tx", "rx"; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 386 reg-io-width = <4>; 387 reg-shift = <2>; 388 status = "disabled"; 389 }; 390 391 uart1: serial@20064000 { 392 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 393 reg = <0x20064000 0x100>; 394 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 395 clock-frequency = <24000000>; 396 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 397 clock-names = "baudclk", "apb_pclk"; 398 dmas = <&pdma 4>, <&pdma 5>; 399 dma-names = "tx", "rx"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&uart1_xfer>; 402 reg-io-width = <4>; 403 reg-shift = <2>; 404 status = "disabled"; 405 }; 406 407 uart2: serial@20068000 { 408 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 409 reg = <0x20068000 0x100>; 410 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 411 clock-frequency = <24000000>; 412 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 413 clock-names = "baudclk", "apb_pclk"; 414 dmas = <&pdma 6>, <&pdma 7>; 415 dma-names = "tx", "rx"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&uart2_xfer>; 418 reg-io-width = <4>; 419 reg-shift = <2>; 420 status = "disabled"; 421 }; 422 423 saradc: saradc@2006c000 { 424 compatible = "rockchip,saradc"; 425 reg = <0x2006c000 0x100>; 426 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 428 clock-names = "saradc", "apb_pclk"; 429 resets = <&cru SRST_SARADC>; 430 reset-names = "saradc-apb"; 431 #io-channel-cells = <1>; 432 status = "disabled"; 433 }; 434 435 i2c0: i2c@20072000 { 436 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 437 reg = <20072000 0x1000>; 438 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 439 clock-names = "i2c"; 440 clocks = <&cru PCLK_I2C0>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&i2c0_xfer>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 spi0: spi@20074000 { 449 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 450 reg = <0x20074000 0x1000>; 451 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 453 clock-names = "spiclk", "apb_pclk"; 454 dmas = <&pdma 8>, <&pdma 9>; 455 dma-names = "tx", "rx"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 463 pdma: dma-controller@20078000 { 464 compatible = "arm,pl330", "arm,primecell"; 465 reg = <0x20078000 0x4000>; 466 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 468 arm,pl330-broken-no-flushp; 469 clocks = <&cru ACLK_DMAC>; 470 clock-names = "apb_pclk"; 471 #dma-cells = <1>; 472 }; 473 474 pinctrl: pinctrl { 475 compatible = "rockchip,rk3128-pinctrl"; 476 rockchip,grf = <&grf>; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 ranges; 480 481 gpio0: gpio@2007c000 { 482 compatible = "rockchip,gpio-bank"; 483 reg = <0x2007c000 0x100>; 484 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cru PCLK_GPIO0>; 486 gpio-controller; 487 #gpio-cells = <2>; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 }; 491 492 gpio1: gpio@20080000 { 493 compatible = "rockchip,gpio-bank"; 494 reg = <0x20080000 0x100>; 495 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&cru PCLK_GPIO1>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 }; 502 503 gpio2: gpio@20084000 { 504 compatible = "rockchip,gpio-bank"; 505 reg = <0x20084000 0x100>; 506 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cru PCLK_GPIO2>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 }; 513 514 gpio3: gpio@20088000 { 515 compatible = "rockchip,gpio-bank"; 516 reg = <0x20088000 0x100>; 517 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cru PCLK_GPIO3>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 }; 524 525 pcfg_pull_default: pcfg-pull-default { 526 bias-pull-pin-default; 527 }; 528 529 pcfg_pull_none: pcfg-pull-none { 530 bias-disable; 531 }; 532 533 emmc { 534 emmc_clk: emmc-clk { 535 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 536 }; 537 538 emmc_cmd: emmc-cmd { 539 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 540 }; 541 542 emmc_cmd1: emmc-cmd1 { 543 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 544 }; 545 546 emmc_pwr: emmc-pwr { 547 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 548 }; 549 550 emmc_bus1: emmc-bus1 { 551 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 552 }; 553 554 emmc_bus4: emmc-bus4 { 555 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 556 <1 RK_PD1 2 &pcfg_pull_default>, 557 <1 RK_PD2 2 &pcfg_pull_default>, 558 <1 RK_PD3 2 &pcfg_pull_default>; 559 }; 560 561 emmc_bus8: emmc-bus8 { 562 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 563 <1 RK_PD1 2 &pcfg_pull_default>, 564 <1 RK_PD2 2 &pcfg_pull_default>, 565 <1 RK_PD3 2 &pcfg_pull_default>, 566 <1 RK_PD4 2 &pcfg_pull_default>, 567 <1 RK_PD5 2 &pcfg_pull_default>, 568 <1 RK_PD6 2 &pcfg_pull_default>, 569 <1 RK_PD7 2 &pcfg_pull_default>; 570 }; 571 }; 572 573 gmac { 574 rgmii_pins: rgmii-pins { 575 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 576 <2 RK_PB1 3 &pcfg_pull_default>, 577 <2 RK_PB3 3 &pcfg_pull_default>, 578 <2 RK_PB4 3 &pcfg_pull_default>, 579 <2 RK_PB5 3 &pcfg_pull_default>, 580 <2 RK_PB6 3 &pcfg_pull_default>, 581 <2 RK_PC0 3 &pcfg_pull_default>, 582 <2 RK_PC1 3 &pcfg_pull_default>, 583 <2 RK_PC2 3 &pcfg_pull_default>, 584 <2 RK_PC3 3 &pcfg_pull_default>, 585 <2 RK_PD1 3 &pcfg_pull_default>, 586 <2 RK_PC4 4 &pcfg_pull_default>, 587 <2 RK_PC5 4 &pcfg_pull_default>, 588 <2 RK_PC6 4 &pcfg_pull_default>, 589 <2 RK_PC7 4 &pcfg_pull_default>; 590 }; 591 592 rmii_pins: rmii-pins { 593 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 594 <2 RK_PB4 3 &pcfg_pull_default>, 595 <2 RK_PB5 3 &pcfg_pull_default>, 596 <2 RK_PB6 3 &pcfg_pull_default>, 597 <2 RK_PB7 3 &pcfg_pull_default>, 598 <2 RK_PC0 3 &pcfg_pull_default>, 599 <2 RK_PC1 3 &pcfg_pull_default>, 600 <2 RK_PC2 3 &pcfg_pull_default>, 601 <2 RK_PC3 3 &pcfg_pull_default>, 602 <2 RK_PD1 3 &pcfg_pull_default>; 603 }; 604 }; 605 606 hdmi { 607 hdmii2c_xfer: hdmii2c-xfer { 608 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 609 <0 RK_PA7 2 &pcfg_pull_none>; 610 }; 611 612 hdmi_hpd: hdmi-hpd { 613 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 614 }; 615 616 hdmi_cec: hdmi-cec { 617 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 618 }; 619 }; 620 621 i2c0 { 622 i2c0_xfer: i2c0-xfer { 623 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 624 <0 RK_PA1 1 &pcfg_pull_none>; 625 }; 626 }; 627 628 i2c1 { 629 i2c1_xfer: i2c1-xfer { 630 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 631 <0 RK_PA3 1 &pcfg_pull_none>; 632 }; 633 }; 634 635 i2c2 { 636 i2c2_xfer: i2c2-xfer { 637 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 638 <2 RK_PC5 3 &pcfg_pull_none>; 639 }; 640 }; 641 642 i2c3 { 643 i2c3_xfer: i2c3-xfer { 644 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 645 <0 RK_PA7 1 &pcfg_pull_none>; 646 }; 647 }; 648 649 i2s { 650 i2s_bus: i2s-bus { 651 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 652 <0 RK_PB1 1 &pcfg_pull_none>, 653 <0 RK_PB3 1 &pcfg_pull_none>, 654 <0 RK_PB4 1 &pcfg_pull_none>, 655 <0 RK_PB5 1 &pcfg_pull_none>, 656 <0 RK_PB6 1 &pcfg_pull_none>; 657 }; 658 659 i2s1_bus: i2s1-bus { 660 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 661 <1 RK_PA1 1 &pcfg_pull_none>, 662 <1 RK_PA2 1 &pcfg_pull_none>, 663 <1 RK_PA3 1 &pcfg_pull_none>, 664 <1 RK_PA4 1 &pcfg_pull_none>, 665 <1 RK_PA5 1 &pcfg_pull_none>; 666 }; 667 }; 668 669 lcdc { 670 lcdc_dclk: lcdc-dclk { 671 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 672 }; 673 674 lcdc_den: lcdc-den { 675 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 676 }; 677 678 lcdc_hsync: lcdc-hsync { 679 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 680 }; 681 682 lcdc_vsync: lcdc-vsync { 683 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 684 }; 685 686 lcdc_rgb24: lcdc-rgb24 { 687 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 688 <2 RK_PB5 1 &pcfg_pull_none>, 689 <2 RK_PB6 1 &pcfg_pull_none>, 690 <2 RK_PB7 1 &pcfg_pull_none>, 691 <2 RK_PC0 1 &pcfg_pull_none>, 692 <2 RK_PC1 1 &pcfg_pull_none>, 693 <2 RK_PC2 1 &pcfg_pull_none>, 694 <2 RK_PC3 1 &pcfg_pull_none>, 695 <2 RK_PC4 1 &pcfg_pull_none>, 696 <2 RK_PC5 1 &pcfg_pull_none>, 697 <2 RK_PC6 1 &pcfg_pull_none>, 698 <2 RK_PC7 1 &pcfg_pull_none>, 699 <2 RK_PD0 1 &pcfg_pull_none>, 700 <2 RK_PD1 1 &pcfg_pull_none>; 701 }; 702 }; 703 704 nfc { 705 flash_ale: flash-ale { 706 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 707 }; 708 709 flash_cle: flash-cle { 710 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 711 }; 712 713 flash_wrn: flash-wrn { 714 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 715 }; 716 717 flash_rdn: flash-rdn { 718 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 719 }; 720 721 flash_rdy: flash-rdy { 722 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 723 }; 724 725 flash_cs0: flash-cs0 { 726 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 727 }; 728 729 flash_dqs: flash-dqs { 730 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 731 }; 732 733 flash_bus8: flash-bus8 { 734 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 735 <1 RK_PD1 1 &pcfg_pull_none>, 736 <1 RK_PD2 1 &pcfg_pull_none>, 737 <1 RK_PD3 1 &pcfg_pull_none>, 738 <1 RK_PD4 1 &pcfg_pull_none>, 739 <1 RK_PD5 1 &pcfg_pull_none>, 740 <1 RK_PD6 1 &pcfg_pull_none>, 741 <1 RK_PD7 1 &pcfg_pull_none>; 742 }; 743 }; 744 745 pwm0 { 746 pwm0_pin: pwm0-pin { 747 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 748 }; 749 }; 750 751 pwm1 { 752 pwm1_pin: pwm1-pin { 753 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 754 }; 755 }; 756 757 pwm2 { 758 pwm2_pin: pwm2-pin { 759 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 760 }; 761 }; 762 763 pwm3 { 764 pwm3_pin: pwm3-pin { 765 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 766 }; 767 }; 768 769 sdio { 770 sdio_clk: sdio-clk { 771 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 772 }; 773 774 sdio_cmd: sdio-cmd { 775 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 776 }; 777 778 sdio_pwren: sdio-pwren { 779 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 780 }; 781 782 sdio_bus4: sdio-bus4 { 783 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 784 <1 RK_PA2 2 &pcfg_pull_default>, 785 <1 RK_PA4 2 &pcfg_pull_default>, 786 <1 RK_PA5 2 &pcfg_pull_default>; 787 }; 788 }; 789 790 sdmmc { 791 sdmmc_clk: sdmmc-clk { 792 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 793 }; 794 795 sdmmc_cmd: sdmmc-cmd { 796 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 797 }; 798 799 sdmmc_wp: sdmmc-wp { 800 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 801 }; 802 803 sdmmc_pwren: sdmmc-pwren { 804 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 805 }; 806 807 sdmmc_bus4: sdmmc-bus4 { 808 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 809 <1 RK_PC3 1 &pcfg_pull_default>, 810 <1 RK_PC4 1 &pcfg_pull_default>, 811 <1 RK_PC5 1 &pcfg_pull_default>; 812 }; 813 }; 814 815 spdif { 816 spdif_tx: spdif-tx { 817 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 818 }; 819 }; 820 821 spi0 { 822 spi0_clk: spi0-clk { 823 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 824 }; 825 826 spi0_cs0: spi0-cs0 { 827 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 828 }; 829 830 spi0_tx: spi0-tx { 831 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 832 }; 833 834 spi0_rx: spi0-rx { 835 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 836 }; 837 838 spi0_cs1: spi0-cs1 { 839 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 840 }; 841 842 spi1_clk: spi1-clk { 843 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 844 }; 845 846 spi1_cs0: spi1-cs0 { 847 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 848 }; 849 850 spi1_tx: spi1-tx { 851 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 852 }; 853 854 spi1_rx: spi1-rx { 855 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 856 }; 857 858 spi1_cs1: spi1-cs1 { 859 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 860 }; 861 862 spi2_clk: spi2-clk { 863 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 864 }; 865 866 spi2_cs0: spi2-cs0 { 867 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 868 }; 869 870 spi2_tx: spi2-tx { 871 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 872 }; 873 874 spi2_rx: spi2-rx { 875 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 876 }; 877 }; 878 879 uart0 { 880 uart0_xfer: uart0-xfer { 881 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 882 <2 RK_PD3 2 &pcfg_pull_none>; 883 }; 884 885 uart0_cts: uart0-cts { 886 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 887 }; 888 889 uart0_rts: uart0-rts { 890 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 891 }; 892 }; 893 894 uart1 { 895 uart1_xfer: uart1-xfer { 896 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 897 <1 RK_PB2 2 &pcfg_pull_default>; 898 }; 899 900 uart1_cts: uart1-cts { 901 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 902 }; 903 904 uart1_rts: uart1-rts { 905 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 906 }; 907 }; 908 909 uart2 { 910 uart2_xfer: uart2-xfer { 911 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 912 <1 RK_PC3 2 &pcfg_pull_none>; 913 }; 914 915 uart2_cts: uart2-cts { 916 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 917 }; 918 919 uart2_rts: uart2-rts { 920 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 921 }; 922 }; 923 }; 924}; 925