1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 enable-method = "rockchip,rk3036-smp"; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 resets = <&cru SRST_CORE0>; 39 operating-points-v2 = <&cpu_opp_table>; 40 #cooling-cells = <2>; /* min followed by max */ 41 }; 42 43 cpu1: cpu@f01 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0xf01>; 47 resets = <&cru SRST_CORE1>; 48 operating-points-v2 = <&cpu_opp_table>; 49 }; 50 51 cpu2: cpu@f02 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf02>; 55 resets = <&cru SRST_CORE2>; 56 operating-points-v2 = <&cpu_opp_table>; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 operating-points-v2 = <&cpu_opp_table>; 65 }; 66 }; 67 68 cpu_opp_table: opp-table-0 { 69 compatible = "operating-points-v2"; 70 opp-shared; 71 72 opp-216000000 { 73 opp-hz = /bits/ 64 <216000000>; 74 opp-microvolt = <950000 950000 1325000>; 75 }; 76 opp-408000000 { 77 opp-hz = /bits/ 64 <408000000>; 78 opp-microvolt = <950000 950000 1325000>; 79 }; 80 opp-600000000 { 81 opp-hz = /bits/ 64 <600000000>; 82 opp-microvolt = <950000 950000 1325000>; 83 }; 84 opp-696000000 { 85 opp-hz = /bits/ 64 <696000000>; 86 opp-microvolt = <975000 975000 1325000>; 87 }; 88 opp-816000000 { 89 opp-hz = /bits/ 64 <816000000>; 90 opp-microvolt = <1075000 1075000 1325000>; 91 opp-suspend; 92 }; 93 opp-1008000000 { 94 opp-hz = /bits/ 64 <1008000000>; 95 opp-microvolt = <1200000 1200000 1325000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <1325000 1325000 1325000>; 100 }; 101 }; 102 103 timer { 104 compatible = "arm,armv7-timer"; 105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 arm,cpu-registers-not-fw-configured; 110 clock-frequency = <24000000>; 111 }; 112 113 xin24m: oscillator { 114 compatible = "fixed-clock"; 115 clock-frequency = <24000000>; 116 clock-output-names = "xin24m"; 117 #clock-cells = <0>; 118 }; 119 120 imem: sram@10080000 { 121 compatible = "mmio-sram"; 122 reg = <0x10080000 0x2000>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0x10080000 0x2000>; 126 127 smp-sram@0 { 128 compatible = "rockchip,rk3066-smp-sram"; 129 reg = <0x00 0x10>; 130 }; 131 }; 132 133 pmu: syscon@100a0000 { 134 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 135 reg = <0x100a0000 0x1000>; 136 }; 137 138 gic: interrupt-controller@10139000 { 139 compatible = "arm,cortex-a7-gic"; 140 reg = <0x10139000 0x1000>, 141 <0x1013a000 0x1000>, 142 <0x1013c000 0x2000>, 143 <0x1013e000 0x2000>; 144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 #address-cells = <0>; 148 }; 149 150 usb_otg: usb@10180000 { 151 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 152 reg = <0x10180000 0x40000>; 153 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&cru HCLK_OTG>; 155 clock-names = "otg"; 156 dr_mode = "otg"; 157 phys = <&usb2phy_otg>; 158 phy-names = "usb2-phy"; 159 status = "disabled"; 160 }; 161 162 usb_host_ehci: usb@101c0000 { 163 compatible = "generic-ehci"; 164 reg = <0x101c0000 0x20000>; 165 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&cru HCLK_HOST2>; 167 phys = <&usb2phy_host>; 168 phy-names = "usb"; 169 status = "disabled"; 170 }; 171 172 usb_host_ohci: usb@101e0000 { 173 compatible = "generic-ohci"; 174 reg = <0x101e0000 0x20000>; 175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&cru HCLK_HOST2>; 177 phys = <&usb2phy_host>; 178 phy-names = "usb"; 179 status = "disabled"; 180 }; 181 182 sdmmc: mmc@10214000 { 183 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 184 reg = <0x10214000 0x4000>; 185 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 187 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 188 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 189 dmas = <&pdma 10>; 190 dma-names = "rx-tx"; 191 fifo-depth = <256>; 192 max-frequency = <150000000>; 193 resets = <&cru SRST_SDMMC>; 194 reset-names = "reset"; 195 status = "disabled"; 196 }; 197 198 sdio: mmc@10218000 { 199 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 200 reg = <0x10218000 0x4000>; 201 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 203 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 204 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 205 dmas = <&pdma 11>; 206 dma-names = "rx-tx"; 207 fifo-depth = <256>; 208 max-frequency = <150000000>; 209 resets = <&cru SRST_SDIO>; 210 reset-names = "reset"; 211 status = "disabled"; 212 }; 213 214 emmc: mmc@1021c000 { 215 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 216 reg = <0x1021c000 0x4000>; 217 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 219 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 220 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 221 dmas = <&pdma 12>; 222 dma-names = "rx-tx"; 223 fifo-depth = <256>; 224 max-frequency = <150000000>; 225 resets = <&cru SRST_EMMC>; 226 reset-names = "reset"; 227 status = "disabled"; 228 }; 229 230 nfc: nand-controller@10500000 { 231 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 232 reg = <0x10500000 0x4000>; 233 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 235 clock-names = "ahb", "nfc"; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 238 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 239 status = "disabled"; 240 }; 241 242 cru: clock-controller@20000000 { 243 compatible = "rockchip,rk3128-cru"; 244 reg = <0x20000000 0x1000>; 245 clocks = <&xin24m>; 246 clock-names = "xin24m"; 247 rockchip,grf = <&grf>; 248 #clock-cells = <1>; 249 #reset-cells = <1>; 250 assigned-clocks = <&cru PLL_GPLL>; 251 assigned-clock-rates = <594000000>; 252 }; 253 254 grf: syscon@20008000 { 255 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 256 reg = <0x20008000 0x1000>; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 260 usb2phy: usb2phy@17c { 261 compatible = "rockchip,rk3128-usb2phy"; 262 reg = <0x017c 0x0c>; 263 clocks = <&cru SCLK_OTGPHY0>; 264 clock-names = "phyclk"; 265 clock-output-names = "usb480m_phy"; 266 #clock-cells = <0>; 267 status = "disabled"; 268 269 usb2phy_host: host-port { 270 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-names = "linestate"; 272 #phy-cells = <0>; 273 status = "disabled"; 274 }; 275 276 usb2phy_otg: otg-port { 277 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 280 interrupt-names = "otg-bvalid", "otg-id", 281 "linestate"; 282 #phy-cells = <0>; 283 status = "disabled"; 284 }; 285 }; 286 }; 287 288 timer0: timer@20044000 { 289 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 290 reg = <0x20044000 0x20>; 291 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 293 clock-names = "pclk", "timer"; 294 }; 295 296 timer1: timer@20044020 { 297 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 298 reg = <0x20044020 0x20>; 299 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 301 clock-names = "pclk", "timer"; 302 }; 303 304 timer2: timer@20044040 { 305 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 306 reg = <0x20044040 0x20>; 307 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 309 clock-names = "pclk", "timer"; 310 }; 311 312 timer3: timer@20044060 { 313 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 314 reg = <0x20044060 0x20>; 315 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 317 clock-names = "pclk", "timer"; 318 }; 319 320 timer4: timer@20044080 { 321 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 322 reg = <0x20044080 0x20>; 323 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 325 clock-names = "pclk", "timer"; 326 }; 327 328 timer5: timer@200440a0 { 329 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 330 reg = <0x200440a0 0x20>; 331 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 333 clock-names = "pclk", "timer"; 334 }; 335 336 watchdog: watchdog@2004c000 { 337 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 338 reg = <0x2004c000 0x100>; 339 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cru PCLK_WDT>; 341 status = "disabled"; 342 }; 343 344 pwm0: pwm@20050000 { 345 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 346 reg = <0x20050000 0x10>; 347 clocks = <&cru PCLK_PWM>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pwm0_pin>; 350 #pwm-cells = <3>; 351 status = "disabled"; 352 }; 353 354 pwm1: pwm@20050010 { 355 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 356 reg = <0x20050010 0x10>; 357 clocks = <&cru PCLK_PWM>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pwm1_pin>; 360 #pwm-cells = <3>; 361 status = "disabled"; 362 }; 363 364 pwm2: pwm@20050020 { 365 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 366 reg = <0x20050020 0x10>; 367 clocks = <&cru PCLK_PWM>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pwm2_pin>; 370 #pwm-cells = <3>; 371 status = "disabled"; 372 }; 373 374 pwm3: pwm@20050030 { 375 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 376 reg = <0x20050030 0x10>; 377 clocks = <&cru PCLK_PWM>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pwm3_pin>; 380 #pwm-cells = <3>; 381 status = "disabled"; 382 }; 383 384 i2c1: i2c@20056000 { 385 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 386 reg = <0x20056000 0x1000>; 387 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 388 clock-names = "i2c"; 389 clocks = <&cru PCLK_I2C1>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&i2c1_xfer>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 i2c2: i2c@2005a000 { 398 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 399 reg = <0x2005a000 0x1000>; 400 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 401 clock-names = "i2c"; 402 clocks = <&cru PCLK_I2C2>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&i2c2_xfer>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 i2c3: i2c@2005e000 { 411 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 412 reg = <0x2005e000 0x1000>; 413 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 414 clock-names = "i2c"; 415 clocks = <&cru PCLK_I2C3>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&i2c3_xfer>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 }; 422 423 uart0: serial@20060000 { 424 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 425 reg = <0x20060000 0x100>; 426 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 427 clock-frequency = <24000000>; 428 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 429 clock-names = "baudclk", "apb_pclk"; 430 dmas = <&pdma 2>, <&pdma 3>; 431 dma-names = "tx", "rx"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 434 reg-io-width = <4>; 435 reg-shift = <2>; 436 status = "disabled"; 437 }; 438 439 uart1: serial@20064000 { 440 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 441 reg = <0x20064000 0x100>; 442 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 443 clock-frequency = <24000000>; 444 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 445 clock-names = "baudclk", "apb_pclk"; 446 dmas = <&pdma 4>, <&pdma 5>; 447 dma-names = "tx", "rx"; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&uart1_xfer>; 450 reg-io-width = <4>; 451 reg-shift = <2>; 452 status = "disabled"; 453 }; 454 455 uart2: serial@20068000 { 456 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 457 reg = <0x20068000 0x100>; 458 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 459 clock-frequency = <24000000>; 460 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 461 clock-names = "baudclk", "apb_pclk"; 462 dmas = <&pdma 6>, <&pdma 7>; 463 dma-names = "tx", "rx"; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&uart2_xfer>; 466 reg-io-width = <4>; 467 reg-shift = <2>; 468 status = "disabled"; 469 }; 470 471 saradc: saradc@2006c000 { 472 compatible = "rockchip,saradc"; 473 reg = <0x2006c000 0x100>; 474 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 476 clock-names = "saradc", "apb_pclk"; 477 resets = <&cru SRST_SARADC>; 478 reset-names = "saradc-apb"; 479 #io-channel-cells = <1>; 480 status = "disabled"; 481 }; 482 483 i2c0: i2c@20072000 { 484 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 485 reg = <0x20072000 0x1000>; 486 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 487 clock-names = "i2c"; 488 clocks = <&cru PCLK_I2C0>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&i2c0_xfer>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 496 spi0: spi@20074000 { 497 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 498 reg = <0x20074000 0x1000>; 499 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 501 clock-names = "spiclk", "apb_pclk"; 502 dmas = <&pdma 8>, <&pdma 9>; 503 dma-names = "tx", "rx"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 pdma: dma-controller@20078000 { 512 compatible = "arm,pl330", "arm,primecell"; 513 reg = <0x20078000 0x4000>; 514 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 516 arm,pl330-broken-no-flushp; 517 arm,pl330-periph-burst; 518 clocks = <&cru ACLK_DMAC>; 519 clock-names = "apb_pclk"; 520 #dma-cells = <1>; 521 }; 522 523 pinctrl: pinctrl { 524 compatible = "rockchip,rk3128-pinctrl"; 525 rockchip,grf = <&grf>; 526 #address-cells = <1>; 527 #size-cells = <1>; 528 ranges; 529 530 gpio0: gpio@2007c000 { 531 compatible = "rockchip,gpio-bank"; 532 reg = <0x2007c000 0x100>; 533 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cru PCLK_GPIO0>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 }; 540 541 gpio1: gpio@20080000 { 542 compatible = "rockchip,gpio-bank"; 543 reg = <0x20080000 0x100>; 544 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&cru PCLK_GPIO1>; 546 gpio-controller; 547 #gpio-cells = <2>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 552 gpio2: gpio@20084000 { 553 compatible = "rockchip,gpio-bank"; 554 reg = <0x20084000 0x100>; 555 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cru PCLK_GPIO2>; 557 gpio-controller; 558 #gpio-cells = <2>; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 }; 562 563 gpio3: gpio@20088000 { 564 compatible = "rockchip,gpio-bank"; 565 reg = <0x20088000 0x100>; 566 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&cru PCLK_GPIO3>; 568 gpio-controller; 569 #gpio-cells = <2>; 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 }; 573 574 pcfg_pull_default: pcfg-pull-default { 575 bias-pull-pin-default; 576 }; 577 578 pcfg_pull_none: pcfg-pull-none { 579 bias-disable; 580 }; 581 582 emmc { 583 emmc_clk: emmc-clk { 584 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 585 }; 586 587 emmc_cmd: emmc-cmd { 588 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 589 }; 590 591 emmc_cmd1: emmc-cmd1 { 592 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 593 }; 594 595 emmc_pwr: emmc-pwr { 596 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 597 }; 598 599 emmc_bus1: emmc-bus1 { 600 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 601 }; 602 603 emmc_bus4: emmc-bus4 { 604 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 605 <1 RK_PD1 2 &pcfg_pull_default>, 606 <1 RK_PD2 2 &pcfg_pull_default>, 607 <1 RK_PD3 2 &pcfg_pull_default>; 608 }; 609 610 emmc_bus8: emmc-bus8 { 611 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 612 <1 RK_PD1 2 &pcfg_pull_default>, 613 <1 RK_PD2 2 &pcfg_pull_default>, 614 <1 RK_PD3 2 &pcfg_pull_default>, 615 <1 RK_PD4 2 &pcfg_pull_default>, 616 <1 RK_PD5 2 &pcfg_pull_default>, 617 <1 RK_PD6 2 &pcfg_pull_default>, 618 <1 RK_PD7 2 &pcfg_pull_default>; 619 }; 620 }; 621 622 gmac { 623 rgmii_pins: rgmii-pins { 624 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 625 <2 RK_PB1 3 &pcfg_pull_default>, 626 <2 RK_PB3 3 &pcfg_pull_default>, 627 <2 RK_PB4 3 &pcfg_pull_default>, 628 <2 RK_PB5 3 &pcfg_pull_default>, 629 <2 RK_PB6 3 &pcfg_pull_default>, 630 <2 RK_PC0 3 &pcfg_pull_default>, 631 <2 RK_PC1 3 &pcfg_pull_default>, 632 <2 RK_PC2 3 &pcfg_pull_default>, 633 <2 RK_PC3 3 &pcfg_pull_default>, 634 <2 RK_PD1 3 &pcfg_pull_default>, 635 <2 RK_PC4 4 &pcfg_pull_default>, 636 <2 RK_PC5 4 &pcfg_pull_default>, 637 <2 RK_PC6 4 &pcfg_pull_default>, 638 <2 RK_PC7 4 &pcfg_pull_default>; 639 }; 640 641 rmii_pins: rmii-pins { 642 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 643 <2 RK_PB4 3 &pcfg_pull_default>, 644 <2 RK_PB5 3 &pcfg_pull_default>, 645 <2 RK_PB6 3 &pcfg_pull_default>, 646 <2 RK_PB7 3 &pcfg_pull_default>, 647 <2 RK_PC0 3 &pcfg_pull_default>, 648 <2 RK_PC1 3 &pcfg_pull_default>, 649 <2 RK_PC2 3 &pcfg_pull_default>, 650 <2 RK_PC3 3 &pcfg_pull_default>, 651 <2 RK_PD1 3 &pcfg_pull_default>; 652 }; 653 }; 654 655 hdmi { 656 hdmii2c_xfer: hdmii2c-xfer { 657 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 658 <0 RK_PA7 2 &pcfg_pull_none>; 659 }; 660 661 hdmi_hpd: hdmi-hpd { 662 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 663 }; 664 665 hdmi_cec: hdmi-cec { 666 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 667 }; 668 }; 669 670 i2c0 { 671 i2c0_xfer: i2c0-xfer { 672 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 673 <0 RK_PA1 1 &pcfg_pull_none>; 674 }; 675 }; 676 677 i2c1 { 678 i2c1_xfer: i2c1-xfer { 679 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 680 <0 RK_PA3 1 &pcfg_pull_none>; 681 }; 682 }; 683 684 i2c2 { 685 i2c2_xfer: i2c2-xfer { 686 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 687 <2 RK_PC5 3 &pcfg_pull_none>; 688 }; 689 }; 690 691 i2c3 { 692 i2c3_xfer: i2c3-xfer { 693 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 694 <0 RK_PA7 1 &pcfg_pull_none>; 695 }; 696 }; 697 698 i2s { 699 i2s_bus: i2s-bus { 700 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 701 <0 RK_PB1 1 &pcfg_pull_none>, 702 <0 RK_PB3 1 &pcfg_pull_none>, 703 <0 RK_PB4 1 &pcfg_pull_none>, 704 <0 RK_PB5 1 &pcfg_pull_none>, 705 <0 RK_PB6 1 &pcfg_pull_none>; 706 }; 707 708 i2s1_bus: i2s1-bus { 709 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 710 <1 RK_PA1 1 &pcfg_pull_none>, 711 <1 RK_PA2 1 &pcfg_pull_none>, 712 <1 RK_PA3 1 &pcfg_pull_none>, 713 <1 RK_PA4 1 &pcfg_pull_none>, 714 <1 RK_PA5 1 &pcfg_pull_none>; 715 }; 716 }; 717 718 lcdc { 719 lcdc_dclk: lcdc-dclk { 720 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 721 }; 722 723 lcdc_den: lcdc-den { 724 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 725 }; 726 727 lcdc_hsync: lcdc-hsync { 728 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 729 }; 730 731 lcdc_vsync: lcdc-vsync { 732 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 733 }; 734 735 lcdc_rgb24: lcdc-rgb24 { 736 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 737 <2 RK_PB5 1 &pcfg_pull_none>, 738 <2 RK_PB6 1 &pcfg_pull_none>, 739 <2 RK_PB7 1 &pcfg_pull_none>, 740 <2 RK_PC0 1 &pcfg_pull_none>, 741 <2 RK_PC1 1 &pcfg_pull_none>, 742 <2 RK_PC2 1 &pcfg_pull_none>, 743 <2 RK_PC3 1 &pcfg_pull_none>, 744 <2 RK_PC4 1 &pcfg_pull_none>, 745 <2 RK_PC5 1 &pcfg_pull_none>, 746 <2 RK_PC6 1 &pcfg_pull_none>, 747 <2 RK_PC7 1 &pcfg_pull_none>, 748 <2 RK_PD0 1 &pcfg_pull_none>, 749 <2 RK_PD1 1 &pcfg_pull_none>; 750 }; 751 }; 752 753 nfc { 754 flash_ale: flash-ale { 755 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 756 }; 757 758 flash_cle: flash-cle { 759 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 760 }; 761 762 flash_wrn: flash-wrn { 763 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 764 }; 765 766 flash_rdn: flash-rdn { 767 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 768 }; 769 770 flash_rdy: flash-rdy { 771 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 772 }; 773 774 flash_cs0: flash-cs0 { 775 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 776 }; 777 778 flash_dqs: flash-dqs { 779 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 780 }; 781 782 flash_bus8: flash-bus8 { 783 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 784 <1 RK_PD1 1 &pcfg_pull_none>, 785 <1 RK_PD2 1 &pcfg_pull_none>, 786 <1 RK_PD3 1 &pcfg_pull_none>, 787 <1 RK_PD4 1 &pcfg_pull_none>, 788 <1 RK_PD5 1 &pcfg_pull_none>, 789 <1 RK_PD6 1 &pcfg_pull_none>, 790 <1 RK_PD7 1 &pcfg_pull_none>; 791 }; 792 }; 793 794 pwm0 { 795 pwm0_pin: pwm0-pin { 796 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 797 }; 798 }; 799 800 pwm1 { 801 pwm1_pin: pwm1-pin { 802 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 803 }; 804 }; 805 806 pwm2 { 807 pwm2_pin: pwm2-pin { 808 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 809 }; 810 }; 811 812 pwm3 { 813 pwm3_pin: pwm3-pin { 814 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 815 }; 816 }; 817 818 sdio { 819 sdio_clk: sdio-clk { 820 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 821 }; 822 823 sdio_cmd: sdio-cmd { 824 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 825 }; 826 827 sdio_pwren: sdio-pwren { 828 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 829 }; 830 831 sdio_bus4: sdio-bus4 { 832 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 833 <1 RK_PA2 2 &pcfg_pull_default>, 834 <1 RK_PA4 2 &pcfg_pull_default>, 835 <1 RK_PA5 2 &pcfg_pull_default>; 836 }; 837 }; 838 839 sdmmc { 840 sdmmc_clk: sdmmc-clk { 841 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 842 }; 843 844 sdmmc_cmd: sdmmc-cmd { 845 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 846 }; 847 848 sdmmc_det: sdmmc-det { 849 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 850 }; 851 852 sdmmc_wp: sdmmc-wp { 853 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 854 }; 855 856 sdmmc_pwren: sdmmc-pwren { 857 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 858 }; 859 860 sdmmc_bus4: sdmmc-bus4 { 861 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 862 <1 RK_PC3 1 &pcfg_pull_default>, 863 <1 RK_PC4 1 &pcfg_pull_default>, 864 <1 RK_PC5 1 &pcfg_pull_default>; 865 }; 866 }; 867 868 spdif { 869 spdif_tx: spdif-tx { 870 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 871 }; 872 }; 873 874 spi0 { 875 spi0_clk: spi0-clk { 876 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 877 }; 878 879 spi0_cs0: spi0-cs0 { 880 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 881 }; 882 883 spi0_tx: spi0-tx { 884 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 885 }; 886 887 spi0_rx: spi0-rx { 888 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 889 }; 890 891 spi0_cs1: spi0-cs1 { 892 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 893 }; 894 895 spi1_clk: spi1-clk { 896 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 897 }; 898 899 spi1_cs0: spi1-cs0 { 900 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 901 }; 902 903 spi1_tx: spi1-tx { 904 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 905 }; 906 907 spi1_rx: spi1-rx { 908 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 909 }; 910 911 spi1_cs1: spi1-cs1 { 912 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 913 }; 914 915 spi2_clk: spi2-clk { 916 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 917 }; 918 919 spi2_cs0: spi2-cs0 { 920 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 921 }; 922 923 spi2_tx: spi2-tx { 924 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 925 }; 926 927 spi2_rx: spi2-rx { 928 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 929 }; 930 }; 931 932 uart0 { 933 uart0_xfer: uart0-xfer { 934 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 935 <2 RK_PD3 2 &pcfg_pull_none>; 936 }; 937 938 uart0_cts: uart0-cts { 939 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 940 }; 941 942 uart0_rts: uart0-rts { 943 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 944 }; 945 }; 946 947 uart1 { 948 uart1_xfer: uart1-xfer { 949 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 950 <1 RK_PB2 2 &pcfg_pull_default>; 951 }; 952 953 uart1_cts: uart1-cts { 954 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 955 }; 956 957 uart1_rts: uart1-rts { 958 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 959 }; 960 }; 961 962 uart2 { 963 uart2_xfer: uart2-xfer { 964 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 965 <1 RK_PC3 2 &pcfg_pull_none>; 966 }; 967 968 uart2_cts: uart2-cts { 969 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 970 }; 971 972 uart2_rts: uart2-rts { 973 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 974 }; 975 }; 976 }; 977}; 978