1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 }; 32 33 arm-pmu { 34 compatible = "arm,cortex-a7-pmu"; 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "rockchip,rk3036-smp"; 46 47 cpu0: cpu@f00 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a7"; 50 reg = <0xf00>; 51 clock-latency = <40000>; 52 clocks = <&cru ARMCLK>; 53 resets = <&cru SRST_CORE0>; 54 operating-points-v2 = <&cpu_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu1: cpu@f01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf01>; 62 resets = <&cru SRST_CORE1>; 63 operating-points-v2 = <&cpu_opp_table>; 64 }; 65 66 cpu2: cpu@f02 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a7"; 69 reg = <0xf02>; 70 resets = <&cru SRST_CORE2>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 cpu3: cpu@f03 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 reg = <0xf03>; 78 resets = <&cru SRST_CORE3>; 79 operating-points-v2 = <&cpu_opp_table>; 80 }; 81 }; 82 83 cpu_opp_table: opp-table-0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-216000000 { 88 opp-hz = /bits/ 64 <216000000>; 89 opp-microvolt = <950000 950000 1325000>; 90 }; 91 opp-408000000 { 92 opp-hz = /bits/ 64 <408000000>; 93 opp-microvolt = <950000 950000 1325000>; 94 }; 95 opp-600000000 { 96 opp-hz = /bits/ 64 <600000000>; 97 opp-microvolt = <950000 950000 1325000>; 98 }; 99 opp-696000000 { 100 opp-hz = /bits/ 64 <696000000>; 101 opp-microvolt = <975000 975000 1325000>; 102 }; 103 opp-816000000 { 104 opp-hz = /bits/ 64 <816000000>; 105 opp-microvolt = <1075000 1075000 1325000>; 106 opp-suspend; 107 }; 108 opp-1008000000 { 109 opp-hz = /bits/ 64 <1008000000>; 110 opp-microvolt = <1200000 1200000 1325000>; 111 }; 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <1325000 1325000 1325000>; 115 }; 116 }; 117 118 display_subsystem: display-subsystem { 119 compatible = "rockchip,display-subsystem"; 120 ports = <&vop_out>; 121 status = "disabled"; 122 }; 123 124 gpu_opp_table: opp-table-1 { 125 compatible = "operating-points-v2"; 126 127 opp-200000000 { 128 opp-hz = /bits/ 64 <200000000>; 129 opp-microvolt = <975000 975000 1250000>; 130 }; 131 opp-300000000 { 132 opp-hz = /bits/ 64 <300000000>; 133 opp-microvolt = <1050000 1050000 1250000>; 134 }; 135 opp-400000000 { 136 opp-hz = /bits/ 64 <400000000>; 137 opp-microvolt = <1150000 1150000 1250000>; 138 }; 139 opp-480000000 { 140 opp-hz = /bits/ 64 <480000000>; 141 opp-microvolt = <1250000 1250000 1250000>; 142 }; 143 }; 144 145 timer { 146 compatible = "arm,armv7-timer"; 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151 arm,cpu-registers-not-fw-configured; 152 clock-frequency = <24000000>; 153 }; 154 155 xin24m: oscillator { 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-output-names = "xin24m"; 159 #clock-cells = <0>; 160 }; 161 162 imem: sram@10080000 { 163 compatible = "mmio-sram"; 164 reg = <0x10080000 0x2000>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0 0x10080000 0x2000>; 168 169 smp-sram@0 { 170 compatible = "rockchip,rk3066-smp-sram"; 171 reg = <0x00 0x10>; 172 }; 173 }; 174 175 gpu: gpu@10090000 { 176 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 177 reg = <0x10090000 0x10000>; 178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "gp", 185 "gpmmu", 186 "pp0", 187 "ppmmu0", 188 "pp1", 189 "ppmmu1"; 190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 191 clock-names = "bus", "core"; 192 operating-points-v2 = <&gpu_opp_table>; 193 resets = <&cru SRST_GPU>; 194 power-domains = <&power RK3128_PD_GPU>; 195 status = "disabled"; 196 }; 197 198 pmu: syscon@100a0000 { 199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 200 reg = <0x100a0000 0x1000>; 201 202 power: power-controller { 203 compatible = "rockchip,rk3128-power-controller"; 204 #power-domain-cells = <1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 power-domain@RK3128_PD_VIO { 209 reg = <RK3128_PD_VIO>; 210 clocks = <&cru ACLK_CIF>, 211 <&cru HCLK_CIF>, 212 <&cru DCLK_EBC>, 213 <&cru HCLK_EBC>, 214 <&cru ACLK_IEP>, 215 <&cru HCLK_IEP>, 216 <&cru ACLK_LCDC0>, 217 <&cru HCLK_LCDC0>, 218 <&cru PCLK_MIPI>, 219 <&cru PCLK_MIPIPHY>, 220 <&cru SCLK_MIPI_24M>, 221 <&cru ACLK_RGA>, 222 <&cru HCLK_RGA>, 223 <&cru ACLK_VIO0>, 224 <&cru ACLK_VIO1>, 225 <&cru HCLK_VIO>, 226 <&cru HCLK_VIO_H2P>, 227 <&cru DCLK_VOP>, 228 <&cru SCLK_VOP>; 229 pm_qos = <&qos_ebc>, 230 <&qos_iep>, 231 <&qos_lcdc>, 232 <&qos_rga>, 233 <&qos_vip>; 234 #power-domain-cells = <0>; 235 }; 236 237 power-domain@RK3128_PD_VIDEO { 238 reg = <RK3128_PD_VIDEO>; 239 clocks = <&cru ACLK_VDPU>, 240 <&cru HCLK_VDPU>, 241 <&cru ACLK_VEPU>, 242 <&cru HCLK_VEPU>, 243 <&cru SCLK_HEVC_CORE>; 244 pm_qos = <&qos_vpu>; 245 #power-domain-cells = <0>; 246 }; 247 248 power-domain@RK3128_PD_GPU { 249 reg = <RK3128_PD_GPU>; 250 clocks = <&cru ACLK_GPU>; 251 pm_qos = <&qos_gpu>; 252 #power-domain-cells = <0>; 253 }; 254 }; 255 }; 256 257 vop: vop@1010e000 { 258 compatible = "rockchip,rk3126-vop"; 259 reg = <0x1010e000 0x300>; 260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, 262 <&cru HCLK_LCDC0>; 263 clock-names = "aclk_vop", "dclk_vop", 264 "hclk_vop"; 265 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, 266 <&cru SRST_VOP_D>; 267 reset-names = "axi", "ahb", 268 "dclk"; 269 power-domains = <&power RK3128_PD_VIO>; 270 status = "disabled"; 271 272 vop_out: port { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 vop_out_hdmi: endpoint@0 { 277 reg = <0>; 278 remote-endpoint = <&hdmi_in_vop>; 279 }; 280 }; 281 }; 282 283 qos_gpu: qos@1012d000 { 284 compatible = "rockchip,rk3128-qos", "syscon"; 285 reg = <0x1012d000 0x20>; 286 }; 287 288 qos_vpu: qos@1012e000 { 289 compatible = "rockchip,rk3128-qos", "syscon"; 290 reg = <0x1012e000 0x20>; 291 }; 292 293 qos_rga: qos@1012f000 { 294 compatible = "rockchip,rk3128-qos", "syscon"; 295 reg = <0x1012f000 0x20>; 296 }; 297 298 qos_ebc: qos@1012f080 { 299 compatible = "rockchip,rk3128-qos", "syscon"; 300 reg = <0x1012f080 0x20>; 301 }; 302 303 qos_iep: qos@1012f100 { 304 compatible = "rockchip,rk3128-qos", "syscon"; 305 reg = <0x1012f100 0x20>; 306 }; 307 308 qos_lcdc: qos@1012f180 { 309 compatible = "rockchip,rk3128-qos", "syscon"; 310 reg = <0x1012f180 0x20>; 311 }; 312 313 qos_vip: qos@1012f200 { 314 compatible = "rockchip,rk3128-qos", "syscon"; 315 reg = <0x1012f200 0x20>; 316 }; 317 318 gic: interrupt-controller@10139000 { 319 compatible = "arm,cortex-a7-gic"; 320 reg = <0x10139000 0x1000>, 321 <0x1013a000 0x1000>, 322 <0x1013c000 0x2000>, 323 <0x1013e000 0x2000>; 324 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 325 interrupt-controller; 326 #interrupt-cells = <3>; 327 #address-cells = <0>; 328 }; 329 330 usb_otg: usb@10180000 { 331 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 332 reg = <0x10180000 0x40000>; 333 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&cru HCLK_OTG>; 335 clock-names = "otg"; 336 dr_mode = "otg"; 337 g-np-tx-fifo-size = <16>; 338 g-rx-fifo-size = <280>; 339 g-tx-fifo-size = <256 128 128 64 32 16>; 340 phys = <&usb2phy_otg>; 341 phy-names = "usb2-phy"; 342 status = "disabled"; 343 }; 344 345 usb_host_ehci: usb@101c0000 { 346 compatible = "generic-ehci"; 347 reg = <0x101c0000 0x20000>; 348 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cru HCLK_HOST2>; 350 phys = <&usb2phy_host>; 351 phy-names = "usb"; 352 status = "disabled"; 353 }; 354 355 usb_host_ohci: usb@101e0000 { 356 compatible = "generic-ohci"; 357 reg = <0x101e0000 0x20000>; 358 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&cru HCLK_HOST2>; 360 phys = <&usb2phy_host>; 361 phy-names = "usb"; 362 status = "disabled"; 363 }; 364 365 sdmmc: mmc@10214000 { 366 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 367 reg = <0x10214000 0x4000>; 368 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 370 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 371 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 372 dmas = <&pdma 10>; 373 dma-names = "rx-tx"; 374 fifo-depth = <256>; 375 max-frequency = <150000000>; 376 resets = <&cru SRST_SDMMC>; 377 reset-names = "reset"; 378 status = "disabled"; 379 }; 380 381 sdio: mmc@10218000 { 382 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 383 reg = <0x10218000 0x4000>; 384 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 386 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 387 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 388 dmas = <&pdma 11>; 389 dma-names = "rx-tx"; 390 fifo-depth = <256>; 391 max-frequency = <150000000>; 392 resets = <&cru SRST_SDIO>; 393 reset-names = "reset"; 394 status = "disabled"; 395 }; 396 397 emmc: mmc@1021c000 { 398 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 399 reg = <0x1021c000 0x4000>; 400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 402 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 403 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 404 dmas = <&pdma 12>; 405 dma-names = "rx-tx"; 406 fifo-depth = <256>; 407 max-frequency = <150000000>; 408 resets = <&cru SRST_EMMC>; 409 reset-names = "reset"; 410 status = "disabled"; 411 }; 412 413 nfc: nand-controller@10500000 { 414 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 415 reg = <0x10500000 0x4000>; 416 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 418 clock-names = "ahb", "nfc"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 421 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 422 status = "disabled"; 423 }; 424 425 cru: clock-controller@20000000 { 426 compatible = "rockchip,rk3128-cru"; 427 reg = <0x20000000 0x1000>; 428 clocks = <&xin24m>; 429 clock-names = "xin24m"; 430 rockchip,grf = <&grf>; 431 #clock-cells = <1>; 432 #reset-cells = <1>; 433 assigned-clocks = <&cru PLL_GPLL>; 434 assigned-clock-rates = <594000000>; 435 }; 436 437 grf: syscon@20008000 { 438 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 439 reg = <0x20008000 0x1000>; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 443 usb2phy: usb2phy@17c { 444 compatible = "rockchip,rk3128-usb2phy"; 445 reg = <0x017c 0x0c>; 446 clocks = <&cru SCLK_OTGPHY0>; 447 clock-names = "phyclk"; 448 clock-output-names = "usb480m_phy"; 449 assigned-clocks = <&cru SCLK_USB480M>; 450 assigned-clock-parents = <&usb2phy>; 451 #clock-cells = <0>; 452 status = "disabled"; 453 454 usb2phy_host: host-port { 455 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 456 interrupt-names = "linestate"; 457 #phy-cells = <0>; 458 status = "disabled"; 459 }; 460 461 usb2phy_otg: otg-port { 462 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "otg-bvalid", "otg-id", 466 "linestate"; 467 #phy-cells = <0>; 468 status = "disabled"; 469 }; 470 }; 471 }; 472 473 hdmi: hdmi@20034000 { 474 compatible = "rockchip,rk3128-inno-hdmi"; 475 reg = <0x20034000 0x4000>; 476 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; 478 clock-names = "pclk", "ref"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 481 power-domains = <&power RK3128_PD_VIO>; 482 status = "disabled"; 483 484 ports { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 488 hdmi_in: port@0 { 489 reg = <0>; 490 hdmi_in_vop: endpoint { 491 remote-endpoint = <&vop_out_hdmi>; 492 }; 493 }; 494 495 hdmi_out: port@1 { 496 reg = <1>; 497 }; 498 }; 499 }; 500 501 dphy: phy@20038000 { 502 compatible = "rockchip,rk3128-dsi-dphy"; 503 reg = <0x20038000 0x4000>; 504 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; 505 clock-names = "ref", "pclk"; 506 #phy-cells = <0>; 507 power-domains = <&power RK3128_PD_VIO>; 508 resets = <&cru SRST_MIPIPHY_P>; 509 reset-names = "apb"; 510 status = "disabled"; 511 }; 512 513 timer0: timer@20044000 { 514 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 515 reg = <0x20044000 0x20>; 516 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 518 clock-names = "pclk", "timer"; 519 }; 520 521 timer1: timer@20044020 { 522 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 523 reg = <0x20044020 0x20>; 524 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 526 clock-names = "pclk", "timer"; 527 }; 528 529 timer2: timer@20044040 { 530 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 531 reg = <0x20044040 0x20>; 532 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 534 clock-names = "pclk", "timer"; 535 }; 536 537 timer3: timer@20044060 { 538 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 539 reg = <0x20044060 0x20>; 540 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 542 clock-names = "pclk", "timer"; 543 }; 544 545 timer4: timer@20044080 { 546 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 547 reg = <0x20044080 0x20>; 548 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 550 clock-names = "pclk", "timer"; 551 }; 552 553 timer5: timer@200440a0 { 554 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 555 reg = <0x200440a0 0x20>; 556 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 558 clock-names = "pclk", "timer"; 559 }; 560 561 watchdog: watchdog@2004c000 { 562 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 563 reg = <0x2004c000 0x100>; 564 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cru PCLK_WDT>; 566 status = "disabled"; 567 }; 568 569 pwm0: pwm@20050000 { 570 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 571 reg = <0x20050000 0x10>; 572 clocks = <&cru PCLK_PWM>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&pwm0_pin>; 575 #pwm-cells = <3>; 576 status = "disabled"; 577 }; 578 579 pwm1: pwm@20050010 { 580 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 581 reg = <0x20050010 0x10>; 582 clocks = <&cru PCLK_PWM>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&pwm1_pin>; 585 #pwm-cells = <3>; 586 status = "disabled"; 587 }; 588 589 pwm2: pwm@20050020 { 590 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 591 reg = <0x20050020 0x10>; 592 clocks = <&cru PCLK_PWM>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&pwm2_pin>; 595 #pwm-cells = <3>; 596 status = "disabled"; 597 }; 598 599 pwm3: pwm@20050030 { 600 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 601 reg = <0x20050030 0x10>; 602 clocks = <&cru PCLK_PWM>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pwm3_pin>; 605 #pwm-cells = <3>; 606 status = "disabled"; 607 }; 608 609 i2c1: i2c@20056000 { 610 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 611 reg = <0x20056000 0x1000>; 612 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 613 clock-names = "i2c"; 614 clocks = <&cru PCLK_I2C1>; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&i2c1_xfer>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 status = "disabled"; 620 }; 621 622 i2c2: i2c@2005a000 { 623 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 624 reg = <0x2005a000 0x1000>; 625 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 626 clock-names = "i2c"; 627 clocks = <&cru PCLK_I2C2>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&i2c2_xfer>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 status = "disabled"; 633 }; 634 635 i2c3: i2c@2005e000 { 636 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 637 reg = <0x2005e000 0x1000>; 638 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 639 clock-names = "i2c"; 640 clocks = <&cru PCLK_I2C3>; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&i2c3_xfer>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 648 uart0: serial@20060000 { 649 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 650 reg = <0x20060000 0x100>; 651 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 652 clock-frequency = <24000000>; 653 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 654 clock-names = "baudclk", "apb_pclk"; 655 dmas = <&pdma 2>, <&pdma 3>; 656 dma-names = "tx", "rx"; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 659 reg-io-width = <4>; 660 reg-shift = <2>; 661 status = "disabled"; 662 }; 663 664 uart1: serial@20064000 { 665 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 666 reg = <0x20064000 0x100>; 667 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 668 clock-frequency = <24000000>; 669 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 670 clock-names = "baudclk", "apb_pclk"; 671 dmas = <&pdma 4>, <&pdma 5>; 672 dma-names = "tx", "rx"; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&uart1_xfer>; 675 reg-io-width = <4>; 676 reg-shift = <2>; 677 status = "disabled"; 678 }; 679 680 uart2: serial@20068000 { 681 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 682 reg = <0x20068000 0x100>; 683 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 684 clock-frequency = <24000000>; 685 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 686 clock-names = "baudclk", "apb_pclk"; 687 dmas = <&pdma 6>, <&pdma 7>; 688 dma-names = "tx", "rx"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&uart2_xfer>; 691 reg-io-width = <4>; 692 reg-shift = <2>; 693 status = "disabled"; 694 }; 695 696 saradc: saradc@2006c000 { 697 compatible = "rockchip,saradc"; 698 reg = <0x2006c000 0x100>; 699 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 701 clock-names = "saradc", "apb_pclk"; 702 resets = <&cru SRST_SARADC>; 703 reset-names = "saradc-apb"; 704 #io-channel-cells = <1>; 705 status = "disabled"; 706 }; 707 708 i2c0: i2c@20072000 { 709 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 710 reg = <0x20072000 0x1000>; 711 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 712 clock-names = "i2c"; 713 clocks = <&cru PCLK_I2C0>; 714 pinctrl-names = "default"; 715 pinctrl-0 = <&i2c0_xfer>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 spi0: spi@20074000 { 722 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 723 reg = <0x20074000 0x1000>; 724 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 726 clock-names = "spiclk", "apb_pclk"; 727 dmas = <&pdma 8>, <&pdma 9>; 728 dma-names = "tx", "rx"; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 pdma: dma-controller@20078000 { 737 compatible = "arm,pl330", "arm,primecell"; 738 reg = <0x20078000 0x4000>; 739 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 741 arm,pl330-broken-no-flushp; 742 arm,pl330-periph-burst; 743 clocks = <&cru ACLK_DMAC>; 744 clock-names = "apb_pclk"; 745 #dma-cells = <1>; 746 }; 747 748 gmac: ethernet@2008c000 { 749 compatible = "rockchip,rk3128-gmac"; 750 reg = <0x2008c000 0x4000>; 751 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 753 interrupt-names = "macirq", "eth_wake_irq"; 754 clocks = <&cru SCLK_MAC>, 755 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 756 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 757 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 758 clock-names = "stmmaceth", 759 "mac_clk_rx", "mac_clk_tx", 760 "clk_mac_ref", "clk_mac_refout", 761 "aclk_mac", "pclk_mac"; 762 resets = <&cru SRST_GMAC>; 763 reset-names = "stmmaceth"; 764 rockchip,grf = <&grf>; 765 rx-fifo-depth = <4096>; 766 tx-fifo-depth = <2048>; 767 status = "disabled"; 768 769 mdio: mdio { 770 compatible = "snps,dwmac-mdio"; 771 #address-cells = <0x1>; 772 #size-cells = <0x0>; 773 }; 774 }; 775 776 pinctrl: pinctrl { 777 compatible = "rockchip,rk3128-pinctrl"; 778 rockchip,grf = <&grf>; 779 #address-cells = <1>; 780 #size-cells = <1>; 781 ranges; 782 783 gpio0: gpio@2007c000 { 784 compatible = "rockchip,gpio-bank"; 785 reg = <0x2007c000 0x100>; 786 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&cru PCLK_GPIO0>; 788 gpio-controller; 789 #gpio-cells = <2>; 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 }; 793 794 gpio1: gpio@20080000 { 795 compatible = "rockchip,gpio-bank"; 796 reg = <0x20080000 0x100>; 797 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&cru PCLK_GPIO1>; 799 gpio-controller; 800 #gpio-cells = <2>; 801 interrupt-controller; 802 #interrupt-cells = <2>; 803 }; 804 805 gpio2: gpio@20084000 { 806 compatible = "rockchip,gpio-bank"; 807 reg = <0x20084000 0x100>; 808 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&cru PCLK_GPIO2>; 810 gpio-controller; 811 #gpio-cells = <2>; 812 interrupt-controller; 813 #interrupt-cells = <2>; 814 }; 815 816 gpio3: gpio@20088000 { 817 compatible = "rockchip,gpio-bank"; 818 reg = <0x20088000 0x100>; 819 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&cru PCLK_GPIO3>; 821 gpio-controller; 822 #gpio-cells = <2>; 823 interrupt-controller; 824 #interrupt-cells = <2>; 825 }; 826 827 pcfg_pull_default: pcfg-pull-default { 828 bias-pull-pin-default; 829 }; 830 831 pcfg_pull_none: pcfg-pull-none { 832 bias-disable; 833 }; 834 835 emmc { 836 emmc_clk: emmc-clk { 837 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 838 }; 839 840 emmc_cmd: emmc-cmd { 841 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 842 }; 843 844 emmc_cmd1: emmc-cmd1 { 845 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 846 }; 847 848 emmc_pwr: emmc-pwr { 849 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 850 }; 851 852 emmc_bus1: emmc-bus1 { 853 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 854 }; 855 856 emmc_bus4: emmc-bus4 { 857 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 858 <1 RK_PD1 2 &pcfg_pull_default>, 859 <1 RK_PD2 2 &pcfg_pull_default>, 860 <1 RK_PD3 2 &pcfg_pull_default>; 861 }; 862 863 emmc_bus8: emmc-bus8 { 864 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 865 <1 RK_PD1 2 &pcfg_pull_default>, 866 <1 RK_PD2 2 &pcfg_pull_default>, 867 <1 RK_PD3 2 &pcfg_pull_default>, 868 <1 RK_PD4 2 &pcfg_pull_default>, 869 <1 RK_PD5 2 &pcfg_pull_default>, 870 <1 RK_PD6 2 &pcfg_pull_default>, 871 <1 RK_PD7 2 &pcfg_pull_default>; 872 }; 873 }; 874 875 gmac { 876 rgmii_pins: rgmii-pins { 877 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 878 <2 RK_PB1 3 &pcfg_pull_default>, 879 <2 RK_PB3 3 &pcfg_pull_default>, 880 <2 RK_PB4 3 &pcfg_pull_default>, 881 <2 RK_PB5 3 &pcfg_pull_default>, 882 <2 RK_PB6 3 &pcfg_pull_default>, 883 <2 RK_PC0 3 &pcfg_pull_default>, 884 <2 RK_PC1 3 &pcfg_pull_default>, 885 <2 RK_PC2 3 &pcfg_pull_default>, 886 <2 RK_PC3 3 &pcfg_pull_default>, 887 <2 RK_PD1 3 &pcfg_pull_default>, 888 <2 RK_PC4 4 &pcfg_pull_default>, 889 <2 RK_PC5 4 &pcfg_pull_default>, 890 <2 RK_PC6 4 &pcfg_pull_default>, 891 <2 RK_PC7 4 &pcfg_pull_default>; 892 }; 893 894 rmii_pins: rmii-pins { 895 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 896 <2 RK_PB4 3 &pcfg_pull_default>, 897 <2 RK_PB5 3 &pcfg_pull_default>, 898 <2 RK_PB6 3 &pcfg_pull_default>, 899 <2 RK_PB7 3 &pcfg_pull_default>, 900 <2 RK_PC0 3 &pcfg_pull_default>, 901 <2 RK_PC1 3 &pcfg_pull_default>, 902 <2 RK_PC2 3 &pcfg_pull_default>, 903 <2 RK_PC3 3 &pcfg_pull_default>, 904 <2 RK_PD1 3 &pcfg_pull_default>; 905 }; 906 }; 907 908 hdmi { 909 hdmii2c_xfer: hdmii2c-xfer { 910 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 911 <0 RK_PA7 2 &pcfg_pull_none>; 912 }; 913 914 hdmi_hpd: hdmi-hpd { 915 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 916 }; 917 918 hdmi_cec: hdmi-cec { 919 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 920 }; 921 }; 922 923 i2c0 { 924 i2c0_xfer: i2c0-xfer { 925 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 926 <0 RK_PA1 1 &pcfg_pull_none>; 927 }; 928 }; 929 930 i2c1 { 931 i2c1_xfer: i2c1-xfer { 932 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 933 <0 RK_PA3 1 &pcfg_pull_none>; 934 }; 935 }; 936 937 i2c2 { 938 i2c2_xfer: i2c2-xfer { 939 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 940 <2 RK_PC5 3 &pcfg_pull_none>; 941 }; 942 }; 943 944 i2c3 { 945 i2c3_xfer: i2c3-xfer { 946 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 947 <0 RK_PA7 1 &pcfg_pull_none>; 948 }; 949 }; 950 951 i2s { 952 i2s_bus: i2s-bus { 953 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 954 <0 RK_PB1 1 &pcfg_pull_none>, 955 <0 RK_PB3 1 &pcfg_pull_none>, 956 <0 RK_PB4 1 &pcfg_pull_none>, 957 <0 RK_PB5 1 &pcfg_pull_none>, 958 <0 RK_PB6 1 &pcfg_pull_none>; 959 }; 960 961 i2s1_bus: i2s1-bus { 962 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 963 <1 RK_PA1 1 &pcfg_pull_none>, 964 <1 RK_PA2 1 &pcfg_pull_none>, 965 <1 RK_PA3 1 &pcfg_pull_none>, 966 <1 RK_PA4 1 &pcfg_pull_none>, 967 <1 RK_PA5 1 &pcfg_pull_none>; 968 }; 969 }; 970 971 lcdc { 972 lcdc_dclk: lcdc-dclk { 973 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 974 }; 975 976 lcdc_den: lcdc-den { 977 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 978 }; 979 980 lcdc_hsync: lcdc-hsync { 981 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 982 }; 983 984 lcdc_vsync: lcdc-vsync { 985 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 986 }; 987 988 lcdc_rgb24: lcdc-rgb24 { 989 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 990 <2 RK_PB5 1 &pcfg_pull_none>, 991 <2 RK_PB6 1 &pcfg_pull_none>, 992 <2 RK_PB7 1 &pcfg_pull_none>, 993 <2 RK_PC0 1 &pcfg_pull_none>, 994 <2 RK_PC1 1 &pcfg_pull_none>, 995 <2 RK_PC2 1 &pcfg_pull_none>, 996 <2 RK_PC3 1 &pcfg_pull_none>, 997 <2 RK_PC4 1 &pcfg_pull_none>, 998 <2 RK_PC5 1 &pcfg_pull_none>, 999 <2 RK_PC6 1 &pcfg_pull_none>, 1000 <2 RK_PC7 1 &pcfg_pull_none>, 1001 <2 RK_PD0 1 &pcfg_pull_none>, 1002 <2 RK_PD1 1 &pcfg_pull_none>; 1003 }; 1004 }; 1005 1006 nfc { 1007 flash_ale: flash-ale { 1008 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 1009 }; 1010 1011 flash_cle: flash-cle { 1012 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 1013 }; 1014 1015 flash_wrn: flash-wrn { 1016 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1017 }; 1018 1019 flash_rdn: flash-rdn { 1020 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 1021 }; 1022 1023 flash_rdy: flash-rdy { 1024 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1025 }; 1026 1027 flash_cs0: flash-cs0 { 1028 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1029 }; 1030 1031 flash_dqs: flash-dqs { 1032 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 1033 }; 1034 1035 flash_bus8: flash-bus8 { 1036 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1037 <1 RK_PD1 1 &pcfg_pull_none>, 1038 <1 RK_PD2 1 &pcfg_pull_none>, 1039 <1 RK_PD3 1 &pcfg_pull_none>, 1040 <1 RK_PD4 1 &pcfg_pull_none>, 1041 <1 RK_PD5 1 &pcfg_pull_none>, 1042 <1 RK_PD6 1 &pcfg_pull_none>, 1043 <1 RK_PD7 1 &pcfg_pull_none>; 1044 }; 1045 }; 1046 1047 pwm0 { 1048 pwm0_pin: pwm0-pin { 1049 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 1050 }; 1051 }; 1052 1053 pwm1 { 1054 pwm1_pin: pwm1-pin { 1055 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1056 }; 1057 }; 1058 1059 pwm2 { 1060 pwm2_pin: pwm2-pin { 1061 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1062 }; 1063 }; 1064 1065 pwm3 { 1066 pwm3_pin: pwm3-pin { 1067 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 1068 }; 1069 }; 1070 1071 sdio { 1072 sdio_clk: sdio-clk { 1073 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1074 }; 1075 1076 sdio_cmd: sdio-cmd { 1077 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1078 }; 1079 1080 sdio_pwren: sdio-pwren { 1081 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1082 }; 1083 1084 sdio_bus4: sdio-bus4 { 1085 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1086 <1 RK_PA2 2 &pcfg_pull_default>, 1087 <1 RK_PA4 2 &pcfg_pull_default>, 1088 <1 RK_PA5 2 &pcfg_pull_default>; 1089 }; 1090 }; 1091 1092 sdmmc { 1093 sdmmc_clk: sdmmc-clk { 1094 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1095 }; 1096 1097 sdmmc_cmd: sdmmc-cmd { 1098 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1099 }; 1100 1101 sdmmc_det: sdmmc-det { 1102 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1103 }; 1104 1105 sdmmc_wp: sdmmc-wp { 1106 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1107 }; 1108 1109 sdmmc_pwren: sdmmc-pwren { 1110 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 1111 }; 1112 1113 sdmmc_bus4: sdmmc-bus4 { 1114 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1115 <1 RK_PC3 1 &pcfg_pull_default>, 1116 <1 RK_PC4 1 &pcfg_pull_default>, 1117 <1 RK_PC5 1 &pcfg_pull_default>; 1118 }; 1119 }; 1120 1121 spdif { 1122 spdif_tx: spdif-tx { 1123 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1124 }; 1125 }; 1126 1127 spi0 { 1128 spi0_clk: spi0-clk { 1129 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1130 }; 1131 1132 spi0_cs0: spi0-cs0 { 1133 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1134 }; 1135 1136 spi0_tx: spi0-tx { 1137 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1138 }; 1139 1140 spi0_rx: spi0-rx { 1141 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1142 }; 1143 1144 spi0_cs1: spi0-cs1 { 1145 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1146 }; 1147 1148 spi1_clk: spi1-clk { 1149 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1150 }; 1151 1152 spi1_cs0: spi1-cs0 { 1153 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1154 }; 1155 1156 spi1_tx: spi1-tx { 1157 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1158 }; 1159 1160 spi1_rx: spi1-rx { 1161 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1162 }; 1163 1164 spi1_cs1: spi1-cs1 { 1165 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1166 }; 1167 1168 spi2_clk: spi2-clk { 1169 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1170 }; 1171 1172 spi2_cs0: spi2-cs0 { 1173 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1174 }; 1175 1176 spi2_tx: spi2-tx { 1177 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1178 }; 1179 1180 spi2_rx: spi2-rx { 1181 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1182 }; 1183 }; 1184 1185 uart0 { 1186 uart0_xfer: uart0-xfer { 1187 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1188 <2 RK_PD3 2 &pcfg_pull_none>; 1189 }; 1190 1191 uart0_cts: uart0-cts { 1192 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1193 }; 1194 1195 uart0_rts: uart0-rts { 1196 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1197 }; 1198 }; 1199 1200 uart1 { 1201 uart1_xfer: uart1-xfer { 1202 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1203 <1 RK_PB2 2 &pcfg_pull_default>; 1204 }; 1205 1206 uart1_cts: uart1-cts { 1207 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1208 }; 1209 1210 uart1_rts: uart1-rts { 1211 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1212 }; 1213 }; 1214 1215 uart2 { 1216 uart2_xfer: uart2-xfer { 1217 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1218 <1 RK_PC3 2 &pcfg_pull_none>; 1219 }; 1220 1221 uart2_cts: uart2-cts { 1222 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1223 }; 1224 1225 uart2_rts: uart2-rts { 1226 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1227 }; 1228 }; 1229 }; 1230}; 1231