1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 enable-method = "rockchip,rk3036-smp"; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 resets = <&cru SRST_CORE0>; 39 operating-points-v2 = <&cpu_opp_table>; 40 #cooling-cells = <2>; /* min followed by max */ 41 }; 42 43 cpu1: cpu@f01 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0xf01>; 47 resets = <&cru SRST_CORE1>; 48 operating-points-v2 = <&cpu_opp_table>; 49 }; 50 51 cpu2: cpu@f02 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf02>; 55 resets = <&cru SRST_CORE2>; 56 operating-points-v2 = <&cpu_opp_table>; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 operating-points-v2 = <&cpu_opp_table>; 65 }; 66 }; 67 68 cpu_opp_table: opp-table-0 { 69 compatible = "operating-points-v2"; 70 opp-shared; 71 72 opp-216000000 { 73 opp-hz = /bits/ 64 <216000000>; 74 opp-microvolt = <950000 950000 1325000>; 75 }; 76 opp-408000000 { 77 opp-hz = /bits/ 64 <408000000>; 78 opp-microvolt = <950000 950000 1325000>; 79 }; 80 opp-600000000 { 81 opp-hz = /bits/ 64 <600000000>; 82 opp-microvolt = <950000 950000 1325000>; 83 }; 84 opp-696000000 { 85 opp-hz = /bits/ 64 <696000000>; 86 opp-microvolt = <975000 975000 1325000>; 87 }; 88 opp-816000000 { 89 opp-hz = /bits/ 64 <816000000>; 90 opp-microvolt = <1075000 1075000 1325000>; 91 opp-suspend; 92 }; 93 opp-1008000000 { 94 opp-hz = /bits/ 64 <1008000000>; 95 opp-microvolt = <1200000 1200000 1325000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <1325000 1325000 1325000>; 100 }; 101 }; 102 103 timer { 104 compatible = "arm,armv7-timer"; 105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 arm,cpu-registers-not-fw-configured; 110 clock-frequency = <24000000>; 111 }; 112 113 xin24m: oscillator { 114 compatible = "fixed-clock"; 115 clock-frequency = <24000000>; 116 clock-output-names = "xin24m"; 117 #clock-cells = <0>; 118 }; 119 120 imem: sram@10080000 { 121 compatible = "mmio-sram"; 122 reg = <0x10080000 0x2000>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0x10080000 0x2000>; 126 127 smp-sram@0 { 128 compatible = "rockchip,rk3066-smp-sram"; 129 reg = <0x00 0x10>; 130 }; 131 }; 132 133 pmu: syscon@100a0000 { 134 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 135 reg = <0x100a0000 0x1000>; 136 }; 137 138 gic: interrupt-controller@10139000 { 139 compatible = "arm,cortex-a7-gic"; 140 reg = <0x10139000 0x1000>, 141 <0x1013a000 0x1000>, 142 <0x1013c000 0x2000>, 143 <0x1013e000 0x2000>; 144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 #address-cells = <0>; 148 }; 149 150 usb_otg: usb@10180000 { 151 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 152 reg = <0x10180000 0x40000>; 153 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&cru HCLK_OTG>; 155 clock-names = "otg"; 156 dr_mode = "otg"; 157 g-np-tx-fifo-size = <16>; 158 g-rx-fifo-size = <280>; 159 g-tx-fifo-size = <256 128 128 64 32 16>; 160 phys = <&usb2phy_otg>; 161 phy-names = "usb2-phy"; 162 status = "disabled"; 163 }; 164 165 usb_host_ehci: usb@101c0000 { 166 compatible = "generic-ehci"; 167 reg = <0x101c0000 0x20000>; 168 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&cru HCLK_HOST2>; 170 phys = <&usb2phy_host>; 171 phy-names = "usb"; 172 status = "disabled"; 173 }; 174 175 usb_host_ohci: usb@101e0000 { 176 compatible = "generic-ohci"; 177 reg = <0x101e0000 0x20000>; 178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru HCLK_HOST2>; 180 phys = <&usb2phy_host>; 181 phy-names = "usb"; 182 status = "disabled"; 183 }; 184 185 sdmmc: mmc@10214000 { 186 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 187 reg = <0x10214000 0x4000>; 188 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 190 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 191 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 192 dmas = <&pdma 10>; 193 dma-names = "rx-tx"; 194 fifo-depth = <256>; 195 max-frequency = <150000000>; 196 resets = <&cru SRST_SDMMC>; 197 reset-names = "reset"; 198 status = "disabled"; 199 }; 200 201 sdio: mmc@10218000 { 202 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 203 reg = <0x10218000 0x4000>; 204 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 206 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 207 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 208 dmas = <&pdma 11>; 209 dma-names = "rx-tx"; 210 fifo-depth = <256>; 211 max-frequency = <150000000>; 212 resets = <&cru SRST_SDIO>; 213 reset-names = "reset"; 214 status = "disabled"; 215 }; 216 217 emmc: mmc@1021c000 { 218 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 219 reg = <0x1021c000 0x4000>; 220 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 222 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 223 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 224 dmas = <&pdma 12>; 225 dma-names = "rx-tx"; 226 fifo-depth = <256>; 227 max-frequency = <150000000>; 228 resets = <&cru SRST_EMMC>; 229 reset-names = "reset"; 230 status = "disabled"; 231 }; 232 233 nfc: nand-controller@10500000 { 234 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 235 reg = <0x10500000 0x4000>; 236 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 238 clock-names = "ahb", "nfc"; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 241 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 242 status = "disabled"; 243 }; 244 245 cru: clock-controller@20000000 { 246 compatible = "rockchip,rk3128-cru"; 247 reg = <0x20000000 0x1000>; 248 clocks = <&xin24m>; 249 clock-names = "xin24m"; 250 rockchip,grf = <&grf>; 251 #clock-cells = <1>; 252 #reset-cells = <1>; 253 assigned-clocks = <&cru PLL_GPLL>; 254 assigned-clock-rates = <594000000>; 255 }; 256 257 grf: syscon@20008000 { 258 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 259 reg = <0x20008000 0x1000>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 263 usb2phy: usb2phy@17c { 264 compatible = "rockchip,rk3128-usb2phy"; 265 reg = <0x017c 0x0c>; 266 clocks = <&cru SCLK_OTGPHY0>; 267 clock-names = "phyclk"; 268 clock-output-names = "usb480m_phy"; 269 #clock-cells = <0>; 270 status = "disabled"; 271 272 usb2phy_host: host-port { 273 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 274 interrupt-names = "linestate"; 275 #phy-cells = <0>; 276 status = "disabled"; 277 }; 278 279 usb2phy_otg: otg-port { 280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "otg-bvalid", "otg-id", 284 "linestate"; 285 #phy-cells = <0>; 286 status = "disabled"; 287 }; 288 }; 289 }; 290 291 timer0: timer@20044000 { 292 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 293 reg = <0x20044000 0x20>; 294 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 296 clock-names = "pclk", "timer"; 297 }; 298 299 timer1: timer@20044020 { 300 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 301 reg = <0x20044020 0x20>; 302 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 304 clock-names = "pclk", "timer"; 305 }; 306 307 timer2: timer@20044040 { 308 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 309 reg = <0x20044040 0x20>; 310 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 312 clock-names = "pclk", "timer"; 313 }; 314 315 timer3: timer@20044060 { 316 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 317 reg = <0x20044060 0x20>; 318 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 320 clock-names = "pclk", "timer"; 321 }; 322 323 timer4: timer@20044080 { 324 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 325 reg = <0x20044080 0x20>; 326 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 328 clock-names = "pclk", "timer"; 329 }; 330 331 timer5: timer@200440a0 { 332 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 333 reg = <0x200440a0 0x20>; 334 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 336 clock-names = "pclk", "timer"; 337 }; 338 339 watchdog: watchdog@2004c000 { 340 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 341 reg = <0x2004c000 0x100>; 342 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru PCLK_WDT>; 344 status = "disabled"; 345 }; 346 347 pwm0: pwm@20050000 { 348 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 349 reg = <0x20050000 0x10>; 350 clocks = <&cru PCLK_PWM>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pwm0_pin>; 353 #pwm-cells = <3>; 354 status = "disabled"; 355 }; 356 357 pwm1: pwm@20050010 { 358 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 359 reg = <0x20050010 0x10>; 360 clocks = <&cru PCLK_PWM>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pwm1_pin>; 363 #pwm-cells = <3>; 364 status = "disabled"; 365 }; 366 367 pwm2: pwm@20050020 { 368 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 369 reg = <0x20050020 0x10>; 370 clocks = <&cru PCLK_PWM>; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&pwm2_pin>; 373 #pwm-cells = <3>; 374 status = "disabled"; 375 }; 376 377 pwm3: pwm@20050030 { 378 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 379 reg = <0x20050030 0x10>; 380 clocks = <&cru PCLK_PWM>; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pwm3_pin>; 383 #pwm-cells = <3>; 384 status = "disabled"; 385 }; 386 387 i2c1: i2c@20056000 { 388 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 389 reg = <0x20056000 0x1000>; 390 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 391 clock-names = "i2c"; 392 clocks = <&cru PCLK_I2C1>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&i2c1_xfer>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 status = "disabled"; 398 }; 399 400 i2c2: i2c@2005a000 { 401 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 402 reg = <0x2005a000 0x1000>; 403 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 404 clock-names = "i2c"; 405 clocks = <&cru PCLK_I2C2>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&i2c2_xfer>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 i2c3: i2c@2005e000 { 414 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 415 reg = <0x2005e000 0x1000>; 416 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 417 clock-names = "i2c"; 418 clocks = <&cru PCLK_I2C3>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2c3_xfer>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 status = "disabled"; 424 }; 425 426 uart0: serial@20060000 { 427 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 428 reg = <0x20060000 0x100>; 429 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 430 clock-frequency = <24000000>; 431 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 432 clock-names = "baudclk", "apb_pclk"; 433 dmas = <&pdma 2>, <&pdma 3>; 434 dma-names = "tx", "rx"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 437 reg-io-width = <4>; 438 reg-shift = <2>; 439 status = "disabled"; 440 }; 441 442 uart1: serial@20064000 { 443 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 444 reg = <0x20064000 0x100>; 445 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 446 clock-frequency = <24000000>; 447 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 448 clock-names = "baudclk", "apb_pclk"; 449 dmas = <&pdma 4>, <&pdma 5>; 450 dma-names = "tx", "rx"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&uart1_xfer>; 453 reg-io-width = <4>; 454 reg-shift = <2>; 455 status = "disabled"; 456 }; 457 458 uart2: serial@20068000 { 459 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 460 reg = <0x20068000 0x100>; 461 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 462 clock-frequency = <24000000>; 463 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 464 clock-names = "baudclk", "apb_pclk"; 465 dmas = <&pdma 6>, <&pdma 7>; 466 dma-names = "tx", "rx"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&uart2_xfer>; 469 reg-io-width = <4>; 470 reg-shift = <2>; 471 status = "disabled"; 472 }; 473 474 saradc: saradc@2006c000 { 475 compatible = "rockchip,saradc"; 476 reg = <0x2006c000 0x100>; 477 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 479 clock-names = "saradc", "apb_pclk"; 480 resets = <&cru SRST_SARADC>; 481 reset-names = "saradc-apb"; 482 #io-channel-cells = <1>; 483 status = "disabled"; 484 }; 485 486 i2c0: i2c@20072000 { 487 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 488 reg = <0x20072000 0x1000>; 489 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 490 clock-names = "i2c"; 491 clocks = <&cru PCLK_I2C0>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&i2c0_xfer>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 status = "disabled"; 497 }; 498 499 spi0: spi@20074000 { 500 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 501 reg = <0x20074000 0x1000>; 502 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 504 clock-names = "spiclk", "apb_pclk"; 505 dmas = <&pdma 8>, <&pdma 9>; 506 dma-names = "tx", "rx"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "disabled"; 512 }; 513 514 pdma: dma-controller@20078000 { 515 compatible = "arm,pl330", "arm,primecell"; 516 reg = <0x20078000 0x4000>; 517 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 519 arm,pl330-broken-no-flushp; 520 arm,pl330-periph-burst; 521 clocks = <&cru ACLK_DMAC>; 522 clock-names = "apb_pclk"; 523 #dma-cells = <1>; 524 }; 525 526 pinctrl: pinctrl { 527 compatible = "rockchip,rk3128-pinctrl"; 528 rockchip,grf = <&grf>; 529 #address-cells = <1>; 530 #size-cells = <1>; 531 ranges; 532 533 gpio0: gpio@2007c000 { 534 compatible = "rockchip,gpio-bank"; 535 reg = <0x2007c000 0x100>; 536 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&cru PCLK_GPIO0>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 }; 543 544 gpio1: gpio@20080000 { 545 compatible = "rockchip,gpio-bank"; 546 reg = <0x20080000 0x100>; 547 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cru PCLK_GPIO1>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 }; 554 555 gpio2: gpio@20084000 { 556 compatible = "rockchip,gpio-bank"; 557 reg = <0x20084000 0x100>; 558 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cru PCLK_GPIO2>; 560 gpio-controller; 561 #gpio-cells = <2>; 562 interrupt-controller; 563 #interrupt-cells = <2>; 564 }; 565 566 gpio3: gpio@20088000 { 567 compatible = "rockchip,gpio-bank"; 568 reg = <0x20088000 0x100>; 569 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cru PCLK_GPIO3>; 571 gpio-controller; 572 #gpio-cells = <2>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 }; 576 577 pcfg_pull_default: pcfg-pull-default { 578 bias-pull-pin-default; 579 }; 580 581 pcfg_pull_none: pcfg-pull-none { 582 bias-disable; 583 }; 584 585 emmc { 586 emmc_clk: emmc-clk { 587 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 588 }; 589 590 emmc_cmd: emmc-cmd { 591 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 592 }; 593 594 emmc_cmd1: emmc-cmd1 { 595 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 596 }; 597 598 emmc_pwr: emmc-pwr { 599 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 600 }; 601 602 emmc_bus1: emmc-bus1 { 603 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 604 }; 605 606 emmc_bus4: emmc-bus4 { 607 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 608 <1 RK_PD1 2 &pcfg_pull_default>, 609 <1 RK_PD2 2 &pcfg_pull_default>, 610 <1 RK_PD3 2 &pcfg_pull_default>; 611 }; 612 613 emmc_bus8: emmc-bus8 { 614 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 615 <1 RK_PD1 2 &pcfg_pull_default>, 616 <1 RK_PD2 2 &pcfg_pull_default>, 617 <1 RK_PD3 2 &pcfg_pull_default>, 618 <1 RK_PD4 2 &pcfg_pull_default>, 619 <1 RK_PD5 2 &pcfg_pull_default>, 620 <1 RK_PD6 2 &pcfg_pull_default>, 621 <1 RK_PD7 2 &pcfg_pull_default>; 622 }; 623 }; 624 625 gmac { 626 rgmii_pins: rgmii-pins { 627 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 628 <2 RK_PB1 3 &pcfg_pull_default>, 629 <2 RK_PB3 3 &pcfg_pull_default>, 630 <2 RK_PB4 3 &pcfg_pull_default>, 631 <2 RK_PB5 3 &pcfg_pull_default>, 632 <2 RK_PB6 3 &pcfg_pull_default>, 633 <2 RK_PC0 3 &pcfg_pull_default>, 634 <2 RK_PC1 3 &pcfg_pull_default>, 635 <2 RK_PC2 3 &pcfg_pull_default>, 636 <2 RK_PC3 3 &pcfg_pull_default>, 637 <2 RK_PD1 3 &pcfg_pull_default>, 638 <2 RK_PC4 4 &pcfg_pull_default>, 639 <2 RK_PC5 4 &pcfg_pull_default>, 640 <2 RK_PC6 4 &pcfg_pull_default>, 641 <2 RK_PC7 4 &pcfg_pull_default>; 642 }; 643 644 rmii_pins: rmii-pins { 645 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 646 <2 RK_PB4 3 &pcfg_pull_default>, 647 <2 RK_PB5 3 &pcfg_pull_default>, 648 <2 RK_PB6 3 &pcfg_pull_default>, 649 <2 RK_PB7 3 &pcfg_pull_default>, 650 <2 RK_PC0 3 &pcfg_pull_default>, 651 <2 RK_PC1 3 &pcfg_pull_default>, 652 <2 RK_PC2 3 &pcfg_pull_default>, 653 <2 RK_PC3 3 &pcfg_pull_default>, 654 <2 RK_PD1 3 &pcfg_pull_default>; 655 }; 656 }; 657 658 hdmi { 659 hdmii2c_xfer: hdmii2c-xfer { 660 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 661 <0 RK_PA7 2 &pcfg_pull_none>; 662 }; 663 664 hdmi_hpd: hdmi-hpd { 665 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 666 }; 667 668 hdmi_cec: hdmi-cec { 669 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 670 }; 671 }; 672 673 i2c0 { 674 i2c0_xfer: i2c0-xfer { 675 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 676 <0 RK_PA1 1 &pcfg_pull_none>; 677 }; 678 }; 679 680 i2c1 { 681 i2c1_xfer: i2c1-xfer { 682 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 683 <0 RK_PA3 1 &pcfg_pull_none>; 684 }; 685 }; 686 687 i2c2 { 688 i2c2_xfer: i2c2-xfer { 689 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 690 <2 RK_PC5 3 &pcfg_pull_none>; 691 }; 692 }; 693 694 i2c3 { 695 i2c3_xfer: i2c3-xfer { 696 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 697 <0 RK_PA7 1 &pcfg_pull_none>; 698 }; 699 }; 700 701 i2s { 702 i2s_bus: i2s-bus { 703 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 704 <0 RK_PB1 1 &pcfg_pull_none>, 705 <0 RK_PB3 1 &pcfg_pull_none>, 706 <0 RK_PB4 1 &pcfg_pull_none>, 707 <0 RK_PB5 1 &pcfg_pull_none>, 708 <0 RK_PB6 1 &pcfg_pull_none>; 709 }; 710 711 i2s1_bus: i2s1-bus { 712 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 713 <1 RK_PA1 1 &pcfg_pull_none>, 714 <1 RK_PA2 1 &pcfg_pull_none>, 715 <1 RK_PA3 1 &pcfg_pull_none>, 716 <1 RK_PA4 1 &pcfg_pull_none>, 717 <1 RK_PA5 1 &pcfg_pull_none>; 718 }; 719 }; 720 721 lcdc { 722 lcdc_dclk: lcdc-dclk { 723 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 724 }; 725 726 lcdc_den: lcdc-den { 727 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 728 }; 729 730 lcdc_hsync: lcdc-hsync { 731 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 732 }; 733 734 lcdc_vsync: lcdc-vsync { 735 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 736 }; 737 738 lcdc_rgb24: lcdc-rgb24 { 739 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 740 <2 RK_PB5 1 &pcfg_pull_none>, 741 <2 RK_PB6 1 &pcfg_pull_none>, 742 <2 RK_PB7 1 &pcfg_pull_none>, 743 <2 RK_PC0 1 &pcfg_pull_none>, 744 <2 RK_PC1 1 &pcfg_pull_none>, 745 <2 RK_PC2 1 &pcfg_pull_none>, 746 <2 RK_PC3 1 &pcfg_pull_none>, 747 <2 RK_PC4 1 &pcfg_pull_none>, 748 <2 RK_PC5 1 &pcfg_pull_none>, 749 <2 RK_PC6 1 &pcfg_pull_none>, 750 <2 RK_PC7 1 &pcfg_pull_none>, 751 <2 RK_PD0 1 &pcfg_pull_none>, 752 <2 RK_PD1 1 &pcfg_pull_none>; 753 }; 754 }; 755 756 nfc { 757 flash_ale: flash-ale { 758 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 759 }; 760 761 flash_cle: flash-cle { 762 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 763 }; 764 765 flash_wrn: flash-wrn { 766 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 767 }; 768 769 flash_rdn: flash-rdn { 770 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 771 }; 772 773 flash_rdy: flash-rdy { 774 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 775 }; 776 777 flash_cs0: flash-cs0 { 778 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 779 }; 780 781 flash_dqs: flash-dqs { 782 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 783 }; 784 785 flash_bus8: flash-bus8 { 786 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 787 <1 RK_PD1 1 &pcfg_pull_none>, 788 <1 RK_PD2 1 &pcfg_pull_none>, 789 <1 RK_PD3 1 &pcfg_pull_none>, 790 <1 RK_PD4 1 &pcfg_pull_none>, 791 <1 RK_PD5 1 &pcfg_pull_none>, 792 <1 RK_PD6 1 &pcfg_pull_none>, 793 <1 RK_PD7 1 &pcfg_pull_none>; 794 }; 795 }; 796 797 pwm0 { 798 pwm0_pin: pwm0-pin { 799 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 800 }; 801 }; 802 803 pwm1 { 804 pwm1_pin: pwm1-pin { 805 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 806 }; 807 }; 808 809 pwm2 { 810 pwm2_pin: pwm2-pin { 811 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 812 }; 813 }; 814 815 pwm3 { 816 pwm3_pin: pwm3-pin { 817 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 818 }; 819 }; 820 821 sdio { 822 sdio_clk: sdio-clk { 823 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 824 }; 825 826 sdio_cmd: sdio-cmd { 827 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 828 }; 829 830 sdio_pwren: sdio-pwren { 831 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 832 }; 833 834 sdio_bus4: sdio-bus4 { 835 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 836 <1 RK_PA2 2 &pcfg_pull_default>, 837 <1 RK_PA4 2 &pcfg_pull_default>, 838 <1 RK_PA5 2 &pcfg_pull_default>; 839 }; 840 }; 841 842 sdmmc { 843 sdmmc_clk: sdmmc-clk { 844 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 845 }; 846 847 sdmmc_cmd: sdmmc-cmd { 848 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 849 }; 850 851 sdmmc_det: sdmmc-det { 852 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 853 }; 854 855 sdmmc_wp: sdmmc-wp { 856 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 857 }; 858 859 sdmmc_pwren: sdmmc-pwren { 860 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 861 }; 862 863 sdmmc_bus4: sdmmc-bus4 { 864 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 865 <1 RK_PC3 1 &pcfg_pull_default>, 866 <1 RK_PC4 1 &pcfg_pull_default>, 867 <1 RK_PC5 1 &pcfg_pull_default>; 868 }; 869 }; 870 871 spdif { 872 spdif_tx: spdif-tx { 873 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 874 }; 875 }; 876 877 spi0 { 878 spi0_clk: spi0-clk { 879 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 880 }; 881 882 spi0_cs0: spi0-cs0 { 883 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 884 }; 885 886 spi0_tx: spi0-tx { 887 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 888 }; 889 890 spi0_rx: spi0-rx { 891 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 892 }; 893 894 spi0_cs1: spi0-cs1 { 895 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 896 }; 897 898 spi1_clk: spi1-clk { 899 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 900 }; 901 902 spi1_cs0: spi1-cs0 { 903 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 904 }; 905 906 spi1_tx: spi1-tx { 907 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 908 }; 909 910 spi1_rx: spi1-rx { 911 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 912 }; 913 914 spi1_cs1: spi1-cs1 { 915 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 916 }; 917 918 spi2_clk: spi2-clk { 919 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 920 }; 921 922 spi2_cs0: spi2-cs0 { 923 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 924 }; 925 926 spi2_tx: spi2-tx { 927 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 928 }; 929 930 spi2_rx: spi2-rx { 931 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 932 }; 933 }; 934 935 uart0 { 936 uart0_xfer: uart0-xfer { 937 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 938 <2 RK_PD3 2 &pcfg_pull_none>; 939 }; 940 941 uart0_cts: uart0-cts { 942 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 943 }; 944 945 uart0_rts: uart0-rts { 946 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 947 }; 948 }; 949 950 uart1 { 951 uart1_xfer: uart1-xfer { 952 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 953 <1 RK_PB2 2 &pcfg_pull_default>; 954 }; 955 956 uart1_cts: uart1-cts { 957 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 958 }; 959 960 uart1_rts: uart1-rts { 961 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 962 }; 963 }; 964 965 uart2 { 966 uart2_xfer: uart2-xfer { 967 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 968 <1 RK_PC3 2 &pcfg_pull_none>; 969 }; 970 971 uart2_cts: uart2-cts { 972 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 973 }; 974 975 uart2_rts: uart2-rts { 976 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 977 }; 978 }; 979 }; 980}; 981