1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 }; 32 33 arm-pmu { 34 compatible = "arm,cortex-a7-pmu"; 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "rockchip,rk3036-smp"; 46 47 cpu0: cpu@f00 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a7"; 50 reg = <0xf00>; 51 clock-latency = <40000>; 52 clocks = <&cru ARMCLK>; 53 resets = <&cru SRST_CORE0>; 54 operating-points-v2 = <&cpu_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu1: cpu@f01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf01>; 62 resets = <&cru SRST_CORE1>; 63 operating-points-v2 = <&cpu_opp_table>; 64 }; 65 66 cpu2: cpu@f02 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a7"; 69 reg = <0xf02>; 70 resets = <&cru SRST_CORE2>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 cpu3: cpu@f03 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 reg = <0xf03>; 78 resets = <&cru SRST_CORE3>; 79 operating-points-v2 = <&cpu_opp_table>; 80 }; 81 }; 82 83 cpu_opp_table: opp-table-0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-216000000 { 88 opp-hz = /bits/ 64 <216000000>; 89 opp-microvolt = <950000 950000 1325000>; 90 }; 91 opp-408000000 { 92 opp-hz = /bits/ 64 <408000000>; 93 opp-microvolt = <950000 950000 1325000>; 94 }; 95 opp-600000000 { 96 opp-hz = /bits/ 64 <600000000>; 97 opp-microvolt = <950000 950000 1325000>; 98 }; 99 opp-696000000 { 100 opp-hz = /bits/ 64 <696000000>; 101 opp-microvolt = <975000 975000 1325000>; 102 }; 103 opp-816000000 { 104 opp-hz = /bits/ 64 <816000000>; 105 opp-microvolt = <1075000 1075000 1325000>; 106 opp-suspend; 107 }; 108 opp-1008000000 { 109 opp-hz = /bits/ 64 <1008000000>; 110 opp-microvolt = <1200000 1200000 1325000>; 111 }; 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <1325000 1325000 1325000>; 115 }; 116 }; 117 118 display_subsystem: display-subsystem { 119 compatible = "rockchip,display-subsystem"; 120 ports = <&vop_out>; 121 status = "disabled"; 122 }; 123 124 gpu_opp_table: opp-table-1 { 125 compatible = "operating-points-v2"; 126 127 opp-200000000 { 128 opp-hz = /bits/ 64 <200000000>; 129 opp-microvolt = <975000 975000 1250000>; 130 }; 131 opp-300000000 { 132 opp-hz = /bits/ 64 <300000000>; 133 opp-microvolt = <1050000 1050000 1250000>; 134 }; 135 opp-400000000 { 136 opp-hz = /bits/ 64 <400000000>; 137 opp-microvolt = <1150000 1150000 1250000>; 138 }; 139 opp-480000000 { 140 opp-hz = /bits/ 64 <480000000>; 141 opp-microvolt = <1250000 1250000 1250000>; 142 }; 143 }; 144 145 timer { 146 compatible = "arm,armv7-timer"; 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151 arm,cpu-registers-not-fw-configured; 152 clock-frequency = <24000000>; 153 }; 154 155 xin24m: oscillator { 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-output-names = "xin24m"; 159 #clock-cells = <0>; 160 }; 161 162 imem: sram@10080000 { 163 compatible = "mmio-sram"; 164 reg = <0x10080000 0x2000>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0 0x10080000 0x2000>; 168 169 smp-sram@0 { 170 compatible = "rockchip,rk3066-smp-sram"; 171 reg = <0x00 0x10>; 172 }; 173 }; 174 175 gpu: gpu@10090000 { 176 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 177 reg = <0x10090000 0x10000>; 178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "gp", 185 "gpmmu", 186 "pp0", 187 "ppmmu0", 188 "pp1", 189 "ppmmu1"; 190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 191 clock-names = "bus", "core"; 192 operating-points-v2 = <&gpu_opp_table>; 193 resets = <&cru SRST_GPU>; 194 power-domains = <&power RK3128_PD_GPU>; 195 status = "disabled"; 196 }; 197 198 pmu: syscon@100a0000 { 199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 200 reg = <0x100a0000 0x1000>; 201 202 power: power-controller { 203 compatible = "rockchip,rk3128-power-controller"; 204 #power-domain-cells = <1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 power-domain@RK3128_PD_VIO { 209 reg = <RK3128_PD_VIO>; 210 clocks = <&cru ACLK_CIF>, 211 <&cru HCLK_CIF>, 212 <&cru DCLK_EBC>, 213 <&cru HCLK_EBC>, 214 <&cru ACLK_IEP>, 215 <&cru HCLK_IEP>, 216 <&cru ACLK_LCDC0>, 217 <&cru HCLK_LCDC0>, 218 <&cru PCLK_MIPI>, 219 <&cru PCLK_MIPIPHY>, 220 <&cru SCLK_MIPI_24M>, 221 <&cru ACLK_RGA>, 222 <&cru HCLK_RGA>, 223 <&cru ACLK_VIO0>, 224 <&cru ACLK_VIO1>, 225 <&cru HCLK_VIO>, 226 <&cru HCLK_VIO_H2P>, 227 <&cru DCLK_VOP>, 228 <&cru SCLK_VOP>; 229 pm_qos = <&qos_ebc>, 230 <&qos_iep>, 231 <&qos_lcdc>, 232 <&qos_rga>, 233 <&qos_vip>; 234 #power-domain-cells = <0>; 235 }; 236 237 power-domain@RK3128_PD_VIDEO { 238 reg = <RK3128_PD_VIDEO>; 239 clocks = <&cru ACLK_VDPU>, 240 <&cru HCLK_VDPU>, 241 <&cru ACLK_VEPU>, 242 <&cru HCLK_VEPU>, 243 <&cru SCLK_HEVC_CORE>; 244 pm_qos = <&qos_vpu>; 245 #power-domain-cells = <0>; 246 }; 247 248 power-domain@RK3128_PD_GPU { 249 reg = <RK3128_PD_GPU>; 250 clocks = <&cru ACLK_GPU>; 251 pm_qos = <&qos_gpu>; 252 #power-domain-cells = <0>; 253 }; 254 }; 255 }; 256 257 vop: vop@1010e000 { 258 compatible = "rockchip,rk3126-vop"; 259 reg = <0x1010e000 0x300>; 260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, 262 <&cru HCLK_LCDC0>; 263 clock-names = "aclk_vop", "dclk_vop", 264 "hclk_vop"; 265 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, 266 <&cru SRST_VOP_D>; 267 reset-names = "axi", "ahb", 268 "dclk"; 269 power-domains = <&power RK3128_PD_VIO>; 270 status = "disabled"; 271 272 vop_out: port { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 vop_out_hdmi: endpoint@0 { 277 reg = <0>; 278 remote-endpoint = <&hdmi_in_vop>; 279 }; 280 281 vop_out_dsi: endpoint@1 { 282 reg = <1>; 283 remote-endpoint = <&dsi_in_vop>; 284 }; 285 }; 286 }; 287 288 dsi: dsi@10110000 { 289 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; 290 reg = <0x10110000 0x4000>; 291 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru PCLK_MIPI>; 293 clock-names = "pclk"; 294 phys = <&dphy>; 295 phy-names = "dphy"; 296 power-domains = <&power RK3128_PD_VIO>; 297 resets = <&cru SRST_VIO_MIPI_DSI>; 298 reset-names = "apb"; 299 rockchip,grf = <&grf>; 300 status = "disabled"; 301 302 ports { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 306 dsi_in: port@0 { 307 reg = <0>; 308 309 dsi_in_vop: endpoint { 310 remote-endpoint = <&vop_out_dsi>; 311 }; 312 }; 313 314 dsi_out: port@1 { 315 reg = <1>; 316 }; 317 }; 318 }; 319 320 qos_gpu: qos@1012d000 { 321 compatible = "rockchip,rk3128-qos", "syscon"; 322 reg = <0x1012d000 0x20>; 323 }; 324 325 qos_vpu: qos@1012e000 { 326 compatible = "rockchip,rk3128-qos", "syscon"; 327 reg = <0x1012e000 0x20>; 328 }; 329 330 qos_rga: qos@1012f000 { 331 compatible = "rockchip,rk3128-qos", "syscon"; 332 reg = <0x1012f000 0x20>; 333 }; 334 335 qos_ebc: qos@1012f080 { 336 compatible = "rockchip,rk3128-qos", "syscon"; 337 reg = <0x1012f080 0x20>; 338 }; 339 340 qos_iep: qos@1012f100 { 341 compatible = "rockchip,rk3128-qos", "syscon"; 342 reg = <0x1012f100 0x20>; 343 }; 344 345 qos_lcdc: qos@1012f180 { 346 compatible = "rockchip,rk3128-qos", "syscon"; 347 reg = <0x1012f180 0x20>; 348 }; 349 350 qos_vip: qos@1012f200 { 351 compatible = "rockchip,rk3128-qos", "syscon"; 352 reg = <0x1012f200 0x20>; 353 }; 354 355 gic: interrupt-controller@10139000 { 356 compatible = "arm,cortex-a7-gic"; 357 reg = <0x10139000 0x1000>, 358 <0x1013a000 0x1000>, 359 <0x1013c000 0x2000>, 360 <0x1013e000 0x2000>; 361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 362 interrupt-controller; 363 #interrupt-cells = <3>; 364 #address-cells = <0>; 365 }; 366 367 usb_otg: usb@10180000 { 368 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 369 reg = <0x10180000 0x40000>; 370 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&cru HCLK_OTG>; 372 clock-names = "otg"; 373 dr_mode = "otg"; 374 g-np-tx-fifo-size = <16>; 375 g-rx-fifo-size = <280>; 376 g-tx-fifo-size = <256 128 128 64 32 16>; 377 phys = <&usb2phy_otg>; 378 phy-names = "usb2-phy"; 379 status = "disabled"; 380 }; 381 382 usb_host_ehci: usb@101c0000 { 383 compatible = "generic-ehci"; 384 reg = <0x101c0000 0x20000>; 385 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cru HCLK_HOST2>; 387 phys = <&usb2phy_host>; 388 phy-names = "usb"; 389 status = "disabled"; 390 }; 391 392 usb_host_ohci: usb@101e0000 { 393 compatible = "generic-ohci"; 394 reg = <0x101e0000 0x20000>; 395 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&cru HCLK_HOST2>; 397 phys = <&usb2phy_host>; 398 phy-names = "usb"; 399 status = "disabled"; 400 }; 401 402 sdmmc: mmc@10214000 { 403 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 404 reg = <0x10214000 0x4000>; 405 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 407 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 408 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 409 dmas = <&pdma 10>; 410 dma-names = "rx-tx"; 411 fifo-depth = <256>; 412 max-frequency = <150000000>; 413 resets = <&cru SRST_SDMMC>; 414 reset-names = "reset"; 415 status = "disabled"; 416 }; 417 418 sdio: mmc@10218000 { 419 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 420 reg = <0x10218000 0x4000>; 421 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 423 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 424 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 425 dmas = <&pdma 11>; 426 dma-names = "rx-tx"; 427 fifo-depth = <256>; 428 max-frequency = <150000000>; 429 resets = <&cru SRST_SDIO>; 430 reset-names = "reset"; 431 status = "disabled"; 432 }; 433 434 emmc: mmc@1021c000 { 435 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 436 reg = <0x1021c000 0x4000>; 437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 439 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 440 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 441 dmas = <&pdma 12>; 442 dma-names = "rx-tx"; 443 fifo-depth = <256>; 444 max-frequency = <150000000>; 445 resets = <&cru SRST_EMMC>; 446 reset-names = "reset"; 447 status = "disabled"; 448 }; 449 450 nfc: nand-controller@10500000 { 451 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 452 reg = <0x10500000 0x4000>; 453 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 455 clock-names = "ahb", "nfc"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 458 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 459 status = "disabled"; 460 }; 461 462 cru: clock-controller@20000000 { 463 compatible = "rockchip,rk3128-cru"; 464 reg = <0x20000000 0x1000>; 465 clocks = <&xin24m>; 466 clock-names = "xin24m"; 467 rockchip,grf = <&grf>; 468 #clock-cells = <1>; 469 #reset-cells = <1>; 470 assigned-clocks = <&cru PLL_GPLL>; 471 assigned-clock-rates = <594000000>; 472 }; 473 474 grf: syscon@20008000 { 475 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 476 reg = <0x20008000 0x1000>; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 480 usb2phy: usb2phy@17c { 481 compatible = "rockchip,rk3128-usb2phy"; 482 reg = <0x017c 0x0c>; 483 clocks = <&cru SCLK_OTGPHY0>; 484 clock-names = "phyclk"; 485 clock-output-names = "usb480m_phy"; 486 assigned-clocks = <&cru SCLK_USB480M>; 487 assigned-clock-parents = <&usb2phy>; 488 #clock-cells = <0>; 489 status = "disabled"; 490 491 usb2phy_host: host-port { 492 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-names = "linestate"; 494 #phy-cells = <0>; 495 status = "disabled"; 496 }; 497 498 usb2phy_otg: otg-port { 499 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "otg-bvalid", "otg-id", 503 "linestate"; 504 #phy-cells = <0>; 505 status = "disabled"; 506 }; 507 }; 508 }; 509 510 hdmi: hdmi@20034000 { 511 compatible = "rockchip,rk3128-inno-hdmi"; 512 reg = <0x20034000 0x4000>; 513 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; 515 clock-names = "pclk", "ref"; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 518 power-domains = <&power RK3128_PD_VIO>; 519 status = "disabled"; 520 521 ports { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 525 hdmi_in: port@0 { 526 reg = <0>; 527 hdmi_in_vop: endpoint { 528 remote-endpoint = <&vop_out_hdmi>; 529 }; 530 }; 531 532 hdmi_out: port@1 { 533 reg = <1>; 534 }; 535 }; 536 }; 537 538 dphy: phy@20038000 { 539 compatible = "rockchip,rk3128-dsi-dphy"; 540 reg = <0x20038000 0x4000>; 541 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; 542 clock-names = "ref", "pclk"; 543 #phy-cells = <0>; 544 power-domains = <&power RK3128_PD_VIO>; 545 resets = <&cru SRST_MIPIPHY_P>; 546 reset-names = "apb"; 547 status = "disabled"; 548 }; 549 550 timer0: timer@20044000 { 551 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 552 reg = <0x20044000 0x20>; 553 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 555 clock-names = "pclk", "timer"; 556 }; 557 558 timer1: timer@20044020 { 559 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 560 reg = <0x20044020 0x20>; 561 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 563 clock-names = "pclk", "timer"; 564 }; 565 566 timer2: timer@20044040 { 567 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 568 reg = <0x20044040 0x20>; 569 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 571 clock-names = "pclk", "timer"; 572 }; 573 574 timer3: timer@20044060 { 575 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 576 reg = <0x20044060 0x20>; 577 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 579 clock-names = "pclk", "timer"; 580 }; 581 582 timer4: timer@20044080 { 583 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 584 reg = <0x20044080 0x20>; 585 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 587 clock-names = "pclk", "timer"; 588 }; 589 590 timer5: timer@200440a0 { 591 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 592 reg = <0x200440a0 0x20>; 593 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 595 clock-names = "pclk", "timer"; 596 }; 597 598 watchdog: watchdog@2004c000 { 599 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 600 reg = <0x2004c000 0x100>; 601 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cru PCLK_WDT>; 603 status = "disabled"; 604 }; 605 606 pwm0: pwm@20050000 { 607 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 608 reg = <0x20050000 0x10>; 609 clocks = <&cru PCLK_PWM>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pwm0_pin>; 612 #pwm-cells = <3>; 613 status = "disabled"; 614 }; 615 616 pwm1: pwm@20050010 { 617 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 618 reg = <0x20050010 0x10>; 619 clocks = <&cru PCLK_PWM>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&pwm1_pin>; 622 #pwm-cells = <3>; 623 status = "disabled"; 624 }; 625 626 pwm2: pwm@20050020 { 627 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 628 reg = <0x20050020 0x10>; 629 clocks = <&cru PCLK_PWM>; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pwm2_pin>; 632 #pwm-cells = <3>; 633 status = "disabled"; 634 }; 635 636 pwm3: pwm@20050030 { 637 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 638 reg = <0x20050030 0x10>; 639 clocks = <&cru PCLK_PWM>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&pwm3_pin>; 642 #pwm-cells = <3>; 643 status = "disabled"; 644 }; 645 646 i2c1: i2c@20056000 { 647 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 648 reg = <0x20056000 0x1000>; 649 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 650 clock-names = "i2c"; 651 clocks = <&cru PCLK_I2C1>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&i2c1_xfer>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 status = "disabled"; 657 }; 658 659 i2c2: i2c@2005a000 { 660 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 661 reg = <0x2005a000 0x1000>; 662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 663 clock-names = "i2c"; 664 clocks = <&cru PCLK_I2C2>; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&i2c2_xfer>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 status = "disabled"; 670 }; 671 672 i2c3: i2c@2005e000 { 673 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 674 reg = <0x2005e000 0x1000>; 675 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 676 clock-names = "i2c"; 677 clocks = <&cru PCLK_I2C3>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&i2c3_xfer>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "disabled"; 683 }; 684 685 uart0: serial@20060000 { 686 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 687 reg = <0x20060000 0x100>; 688 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 689 clock-frequency = <24000000>; 690 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 691 clock-names = "baudclk", "apb_pclk"; 692 dmas = <&pdma 2>, <&pdma 3>; 693 dma-names = "tx", "rx"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 696 reg-io-width = <4>; 697 reg-shift = <2>; 698 status = "disabled"; 699 }; 700 701 uart1: serial@20064000 { 702 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 703 reg = <0x20064000 0x100>; 704 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 705 clock-frequency = <24000000>; 706 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 707 clock-names = "baudclk", "apb_pclk"; 708 dmas = <&pdma 4>, <&pdma 5>; 709 dma-names = "tx", "rx"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&uart1_xfer>; 712 reg-io-width = <4>; 713 reg-shift = <2>; 714 status = "disabled"; 715 }; 716 717 uart2: serial@20068000 { 718 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 719 reg = <0x20068000 0x100>; 720 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 721 clock-frequency = <24000000>; 722 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 723 clock-names = "baudclk", "apb_pclk"; 724 dmas = <&pdma 6>, <&pdma 7>; 725 dma-names = "tx", "rx"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&uart2_xfer>; 728 reg-io-width = <4>; 729 reg-shift = <2>; 730 status = "disabled"; 731 }; 732 733 saradc: saradc@2006c000 { 734 compatible = "rockchip,saradc"; 735 reg = <0x2006c000 0x100>; 736 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 738 clock-names = "saradc", "apb_pclk"; 739 resets = <&cru SRST_SARADC>; 740 reset-names = "saradc-apb"; 741 #io-channel-cells = <1>; 742 status = "disabled"; 743 }; 744 745 i2c0: i2c@20072000 { 746 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 747 reg = <0x20072000 0x1000>; 748 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 749 clock-names = "i2c"; 750 clocks = <&cru PCLK_I2C0>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&i2c0_xfer>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 spi0: spi@20074000 { 759 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 760 reg = <0x20074000 0x1000>; 761 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 763 clock-names = "spiclk", "apb_pclk"; 764 dmas = <&pdma 8>, <&pdma 9>; 765 dma-names = "tx", "rx"; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 773 pdma: dma-controller@20078000 { 774 compatible = "arm,pl330", "arm,primecell"; 775 reg = <0x20078000 0x4000>; 776 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 778 arm,pl330-broken-no-flushp; 779 arm,pl330-periph-burst; 780 clocks = <&cru ACLK_DMAC>; 781 clock-names = "apb_pclk"; 782 #dma-cells = <1>; 783 }; 784 785 gmac: ethernet@2008c000 { 786 compatible = "rockchip,rk3128-gmac"; 787 reg = <0x2008c000 0x4000>; 788 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 790 interrupt-names = "macirq", "eth_wake_irq"; 791 clocks = <&cru SCLK_MAC>, 792 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 793 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 794 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 795 clock-names = "stmmaceth", 796 "mac_clk_rx", "mac_clk_tx", 797 "clk_mac_ref", "clk_mac_refout", 798 "aclk_mac", "pclk_mac"; 799 resets = <&cru SRST_GMAC>; 800 reset-names = "stmmaceth"; 801 rockchip,grf = <&grf>; 802 rx-fifo-depth = <4096>; 803 tx-fifo-depth = <2048>; 804 status = "disabled"; 805 806 mdio: mdio { 807 compatible = "snps,dwmac-mdio"; 808 #address-cells = <0x1>; 809 #size-cells = <0x0>; 810 }; 811 }; 812 813 pinctrl: pinctrl { 814 compatible = "rockchip,rk3128-pinctrl"; 815 rockchip,grf = <&grf>; 816 #address-cells = <1>; 817 #size-cells = <1>; 818 ranges; 819 820 gpio0: gpio@2007c000 { 821 compatible = "rockchip,gpio-bank"; 822 reg = <0x2007c000 0x100>; 823 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cru PCLK_GPIO0>; 825 gpio-controller; 826 #gpio-cells = <2>; 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 }; 830 831 gpio1: gpio@20080000 { 832 compatible = "rockchip,gpio-bank"; 833 reg = <0x20080000 0x100>; 834 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cru PCLK_GPIO1>; 836 gpio-controller; 837 #gpio-cells = <2>; 838 interrupt-controller; 839 #interrupt-cells = <2>; 840 }; 841 842 gpio2: gpio@20084000 { 843 compatible = "rockchip,gpio-bank"; 844 reg = <0x20084000 0x100>; 845 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&cru PCLK_GPIO2>; 847 gpio-controller; 848 #gpio-cells = <2>; 849 interrupt-controller; 850 #interrupt-cells = <2>; 851 }; 852 853 gpio3: gpio@20088000 { 854 compatible = "rockchip,gpio-bank"; 855 reg = <0x20088000 0x100>; 856 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cru PCLK_GPIO3>; 858 gpio-controller; 859 #gpio-cells = <2>; 860 interrupt-controller; 861 #interrupt-cells = <2>; 862 }; 863 864 pcfg_pull_default: pcfg-pull-default { 865 bias-pull-pin-default; 866 }; 867 868 pcfg_pull_none: pcfg-pull-none { 869 bias-disable; 870 }; 871 872 emmc { 873 emmc_clk: emmc-clk { 874 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 875 }; 876 877 emmc_cmd: emmc-cmd { 878 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 879 }; 880 881 emmc_cmd1: emmc-cmd1 { 882 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 883 }; 884 885 emmc_pwr: emmc-pwr { 886 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 887 }; 888 889 emmc_bus1: emmc-bus1 { 890 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 891 }; 892 893 emmc_bus4: emmc-bus4 { 894 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 895 <1 RK_PD1 2 &pcfg_pull_default>, 896 <1 RK_PD2 2 &pcfg_pull_default>, 897 <1 RK_PD3 2 &pcfg_pull_default>; 898 }; 899 900 emmc_bus8: emmc-bus8 { 901 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 902 <1 RK_PD1 2 &pcfg_pull_default>, 903 <1 RK_PD2 2 &pcfg_pull_default>, 904 <1 RK_PD3 2 &pcfg_pull_default>, 905 <1 RK_PD4 2 &pcfg_pull_default>, 906 <1 RK_PD5 2 &pcfg_pull_default>, 907 <1 RK_PD6 2 &pcfg_pull_default>, 908 <1 RK_PD7 2 &pcfg_pull_default>; 909 }; 910 }; 911 912 gmac { 913 rgmii_pins: rgmii-pins { 914 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 915 <2 RK_PB1 3 &pcfg_pull_default>, 916 <2 RK_PB3 3 &pcfg_pull_default>, 917 <2 RK_PB4 3 &pcfg_pull_default>, 918 <2 RK_PB5 3 &pcfg_pull_default>, 919 <2 RK_PB6 3 &pcfg_pull_default>, 920 <2 RK_PC0 3 &pcfg_pull_default>, 921 <2 RK_PC1 3 &pcfg_pull_default>, 922 <2 RK_PC2 3 &pcfg_pull_default>, 923 <2 RK_PC3 3 &pcfg_pull_default>, 924 <2 RK_PD1 3 &pcfg_pull_default>, 925 <2 RK_PC4 4 &pcfg_pull_default>, 926 <2 RK_PC5 4 &pcfg_pull_default>, 927 <2 RK_PC6 4 &pcfg_pull_default>, 928 <2 RK_PC7 4 &pcfg_pull_default>; 929 }; 930 931 rmii_pins: rmii-pins { 932 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 933 <2 RK_PB4 3 &pcfg_pull_default>, 934 <2 RK_PB5 3 &pcfg_pull_default>, 935 <2 RK_PB6 3 &pcfg_pull_default>, 936 <2 RK_PB7 3 &pcfg_pull_default>, 937 <2 RK_PC0 3 &pcfg_pull_default>, 938 <2 RK_PC1 3 &pcfg_pull_default>, 939 <2 RK_PC2 3 &pcfg_pull_default>, 940 <2 RK_PC3 3 &pcfg_pull_default>, 941 <2 RK_PD1 3 &pcfg_pull_default>; 942 }; 943 }; 944 945 hdmi { 946 hdmii2c_xfer: hdmii2c-xfer { 947 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 948 <0 RK_PA7 2 &pcfg_pull_none>; 949 }; 950 951 hdmi_hpd: hdmi-hpd { 952 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 953 }; 954 955 hdmi_cec: hdmi-cec { 956 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 957 }; 958 }; 959 960 i2c0 { 961 i2c0_xfer: i2c0-xfer { 962 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 963 <0 RK_PA1 1 &pcfg_pull_none>; 964 }; 965 }; 966 967 i2c1 { 968 i2c1_xfer: i2c1-xfer { 969 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 970 <0 RK_PA3 1 &pcfg_pull_none>; 971 }; 972 }; 973 974 i2c2 { 975 i2c2_xfer: i2c2-xfer { 976 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 977 <2 RK_PC5 3 &pcfg_pull_none>; 978 }; 979 }; 980 981 i2c3 { 982 i2c3_xfer: i2c3-xfer { 983 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 984 <0 RK_PA7 1 &pcfg_pull_none>; 985 }; 986 }; 987 988 i2s { 989 i2s_bus: i2s-bus { 990 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 991 <0 RK_PB1 1 &pcfg_pull_none>, 992 <0 RK_PB3 1 &pcfg_pull_none>, 993 <0 RK_PB4 1 &pcfg_pull_none>, 994 <0 RK_PB5 1 &pcfg_pull_none>, 995 <0 RK_PB6 1 &pcfg_pull_none>; 996 }; 997 998 i2s1_bus: i2s1-bus { 999 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 1000 <1 RK_PA1 1 &pcfg_pull_none>, 1001 <1 RK_PA2 1 &pcfg_pull_none>, 1002 <1 RK_PA3 1 &pcfg_pull_none>, 1003 <1 RK_PA4 1 &pcfg_pull_none>, 1004 <1 RK_PA5 1 &pcfg_pull_none>; 1005 }; 1006 }; 1007 1008 lcdc { 1009 lcdc_dclk: lcdc-dclk { 1010 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 1011 }; 1012 1013 lcdc_den: lcdc-den { 1014 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 1015 }; 1016 1017 lcdc_hsync: lcdc-hsync { 1018 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1019 }; 1020 1021 lcdc_vsync: lcdc-vsync { 1022 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 1023 }; 1024 1025 lcdc_rgb24: lcdc-rgb24 { 1026 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 1027 <2 RK_PB5 1 &pcfg_pull_none>, 1028 <2 RK_PB6 1 &pcfg_pull_none>, 1029 <2 RK_PB7 1 &pcfg_pull_none>, 1030 <2 RK_PC0 1 &pcfg_pull_none>, 1031 <2 RK_PC1 1 &pcfg_pull_none>, 1032 <2 RK_PC2 1 &pcfg_pull_none>, 1033 <2 RK_PC3 1 &pcfg_pull_none>, 1034 <2 RK_PC4 1 &pcfg_pull_none>, 1035 <2 RK_PC5 1 &pcfg_pull_none>, 1036 <2 RK_PC6 1 &pcfg_pull_none>, 1037 <2 RK_PC7 1 &pcfg_pull_none>, 1038 <2 RK_PD0 1 &pcfg_pull_none>, 1039 <2 RK_PD1 1 &pcfg_pull_none>; 1040 }; 1041 }; 1042 1043 nfc { 1044 flash_ale: flash-ale { 1045 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 1046 }; 1047 1048 flash_cle: flash-cle { 1049 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 1050 }; 1051 1052 flash_wrn: flash-wrn { 1053 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1054 }; 1055 1056 flash_rdn: flash-rdn { 1057 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 1058 }; 1059 1060 flash_rdy: flash-rdy { 1061 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1062 }; 1063 1064 flash_cs0: flash-cs0 { 1065 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1066 }; 1067 1068 flash_dqs: flash-dqs { 1069 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 1070 }; 1071 1072 flash_bus8: flash-bus8 { 1073 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1074 <1 RK_PD1 1 &pcfg_pull_none>, 1075 <1 RK_PD2 1 &pcfg_pull_none>, 1076 <1 RK_PD3 1 &pcfg_pull_none>, 1077 <1 RK_PD4 1 &pcfg_pull_none>, 1078 <1 RK_PD5 1 &pcfg_pull_none>, 1079 <1 RK_PD6 1 &pcfg_pull_none>, 1080 <1 RK_PD7 1 &pcfg_pull_none>; 1081 }; 1082 }; 1083 1084 pwm0 { 1085 pwm0_pin: pwm0-pin { 1086 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 1087 }; 1088 }; 1089 1090 pwm1 { 1091 pwm1_pin: pwm1-pin { 1092 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1093 }; 1094 }; 1095 1096 pwm2 { 1097 pwm2_pin: pwm2-pin { 1098 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1099 }; 1100 }; 1101 1102 pwm3 { 1103 pwm3_pin: pwm3-pin { 1104 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 1105 }; 1106 }; 1107 1108 sdio { 1109 sdio_clk: sdio-clk { 1110 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1111 }; 1112 1113 sdio_cmd: sdio-cmd { 1114 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1115 }; 1116 1117 sdio_pwren: sdio-pwren { 1118 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1119 }; 1120 1121 sdio_bus4: sdio-bus4 { 1122 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1123 <1 RK_PA2 2 &pcfg_pull_default>, 1124 <1 RK_PA4 2 &pcfg_pull_default>, 1125 <1 RK_PA5 2 &pcfg_pull_default>; 1126 }; 1127 }; 1128 1129 sdmmc { 1130 sdmmc_clk: sdmmc-clk { 1131 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1132 }; 1133 1134 sdmmc_cmd: sdmmc-cmd { 1135 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1136 }; 1137 1138 sdmmc_det: sdmmc-det { 1139 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1140 }; 1141 1142 sdmmc_wp: sdmmc-wp { 1143 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1144 }; 1145 1146 sdmmc_pwren: sdmmc-pwren { 1147 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 1148 }; 1149 1150 sdmmc_bus4: sdmmc-bus4 { 1151 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1152 <1 RK_PC3 1 &pcfg_pull_default>, 1153 <1 RK_PC4 1 &pcfg_pull_default>, 1154 <1 RK_PC5 1 &pcfg_pull_default>; 1155 }; 1156 }; 1157 1158 spdif { 1159 spdif_tx: spdif-tx { 1160 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1161 }; 1162 }; 1163 1164 spi0 { 1165 spi0_clk: spi0-clk { 1166 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1167 }; 1168 1169 spi0_cs0: spi0-cs0 { 1170 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1171 }; 1172 1173 spi0_tx: spi0-tx { 1174 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1175 }; 1176 1177 spi0_rx: spi0-rx { 1178 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1179 }; 1180 1181 spi0_cs1: spi0-cs1 { 1182 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1183 }; 1184 1185 spi1_clk: spi1-clk { 1186 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1187 }; 1188 1189 spi1_cs0: spi1-cs0 { 1190 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1191 }; 1192 1193 spi1_tx: spi1-tx { 1194 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1195 }; 1196 1197 spi1_rx: spi1-rx { 1198 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1199 }; 1200 1201 spi1_cs1: spi1-cs1 { 1202 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1203 }; 1204 1205 spi2_clk: spi2-clk { 1206 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1207 }; 1208 1209 spi2_cs0: spi2-cs0 { 1210 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1211 }; 1212 1213 spi2_tx: spi2-tx { 1214 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1215 }; 1216 1217 spi2_rx: spi2-rx { 1218 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1219 }; 1220 }; 1221 1222 uart0 { 1223 uart0_xfer: uart0-xfer { 1224 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1225 <2 RK_PD3 2 &pcfg_pull_none>; 1226 }; 1227 1228 uart0_cts: uart0-cts { 1229 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1230 }; 1231 1232 uart0_rts: uart0-rts { 1233 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1234 }; 1235 }; 1236 1237 uart1 { 1238 uart1_xfer: uart1-xfer { 1239 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1240 <1 RK_PB2 2 &pcfg_pull_default>; 1241 }; 1242 1243 uart1_cts: uart1-cts { 1244 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1245 }; 1246 1247 uart1_rts: uart1-rts { 1248 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1249 }; 1250 }; 1251 1252 uart2 { 1253 uart2_xfer: uart2-xfer { 1254 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1255 <1 RK_PC3 2 &pcfg_pull_none>; 1256 }; 1257 1258 uart2_cts: uart2-cts { 1259 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1260 }; 1261 1262 uart2_rts: uart2-rts { 1263 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1264 }; 1265 }; 1266 }; 1267}; 1268