1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@f00 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0xf00>; 35 clock-latency = <40000>; 36 clocks = <&cru ARMCLK>; 37 resets = <&cru SRST_CORE0>; 38 operating-points = < 39 /* KHz uV */ 40 816000 1000000 41 >; 42 #cooling-cells = <2>; /* min followed by max */ 43 }; 44 45 cpu1: cpu@f01 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a7"; 48 reg = <0xf01>; 49 resets = <&cru SRST_CORE1>; 50 }; 51 52 cpu2: cpu@f02 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0xf02>; 56 resets = <&cru SRST_CORE2>; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 }; 65 }; 66 67 timer { 68 compatible = "arm,armv7-timer"; 69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 70 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 71 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72 arm,cpu-registers-not-fw-configured; 73 clock-frequency = <24000000>; 74 }; 75 76 xin24m: oscillator { 77 compatible = "fixed-clock"; 78 clock-frequency = <24000000>; 79 clock-output-names = "xin24m"; 80 #clock-cells = <0>; 81 }; 82 83 imem: sram@10080000 { 84 compatible = "mmio-sram"; 85 reg = <0x10080000 0x2000>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges = <0 0x10080000 0x2000>; 89 }; 90 91 pmu: syscon@100a0000 { 92 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 93 reg = <0x100a0000 0x1000>; 94 }; 95 96 gic: interrupt-controller@10139000 { 97 compatible = "arm,cortex-a7-gic"; 98 reg = <0x10139000 0x1000>, 99 <0x1013a000 0x1000>, 100 <0x1013c000 0x2000>, 101 <0x1013e000 0x2000>; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 interrupt-controller; 104 #interrupt-cells = <3>; 105 #address-cells = <0>; 106 }; 107 108 usb_otg: usb@10180000 { 109 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 110 reg = <0x10180000 0x40000>; 111 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 112 clocks = <&cru HCLK_OTG>; 113 clock-names = "otg"; 114 dr_mode = "otg"; 115 phys = <&usb2phy_otg>; 116 phy-names = "usb2-phy"; 117 status = "disabled"; 118 }; 119 120 usb_host_ehci: usb@101c0000 { 121 compatible = "generic-ehci"; 122 reg = <0x101c0000 0x20000>; 123 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 124 phys = <&usb2phy_host>; 125 phy-names = "usb"; 126 status = "disabled"; 127 }; 128 129 usb_host_ohci: usb@101e0000 { 130 compatible = "generic-ohci"; 131 reg = <0x101e0000 0x20000>; 132 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 133 phys = <&usb2phy_host>; 134 phy-names = "usb"; 135 status = "disabled"; 136 }; 137 138 sdmmc: mmc@10214000 { 139 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 140 reg = <0x10214000 0x4000>; 141 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 143 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 144 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 145 dmas = <&pdma 10>; 146 dma-names = "rx-tx"; 147 fifo-depth = <256>; 148 max-frequency = <150000000>; 149 resets = <&cru SRST_SDMMC>; 150 reset-names = "reset"; 151 status = "disabled"; 152 }; 153 154 sdio: mmc@10218000 { 155 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 156 reg = <0x10218000 0x4000>; 157 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 159 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 160 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 161 dmas = <&pdma 11>; 162 dma-names = "rx-tx"; 163 fifo-depth = <256>; 164 max-frequency = <150000000>; 165 resets = <&cru SRST_SDIO>; 166 reset-names = "reset"; 167 status = "disabled"; 168 }; 169 170 emmc: mmc@1021c000 { 171 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 172 reg = <0x1021c000 0x4000>; 173 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 175 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 176 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 177 dmas = <&pdma 12>; 178 dma-names = "rx-tx"; 179 fifo-depth = <256>; 180 max-frequency = <150000000>; 181 resets = <&cru SRST_EMMC>; 182 reset-names = "reset"; 183 status = "disabled"; 184 }; 185 186 nfc: nand-controller@10500000 { 187 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 188 reg = <0x10500000 0x4000>; 189 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 191 clock-names = "ahb", "nfc"; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 194 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 195 status = "disabled"; 196 }; 197 198 cru: clock-controller@20000000 { 199 compatible = "rockchip,rk3128-cru"; 200 reg = <0x20000000 0x1000>; 201 clocks = <&xin24m>; 202 clock-names = "xin24m"; 203 rockchip,grf = <&grf>; 204 #clock-cells = <1>; 205 #reset-cells = <1>; 206 assigned-clocks = <&cru PLL_GPLL>; 207 assigned-clock-rates = <594000000>; 208 }; 209 210 grf: syscon@20008000 { 211 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 212 reg = <0x20008000 0x1000>; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 216 usb2phy: usb2phy@17c { 217 compatible = "rockchip,rk3128-usb2phy"; 218 reg = <0x017c 0x0c>; 219 clocks = <&cru SCLK_OTGPHY0>; 220 clock-names = "phyclk"; 221 clock-output-names = "usb480m_phy"; 222 #clock-cells = <0>; 223 status = "disabled"; 224 225 usb2phy_host: host-port { 226 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "linestate"; 228 #phy-cells = <0>; 229 status = "disabled"; 230 }; 231 232 usb2phy_otg: otg-port { 233 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "otg-bvalid", "otg-id", 237 "linestate"; 238 #phy-cells = <0>; 239 status = "disabled"; 240 }; 241 }; 242 }; 243 244 timer0: timer@20044000 { 245 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 246 reg = <0x20044000 0x20>; 247 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cru PCLK_TIMER>, <&xin24m>; 249 clock-names = "pclk", "timer"; 250 }; 251 252 timer1: timer@20044020 { 253 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 254 reg = <0x20044020 0x20>; 255 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cru PCLK_TIMER>, <&xin24m>; 257 clock-names = "pclk", "timer"; 258 }; 259 260 timer2: timer@20044040 { 261 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 262 reg = <0x20044040 0x20>; 263 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&cru PCLK_TIMER>, <&xin24m>; 265 clock-names = "pclk", "timer"; 266 }; 267 268 timer3: timer@20044060 { 269 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 270 reg = <0x20044060 0x20>; 271 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&cru PCLK_TIMER>, <&xin24m>; 273 clock-names = "pclk", "timer"; 274 }; 275 276 timer4: timer@20044080 { 277 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 278 reg = <0x20044080 0x20>; 279 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&cru PCLK_TIMER>, <&xin24m>; 281 clock-names = "pclk", "timer"; 282 }; 283 284 timer5: timer@200440a0 { 285 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 286 reg = <0x200440a0 0x20>; 287 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&cru PCLK_TIMER>, <&xin24m>; 289 clock-names = "pclk", "timer"; 290 }; 291 292 watchdog: watchdog@2004c000 { 293 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 294 reg = <0x2004c000 0x100>; 295 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&cru PCLK_WDT>; 297 status = "disabled"; 298 }; 299 300 pwm0: pwm@20050000 { 301 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 302 reg = <0x20050000 0x10>; 303 clocks = <&cru PCLK_PWM>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pwm0_pin>; 306 #pwm-cells = <3>; 307 status = "disabled"; 308 }; 309 310 pwm1: pwm@20050010 { 311 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 312 reg = <0x20050010 0x10>; 313 clocks = <&cru PCLK_PWM>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pwm1_pin>; 316 #pwm-cells = <3>; 317 status = "disabled"; 318 }; 319 320 pwm2: pwm@20050020 { 321 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 322 reg = <0x20050020 0x10>; 323 clocks = <&cru PCLK_PWM>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pwm2_pin>; 326 #pwm-cells = <3>; 327 status = "disabled"; 328 }; 329 330 pwm3: pwm@20050030 { 331 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 332 reg = <0x20050030 0x10>; 333 clocks = <&cru PCLK_PWM>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pwm3_pin>; 336 #pwm-cells = <3>; 337 status = "disabled"; 338 }; 339 340 i2c1: i2c@20056000 { 341 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 342 reg = <0x20056000 0x1000>; 343 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 344 clock-names = "i2c"; 345 clocks = <&cru PCLK_I2C1>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&i2c1_xfer>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 status = "disabled"; 351 }; 352 353 i2c2: i2c@2005a000 { 354 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 355 reg = <0x2005a000 0x1000>; 356 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 357 clock-names = "i2c"; 358 clocks = <&cru PCLK_I2C2>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&i2c2_xfer>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 i2c3: i2c@2005e000 { 367 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 368 reg = <0x2005e000 0x1000>; 369 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 370 clock-names = "i2c"; 371 clocks = <&cru PCLK_I2C3>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&i2c3_xfer>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 status = "disabled"; 377 }; 378 379 uart0: serial@20060000 { 380 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 381 reg = <0x20060000 0x100>; 382 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 383 clock-frequency = <24000000>; 384 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 385 clock-names = "baudclk", "apb_pclk"; 386 dmas = <&pdma 2>, <&pdma 3>; 387 dma-names = "tx", "rx"; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 390 reg-io-width = <4>; 391 reg-shift = <2>; 392 status = "disabled"; 393 }; 394 395 uart1: serial@20064000 { 396 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 397 reg = <0x20064000 0x100>; 398 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 399 clock-frequency = <24000000>; 400 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 401 clock-names = "baudclk", "apb_pclk"; 402 dmas = <&pdma 4>, <&pdma 5>; 403 dma-names = "tx", "rx"; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&uart1_xfer>; 406 reg-io-width = <4>; 407 reg-shift = <2>; 408 status = "disabled"; 409 }; 410 411 uart2: serial@20068000 { 412 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 413 reg = <0x20068000 0x100>; 414 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 415 clock-frequency = <24000000>; 416 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 417 clock-names = "baudclk", "apb_pclk"; 418 dmas = <&pdma 6>, <&pdma 7>; 419 dma-names = "tx", "rx"; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&uart2_xfer>; 422 reg-io-width = <4>; 423 reg-shift = <2>; 424 status = "disabled"; 425 }; 426 427 saradc: saradc@2006c000 { 428 compatible = "rockchip,saradc"; 429 reg = <0x2006c000 0x100>; 430 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 432 clock-names = "saradc", "apb_pclk"; 433 resets = <&cru SRST_SARADC>; 434 reset-names = "saradc-apb"; 435 #io-channel-cells = <1>; 436 status = "disabled"; 437 }; 438 439 i2c0: i2c@20072000 { 440 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 441 reg = <20072000 0x1000>; 442 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 443 clock-names = "i2c"; 444 clocks = <&cru PCLK_I2C0>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&i2c0_xfer>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 spi0: spi@20074000 { 453 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 454 reg = <0x20074000 0x1000>; 455 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 457 clock-names = "spiclk", "apb_pclk"; 458 dmas = <&pdma 8>, <&pdma 9>; 459 dma-names = "tx", "rx"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 pdma: dma-controller@20078000 { 468 compatible = "arm,pl330", "arm,primecell"; 469 reg = <0x20078000 0x4000>; 470 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 472 arm,pl330-broken-no-flushp; 473 clocks = <&cru ACLK_DMAC>; 474 clock-names = "apb_pclk"; 475 #dma-cells = <1>; 476 }; 477 478 pinctrl: pinctrl { 479 compatible = "rockchip,rk3128-pinctrl"; 480 rockchip,grf = <&grf>; 481 #address-cells = <1>; 482 #size-cells = <1>; 483 ranges; 484 485 gpio0: gpio@2007c000 { 486 compatible = "rockchip,gpio-bank"; 487 reg = <0x2007c000 0x100>; 488 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cru PCLK_GPIO0>; 490 gpio-controller; 491 #gpio-cells = <2>; 492 interrupt-controller; 493 #interrupt-cells = <2>; 494 }; 495 496 gpio1: gpio@20080000 { 497 compatible = "rockchip,gpio-bank"; 498 reg = <0x20080000 0x100>; 499 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cru PCLK_GPIO1>; 501 gpio-controller; 502 #gpio-cells = <2>; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 }; 506 507 gpio2: gpio@20084000 { 508 compatible = "rockchip,gpio-bank"; 509 reg = <0x20084000 0x100>; 510 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cru PCLK_GPIO2>; 512 gpio-controller; 513 #gpio-cells = <2>; 514 interrupt-controller; 515 #interrupt-cells = <2>; 516 }; 517 518 gpio3: gpio@20088000 { 519 compatible = "rockchip,gpio-bank"; 520 reg = <0x20088000 0x100>; 521 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cru PCLK_GPIO3>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 }; 528 529 pcfg_pull_default: pcfg-pull-default { 530 bias-pull-pin-default; 531 }; 532 533 pcfg_pull_none: pcfg-pull-none { 534 bias-disable; 535 }; 536 537 emmc { 538 emmc_clk: emmc-clk { 539 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 540 }; 541 542 emmc_cmd: emmc-cmd { 543 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 544 }; 545 546 emmc_cmd1: emmc-cmd1 { 547 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 548 }; 549 550 emmc_pwr: emmc-pwr { 551 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 552 }; 553 554 emmc_bus1: emmc-bus1 { 555 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 556 }; 557 558 emmc_bus4: emmc-bus4 { 559 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 560 <1 RK_PD1 2 &pcfg_pull_default>, 561 <1 RK_PD2 2 &pcfg_pull_default>, 562 <1 RK_PD3 2 &pcfg_pull_default>; 563 }; 564 565 emmc_bus8: emmc-bus8 { 566 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 567 <1 RK_PD1 2 &pcfg_pull_default>, 568 <1 RK_PD2 2 &pcfg_pull_default>, 569 <1 RK_PD3 2 &pcfg_pull_default>, 570 <1 RK_PD4 2 &pcfg_pull_default>, 571 <1 RK_PD5 2 &pcfg_pull_default>, 572 <1 RK_PD6 2 &pcfg_pull_default>, 573 <1 RK_PD7 2 &pcfg_pull_default>; 574 }; 575 }; 576 577 gmac { 578 rgmii_pins: rgmii-pins { 579 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 580 <2 RK_PB1 3 &pcfg_pull_default>, 581 <2 RK_PB3 3 &pcfg_pull_default>, 582 <2 RK_PB4 3 &pcfg_pull_default>, 583 <2 RK_PB5 3 &pcfg_pull_default>, 584 <2 RK_PB6 3 &pcfg_pull_default>, 585 <2 RK_PC0 3 &pcfg_pull_default>, 586 <2 RK_PC1 3 &pcfg_pull_default>, 587 <2 RK_PC2 3 &pcfg_pull_default>, 588 <2 RK_PC3 3 &pcfg_pull_default>, 589 <2 RK_PD1 3 &pcfg_pull_default>, 590 <2 RK_PC4 4 &pcfg_pull_default>, 591 <2 RK_PC5 4 &pcfg_pull_default>, 592 <2 RK_PC6 4 &pcfg_pull_default>, 593 <2 RK_PC7 4 &pcfg_pull_default>; 594 }; 595 596 rmii_pins: rmii-pins { 597 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 598 <2 RK_PB4 3 &pcfg_pull_default>, 599 <2 RK_PB5 3 &pcfg_pull_default>, 600 <2 RK_PB6 3 &pcfg_pull_default>, 601 <2 RK_PB7 3 &pcfg_pull_default>, 602 <2 RK_PC0 3 &pcfg_pull_default>, 603 <2 RK_PC1 3 &pcfg_pull_default>, 604 <2 RK_PC2 3 &pcfg_pull_default>, 605 <2 RK_PC3 3 &pcfg_pull_default>, 606 <2 RK_PD1 3 &pcfg_pull_default>; 607 }; 608 }; 609 610 hdmi { 611 hdmii2c_xfer: hdmii2c-xfer { 612 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 613 <0 RK_PA7 2 &pcfg_pull_none>; 614 }; 615 616 hdmi_hpd: hdmi-hpd { 617 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 618 }; 619 620 hdmi_cec: hdmi-cec { 621 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 622 }; 623 }; 624 625 i2c0 { 626 i2c0_xfer: i2c0-xfer { 627 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 628 <0 RK_PA1 1 &pcfg_pull_none>; 629 }; 630 }; 631 632 i2c1 { 633 i2c1_xfer: i2c1-xfer { 634 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 635 <0 RK_PA3 1 &pcfg_pull_none>; 636 }; 637 }; 638 639 i2c2 { 640 i2c2_xfer: i2c2-xfer { 641 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 642 <2 RK_PC5 3 &pcfg_pull_none>; 643 }; 644 }; 645 646 i2c3 { 647 i2c3_xfer: i2c3-xfer { 648 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 649 <0 RK_PA7 1 &pcfg_pull_none>; 650 }; 651 }; 652 653 i2s { 654 i2s_bus: i2s-bus { 655 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 656 <0 RK_PB1 1 &pcfg_pull_none>, 657 <0 RK_PB3 1 &pcfg_pull_none>, 658 <0 RK_PB4 1 &pcfg_pull_none>, 659 <0 RK_PB5 1 &pcfg_pull_none>, 660 <0 RK_PB6 1 &pcfg_pull_none>; 661 }; 662 663 i2s1_bus: i2s1-bus { 664 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 665 <1 RK_PA1 1 &pcfg_pull_none>, 666 <1 RK_PA2 1 &pcfg_pull_none>, 667 <1 RK_PA3 1 &pcfg_pull_none>, 668 <1 RK_PA4 1 &pcfg_pull_none>, 669 <1 RK_PA5 1 &pcfg_pull_none>; 670 }; 671 }; 672 673 lcdc { 674 lcdc_dclk: lcdc-dclk { 675 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 676 }; 677 678 lcdc_den: lcdc-den { 679 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 680 }; 681 682 lcdc_hsync: lcdc-hsync { 683 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 684 }; 685 686 lcdc_vsync: lcdc-vsync { 687 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 688 }; 689 690 lcdc_rgb24: lcdc-rgb24 { 691 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 692 <2 RK_PB5 1 &pcfg_pull_none>, 693 <2 RK_PB6 1 &pcfg_pull_none>, 694 <2 RK_PB7 1 &pcfg_pull_none>, 695 <2 RK_PC0 1 &pcfg_pull_none>, 696 <2 RK_PC1 1 &pcfg_pull_none>, 697 <2 RK_PC2 1 &pcfg_pull_none>, 698 <2 RK_PC3 1 &pcfg_pull_none>, 699 <2 RK_PC4 1 &pcfg_pull_none>, 700 <2 RK_PC5 1 &pcfg_pull_none>, 701 <2 RK_PC6 1 &pcfg_pull_none>, 702 <2 RK_PC7 1 &pcfg_pull_none>, 703 <2 RK_PD0 1 &pcfg_pull_none>, 704 <2 RK_PD1 1 &pcfg_pull_none>; 705 }; 706 }; 707 708 nfc { 709 flash_ale: flash-ale { 710 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 711 }; 712 713 flash_cle: flash-cle { 714 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 715 }; 716 717 flash_wrn: flash-wrn { 718 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 719 }; 720 721 flash_rdn: flash-rdn { 722 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 723 }; 724 725 flash_rdy: flash-rdy { 726 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 727 }; 728 729 flash_cs0: flash-cs0 { 730 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 731 }; 732 733 flash_dqs: flash-dqs { 734 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 735 }; 736 737 flash_bus8: flash-bus8 { 738 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 739 <1 RK_PD1 1 &pcfg_pull_none>, 740 <1 RK_PD2 1 &pcfg_pull_none>, 741 <1 RK_PD3 1 &pcfg_pull_none>, 742 <1 RK_PD4 1 &pcfg_pull_none>, 743 <1 RK_PD5 1 &pcfg_pull_none>, 744 <1 RK_PD6 1 &pcfg_pull_none>, 745 <1 RK_PD7 1 &pcfg_pull_none>; 746 }; 747 }; 748 749 pwm0 { 750 pwm0_pin: pwm0-pin { 751 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 752 }; 753 }; 754 755 pwm1 { 756 pwm1_pin: pwm1-pin { 757 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 758 }; 759 }; 760 761 pwm2 { 762 pwm2_pin: pwm2-pin { 763 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 764 }; 765 }; 766 767 pwm3 { 768 pwm3_pin: pwm3-pin { 769 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 770 }; 771 }; 772 773 sdio { 774 sdio_clk: sdio-clk { 775 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 776 }; 777 778 sdio_cmd: sdio-cmd { 779 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 780 }; 781 782 sdio_pwren: sdio-pwren { 783 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 784 }; 785 786 sdio_bus4: sdio-bus4 { 787 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 788 <1 RK_PA2 2 &pcfg_pull_default>, 789 <1 RK_PA4 2 &pcfg_pull_default>, 790 <1 RK_PA5 2 &pcfg_pull_default>; 791 }; 792 }; 793 794 sdmmc { 795 sdmmc_clk: sdmmc-clk { 796 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 797 }; 798 799 sdmmc_cmd: sdmmc-cmd { 800 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 801 }; 802 803 sdmmc_wp: sdmmc-wp { 804 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 805 }; 806 807 sdmmc_pwren: sdmmc-pwren { 808 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 809 }; 810 811 sdmmc_bus4: sdmmc-bus4 { 812 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 813 <1 RK_PC3 1 &pcfg_pull_default>, 814 <1 RK_PC4 1 &pcfg_pull_default>, 815 <1 RK_PC5 1 &pcfg_pull_default>; 816 }; 817 }; 818 819 spdif { 820 spdif_tx: spdif-tx { 821 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 822 }; 823 }; 824 825 spi0 { 826 spi0_clk: spi0-clk { 827 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 828 }; 829 830 spi0_cs0: spi0-cs0 { 831 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 832 }; 833 834 spi0_tx: spi0-tx { 835 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 836 }; 837 838 spi0_rx: spi0-rx { 839 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 840 }; 841 842 spi0_cs1: spi0-cs1 { 843 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 844 }; 845 846 spi1_clk: spi1-clk { 847 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 848 }; 849 850 spi1_cs0: spi1-cs0 { 851 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 852 }; 853 854 spi1_tx: spi1-tx { 855 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 856 }; 857 858 spi1_rx: spi1-rx { 859 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 860 }; 861 862 spi1_cs1: spi1-cs1 { 863 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 864 }; 865 866 spi2_clk: spi2-clk { 867 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 868 }; 869 870 spi2_cs0: spi2-cs0 { 871 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 872 }; 873 874 spi2_tx: spi2-tx { 875 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 876 }; 877 878 spi2_rx: spi2-rx { 879 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 880 }; 881 }; 882 883 uart0 { 884 uart0_xfer: uart0-xfer { 885 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 886 <2 RK_PD3 2 &pcfg_pull_none>; 887 }; 888 889 uart0_cts: uart0-cts { 890 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 891 }; 892 893 uart0_rts: uart0-rts { 894 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 895 }; 896 }; 897 898 uart1 { 899 uart1_xfer: uart1-xfer { 900 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 901 <1 RK_PB2 2 &pcfg_pull_default>; 902 }; 903 904 uart1_cts: uart1-cts { 905 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 906 }; 907 908 uart1_rts: uart1-rts { 909 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 910 }; 911 }; 912 913 uart2 { 914 uart2_xfer: uart2-xfer { 915 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 916 <1 RK_PC3 2 &pcfg_pull_none>; 917 }; 918 919 uart2_cts: uart2-cts { 920 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 921 }; 922 923 uart2_rts: uart2-rts { 924 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 925 }; 926 }; 927 }; 928}; 929