1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3066a-cru.h> 10#include <dt-bindings/power/rk3066-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 aliases { 17 gpio4 = &gpio4; 18 gpio6 = &gpio6; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-method = "rockchip,rk3066-smp"; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a9"; 29 next-level-cache = <&L2>; 30 reg = <0x0>; 31 operating-points = 32 /* kHz uV */ 33 <1416000 1300000>, 34 <1200000 1175000>, 35 <1008000 1125000>, 36 <816000 1125000>, 37 <600000 1100000>, 38 <504000 1100000>, 39 <312000 1075000>; 40 clock-latency = <40000>; 41 clocks = <&cru ARMCLK>; 42 }; 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a9"; 46 next-level-cache = <&L2>; 47 reg = <0x1>; 48 }; 49 }; 50 51 display-subsystem { 52 compatible = "rockchip,display-subsystem"; 53 ports = <&vop0_out>, <&vop1_out>; 54 }; 55 56 sram: sram@10080000 { 57 compatible = "mmio-sram"; 58 reg = <0x10080000 0x10000>; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges = <0 0x10080000 0x10000>; 62 63 smp-sram@0 { 64 compatible = "rockchip,rk3066-smp-sram"; 65 reg = <0x0 0x50>; 66 }; 67 }; 68 69 vop0: vop@1010c000 { 70 compatible = "rockchip,rk3066-vop"; 71 reg = <0x1010c000 0x19c>; 72 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 73 clocks = <&cru ACLK_LCDC0>, 74 <&cru DCLK_LCDC0>, 75 <&cru HCLK_LCDC0>; 76 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 77 power-domains = <&power RK3066_PD_VIO>; 78 resets = <&cru SRST_LCDC0_AXI>, 79 <&cru SRST_LCDC0_AHB>, 80 <&cru SRST_LCDC0_DCLK>; 81 reset-names = "axi", "ahb", "dclk"; 82 status = "disabled"; 83 84 vop0_out: port { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 vop0_out_hdmi: endpoint@0 { 89 reg = <0>; 90 remote-endpoint = <&hdmi_in_vop0>; 91 }; 92 }; 93 }; 94 95 vop1: vop@1010e000 { 96 compatible = "rockchip,rk3066-vop"; 97 reg = <0x1010e000 0x19c>; 98 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&cru ACLK_LCDC1>, 100 <&cru DCLK_LCDC1>, 101 <&cru HCLK_LCDC1>; 102 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 103 power-domains = <&power RK3066_PD_VIO>; 104 resets = <&cru SRST_LCDC1_AXI>, 105 <&cru SRST_LCDC1_AHB>, 106 <&cru SRST_LCDC1_DCLK>; 107 reset-names = "axi", "ahb", "dclk"; 108 status = "disabled"; 109 110 vop1_out: port { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 114 vop1_out_hdmi: endpoint@0 { 115 reg = <0>; 116 remote-endpoint = <&hdmi_in_vop1>; 117 }; 118 }; 119 }; 120 121 hdmi: hdmi@10116000 { 122 compatible = "rockchip,rk3066-hdmi"; 123 reg = <0x10116000 0x2000>; 124 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&cru HCLK_HDMI>; 126 clock-names = "hclk"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; 129 power-domains = <&power RK3066_PD_VIO>; 130 rockchip,grf = <&grf>; 131 #sound-dai-cells = <0>; 132 status = "disabled"; 133 134 ports { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 hdmi_in: port@0 { 139 reg = <0>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 hdmi_in_vop0: endpoint@0 { 144 reg = <0>; 145 remote-endpoint = <&vop0_out_hdmi>; 146 }; 147 148 hdmi_in_vop1: endpoint@1 { 149 reg = <1>; 150 remote-endpoint = <&vop1_out_hdmi>; 151 }; 152 }; 153 154 hdmi_out: port@1 { 155 reg = <1>; 156 }; 157 }; 158 }; 159 160 i2s0: i2s@10118000 { 161 compatible = "rockchip,rk3066-i2s"; 162 reg = <0x10118000 0x2000>; 163 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&i2s0_bus>; 166 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 167 clock-names = "i2s_clk", "i2s_hclk"; 168 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 169 dma-names = "tx", "rx"; 170 rockchip,playback-channels = <8>; 171 rockchip,capture-channels = <2>; 172 #sound-dai-cells = <0>; 173 status = "disabled"; 174 }; 175 176 i2s1: i2s@1011a000 { 177 compatible = "rockchip,rk3066-i2s"; 178 reg = <0x1011a000 0x2000>; 179 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&i2s1_bus>; 182 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 183 clock-names = "i2s_clk", "i2s_hclk"; 184 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 185 dma-names = "tx", "rx"; 186 rockchip,playback-channels = <2>; 187 rockchip,capture-channels = <2>; 188 #sound-dai-cells = <0>; 189 status = "disabled"; 190 }; 191 192 i2s2: i2s@1011c000 { 193 compatible = "rockchip,rk3066-i2s"; 194 reg = <0x1011c000 0x2000>; 195 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&i2s2_bus>; 198 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 199 clock-names = "i2s_clk", "i2s_hclk"; 200 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 201 dma-names = "tx", "rx"; 202 rockchip,playback-channels = <2>; 203 rockchip,capture-channels = <2>; 204 #sound-dai-cells = <0>; 205 status = "disabled"; 206 }; 207 208 cru: clock-controller@20000000 { 209 compatible = "rockchip,rk3066a-cru"; 210 reg = <0x20000000 0x1000>; 211 clocks = <&xin24m>; 212 clock-names = "xin24m"; 213 rockchip,grf = <&grf>; 214 #clock-cells = <1>; 215 #reset-cells = <1>; 216 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, 217 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 218 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 219 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 220 assigned-clock-rates = <400000000>, <594000000>, 221 <300000000>, <150000000>, 222 <75000000>, <300000000>, 223 <150000000>, <75000000>; 224 }; 225 226 timer2: timer@2000e000 { 227 compatible = "snps,dw-apb-timer"; 228 reg = <0x2000e000 0x100>; 229 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 231 clock-names = "timer", "pclk"; 232 }; 233 234 efuse: efuse@20010000 { 235 compatible = "rockchip,rk3066a-efuse"; 236 reg = <0x20010000 0x4000>; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 clocks = <&cru PCLK_EFUSE>; 240 clock-names = "pclk_efuse"; 241 242 cpu_leakage: cpu_leakage@17 { 243 reg = <0x17 0x1>; 244 }; 245 }; 246 247 timer0: timer@20038000 { 248 compatible = "snps,dw-apb-timer"; 249 reg = <0x20038000 0x100>; 250 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 252 clock-names = "timer", "pclk"; 253 }; 254 255 timer1: timer@2003a000 { 256 compatible = "snps,dw-apb-timer"; 257 reg = <0x2003a000 0x100>; 258 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 260 clock-names = "timer", "pclk"; 261 }; 262 263 tsadc: tsadc@20060000 { 264 compatible = "rockchip,rk3066-tsadc"; 265 reg = <0x20060000 0x100>; 266 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 267 clock-names = "saradc", "apb_pclk"; 268 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 269 #io-channel-cells = <1>; 270 resets = <&cru SRST_TSADC>; 271 reset-names = "saradc-apb"; 272 status = "disabled"; 273 }; 274 275 pinctrl: pinctrl { 276 compatible = "rockchip,rk3066a-pinctrl"; 277 rockchip,grf = <&grf>; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 ranges; 281 282 gpio0: gpio@20034000 { 283 compatible = "rockchip,gpio-bank"; 284 reg = <0x20034000 0x100>; 285 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cru PCLK_GPIO0>; 287 288 gpio-controller; 289 #gpio-cells = <2>; 290 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 }; 294 295 gpio1: gpio@2003c000 { 296 compatible = "rockchip,gpio-bank"; 297 reg = <0x2003c000 0x100>; 298 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&cru PCLK_GPIO1>; 300 301 gpio-controller; 302 #gpio-cells = <2>; 303 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 }; 307 308 gpio2: gpio@2003e000 { 309 compatible = "rockchip,gpio-bank"; 310 reg = <0x2003e000 0x100>; 311 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&cru PCLK_GPIO2>; 313 314 gpio-controller; 315 #gpio-cells = <2>; 316 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 }; 320 321 gpio3: gpio@20080000 { 322 compatible = "rockchip,gpio-bank"; 323 reg = <0x20080000 0x100>; 324 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cru PCLK_GPIO3>; 326 327 gpio-controller; 328 #gpio-cells = <2>; 329 330 interrupt-controller; 331 #interrupt-cells = <2>; 332 }; 333 334 gpio4: gpio@20084000 { 335 compatible = "rockchip,gpio-bank"; 336 reg = <0x20084000 0x100>; 337 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cru PCLK_GPIO4>; 339 340 gpio-controller; 341 #gpio-cells = <2>; 342 343 interrupt-controller; 344 #interrupt-cells = <2>; 345 }; 346 347 gpio6: gpio@2000a000 { 348 compatible = "rockchip,gpio-bank"; 349 reg = <0x2000a000 0x100>; 350 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cru PCLK_GPIO6>; 352 353 gpio-controller; 354 #gpio-cells = <2>; 355 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 }; 359 360 pcfg_pull_default: pcfg-pull-default { 361 bias-pull-pin-default; 362 }; 363 364 pcfg_pull_none: pcfg-pull-none { 365 bias-disable; 366 }; 367 368 emac { 369 emac_xfer: emac-xfer { 370 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ 371 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ 372 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ 373 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ 374 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ 375 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ 376 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ 377 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ 378 }; 379 380 emac_mdio: emac-mdio { 381 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ 382 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ 383 }; 384 }; 385 386 emmc { 387 emmc_clk: emmc-clk { 388 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; 389 }; 390 391 emmc_cmd: emmc-cmd { 392 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; 393 }; 394 395 emmc_rst: emmc-rst { 396 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; 397 }; 398 399 /* 400 * The data pins are shared between nandc and emmc and 401 * not accessible through pinctrl. Also they should've 402 * been already set correctly by firmware, as 403 * flash/emmc is the boot-device. 404 */ 405 }; 406 407 hdmi { 408 hdmi_hpd: hdmi-hpd { 409 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; 410 }; 411 412 hdmii2c_xfer: hdmii2c-xfer { 413 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, 414 <0 RK_PA2 1 &pcfg_pull_none>; 415 }; 416 }; 417 418 i2c0 { 419 i2c0_xfer: i2c0-xfer { 420 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, 421 <2 RK_PD5 1 &pcfg_pull_none>; 422 }; 423 }; 424 425 i2c1 { 426 i2c1_xfer: i2c1-xfer { 427 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, 428 <2 RK_PD7 1 &pcfg_pull_none>; 429 }; 430 }; 431 432 i2c2 { 433 i2c2_xfer: i2c2-xfer { 434 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, 435 <3 RK_PA1 1 &pcfg_pull_none>; 436 }; 437 }; 438 439 i2c3 { 440 i2c3_xfer: i2c3-xfer { 441 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, 442 <3 RK_PA3 2 &pcfg_pull_none>; 443 }; 444 }; 445 446 i2c4 { 447 i2c4_xfer: i2c4-xfer { 448 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 449 <3 RK_PA5 1 &pcfg_pull_none>; 450 }; 451 }; 452 453 pwm0 { 454 pwm0_out: pwm0-out { 455 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 456 }; 457 }; 458 459 pwm1 { 460 pwm1_out: pwm1-out { 461 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 462 }; 463 }; 464 465 pwm2 { 466 pwm2_out: pwm2-out { 467 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 468 }; 469 }; 470 471 pwm3 { 472 pwm3_out: pwm3-out { 473 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 474 }; 475 }; 476 477 spi0 { 478 spi0_clk: spi0-clk { 479 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; 480 }; 481 spi0_cs0: spi0-cs0 { 482 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; 483 }; 484 spi0_tx: spi0-tx { 485 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; 486 }; 487 spi0_rx: spi0-rx { 488 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; 489 }; 490 spi0_cs1: spi0-cs1 { 491 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; 492 }; 493 }; 494 495 spi1 { 496 spi1_clk: spi1-clk { 497 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; 498 }; 499 spi1_cs0: spi1-cs0 { 500 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; 501 }; 502 spi1_rx: spi1-rx { 503 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; 504 }; 505 spi1_tx: spi1-tx { 506 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; 507 }; 508 spi1_cs1: spi1-cs1 { 509 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; 510 }; 511 }; 512 513 uart0 { 514 uart0_xfer: uart0-xfer { 515 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 516 <1 RK_PA1 1 &pcfg_pull_default>; 517 }; 518 519 uart0_cts: uart0-cts { 520 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 521 }; 522 523 uart0_rts: uart0-rts { 524 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 525 }; 526 }; 527 528 uart1 { 529 uart1_xfer: uart1-xfer { 530 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, 531 <1 RK_PA5 1 &pcfg_pull_default>; 532 }; 533 534 uart1_cts: uart1-cts { 535 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; 536 }; 537 538 uart1_rts: uart1-rts { 539 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 540 }; 541 }; 542 543 uart2 { 544 uart2_xfer: uart2-xfer { 545 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 546 <1 RK_PB1 1 &pcfg_pull_default>; 547 }; 548 /* no rts / cts for uart2 */ 549 }; 550 551 uart3 { 552 uart3_xfer: uart3-xfer { 553 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, 554 <3 RK_PD4 1 &pcfg_pull_default>; 555 }; 556 557 uart3_cts: uart3-cts { 558 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; 559 }; 560 561 uart3_rts: uart3-rts { 562 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; 563 }; 564 }; 565 566 sd0 { 567 sd0_clk: sd0-clk { 568 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; 569 }; 570 571 sd0_cmd: sd0-cmd { 572 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; 573 }; 574 575 sd0_cd: sd0-cd { 576 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; 577 }; 578 579 sd0_wp: sd0-wp { 580 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; 581 }; 582 583 sd0_bus1: sd0-bus-width1 { 584 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; 585 }; 586 587 sd0_bus4: sd0-bus-width4 { 588 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, 589 <3 RK_PB3 1 &pcfg_pull_default>, 590 <3 RK_PB4 1 &pcfg_pull_default>, 591 <3 RK_PB5 1 &pcfg_pull_default>; 592 }; 593 }; 594 595 sd1 { 596 sd1_clk: sd1-clk { 597 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; 598 }; 599 600 sd1_cmd: sd1-cmd { 601 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; 602 }; 603 604 sd1_cd: sd1-cd { 605 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; 606 }; 607 608 sd1_wp: sd1-wp { 609 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; 610 }; 611 612 sd1_bus1: sd1-bus-width1 { 613 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; 614 }; 615 616 sd1_bus4: sd1-bus-width4 { 617 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, 618 <3 RK_PC2 1 &pcfg_pull_default>, 619 <3 RK_PC3 1 &pcfg_pull_default>, 620 <3 RK_PC4 1 &pcfg_pull_default>; 621 }; 622 }; 623 624 i2s0 { 625 i2s0_bus: i2s0-bus { 626 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, 627 <0 RK_PB0 1 &pcfg_pull_default>, 628 <0 RK_PB1 1 &pcfg_pull_default>, 629 <0 RK_PB2 1 &pcfg_pull_default>, 630 <0 RK_PB3 1 &pcfg_pull_default>, 631 <0 RK_PB4 1 &pcfg_pull_default>, 632 <0 RK_PB5 1 &pcfg_pull_default>, 633 <0 RK_PB6 1 &pcfg_pull_default>, 634 <0 RK_PB7 1 &pcfg_pull_default>; 635 }; 636 }; 637 638 i2s1 { 639 i2s1_bus: i2s1-bus { 640 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 641 <0 RK_PC1 1 &pcfg_pull_default>, 642 <0 RK_PC2 1 &pcfg_pull_default>, 643 <0 RK_PC3 1 &pcfg_pull_default>, 644 <0 RK_PC4 1 &pcfg_pull_default>, 645 <0 RK_PC5 1 &pcfg_pull_default>; 646 }; 647 }; 648 649 i2s2 { 650 i2s2_bus: i2s2-bus { 651 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, 652 <0 RK_PD1 1 &pcfg_pull_default>, 653 <0 RK_PD2 1 &pcfg_pull_default>, 654 <0 RK_PD3 1 &pcfg_pull_default>, 655 <0 RK_PD4 1 &pcfg_pull_default>, 656 <0 RK_PD5 1 &pcfg_pull_default>; 657 }; 658 }; 659 }; 660}; 661 662&gpu { 663 compatible = "rockchip,rk3066-mali", "arm,mali-400"; 664 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 674 interrupt-names = "gp", 675 "gpmmu", 676 "pp0", 677 "ppmmu0", 678 "pp1", 679 "ppmmu1", 680 "pp2", 681 "ppmmu2", 682 "pp3", 683 "ppmmu3"; 684 power-domains = <&power RK3066_PD_GPU>; 685}; 686 687&grf { 688 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; 689 690 usbphy: usbphy { 691 compatible = "rockchip,rk3066a-usb-phy"; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 status = "disabled"; 695 696 usbphy0: usb-phy@17c { 697 reg = <0x17c>; 698 clocks = <&cru SCLK_OTGPHY0>; 699 clock-names = "phyclk"; 700 #clock-cells = <0>; 701 #phy-cells = <0>; 702 }; 703 704 usbphy1: usb-phy@188 { 705 reg = <0x188>; 706 clocks = <&cru SCLK_OTGPHY1>; 707 clock-names = "phyclk"; 708 #clock-cells = <0>; 709 #phy-cells = <0>; 710 }; 711 }; 712}; 713 714&i2c0 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&i2c0_xfer>; 717}; 718 719&i2c1 { 720 pinctrl-names = "default"; 721 pinctrl-0 = <&i2c1_xfer>; 722}; 723 724&i2c2 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&i2c2_xfer>; 727}; 728 729&i2c3 { 730 pinctrl-names = "default"; 731 pinctrl-0 = <&i2c3_xfer>; 732}; 733 734&i2c4 { 735 pinctrl-names = "default"; 736 pinctrl-0 = <&i2c4_xfer>; 737}; 738 739&mmc0 { 740 clock-frequency = <50000000>; 741 dmas = <&dmac2 1>; 742 dma-names = "rx-tx"; 743 max-frequency = <50000000>; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 746}; 747 748&mmc1 { 749 dmas = <&dmac2 3>; 750 dma-names = "rx-tx"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 753}; 754 755&emmc { 756 dmas = <&dmac2 4>; 757 dma-names = "rx-tx"; 758}; 759 760&pmu { 761 power: power-controller { 762 compatible = "rockchip,rk3066-power-controller"; 763 #power-domain-cells = <1>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 767 power-domain@RK3066_PD_VIO { 768 reg = <RK3066_PD_VIO>; 769 clocks = <&cru ACLK_LCDC0>, 770 <&cru ACLK_LCDC1>, 771 <&cru DCLK_LCDC0>, 772 <&cru DCLK_LCDC1>, 773 <&cru HCLK_LCDC0>, 774 <&cru HCLK_LCDC1>, 775 <&cru SCLK_CIF1>, 776 <&cru ACLK_CIF1>, 777 <&cru HCLK_CIF1>, 778 <&cru SCLK_CIF0>, 779 <&cru ACLK_CIF0>, 780 <&cru HCLK_CIF0>, 781 <&cru HCLK_HDMI>, 782 <&cru ACLK_IPP>, 783 <&cru HCLK_IPP>, 784 <&cru ACLK_RGA>, 785 <&cru HCLK_RGA>; 786 pm_qos = <&qos_lcdc0>, 787 <&qos_lcdc1>, 788 <&qos_cif0>, 789 <&qos_cif1>, 790 <&qos_ipp>, 791 <&qos_rga>; 792 #power-domain-cells = <0>; 793 }; 794 795 power-domain@RK3066_PD_VIDEO { 796 reg = <RK3066_PD_VIDEO>; 797 clocks = <&cru ACLK_VDPU>, 798 <&cru ACLK_VEPU>, 799 <&cru HCLK_VDPU>, 800 <&cru HCLK_VEPU>; 801 pm_qos = <&qos_vpu>; 802 #power-domain-cells = <0>; 803 }; 804 805 power-domain@RK3066_PD_GPU { 806 reg = <RK3066_PD_GPU>; 807 clocks = <&cru ACLK_GPU>; 808 pm_qos = <&qos_gpu>; 809 #power-domain-cells = <0>; 810 }; 811 }; 812}; 813 814&pwm0 { 815 pinctrl-names = "default"; 816 pinctrl-0 = <&pwm0_out>; 817}; 818 819&pwm1 { 820 pinctrl-names = "default"; 821 pinctrl-0 = <&pwm1_out>; 822}; 823 824&pwm2 { 825 pinctrl-names = "default"; 826 pinctrl-0 = <&pwm2_out>; 827}; 828 829&pwm3 { 830 pinctrl-names = "default"; 831 pinctrl-0 = <&pwm3_out>; 832}; 833 834&spi0 { 835 pinctrl-names = "default"; 836 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 837}; 838 839&spi1 { 840 pinctrl-names = "default"; 841 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 842}; 843 844&uart0 { 845 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 846 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 847 dma-names = "tx", "rx"; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&uart0_xfer>; 850}; 851 852&uart1 { 853 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 854 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 855 dma-names = "tx", "rx"; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&uart1_xfer>; 858}; 859 860&uart2 { 861 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 862 dmas = <&dmac2 6>, <&dmac2 7>; 863 dma-names = "tx", "rx"; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&uart2_xfer>; 866}; 867 868&uart3 { 869 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 870 dmas = <&dmac2 8>, <&dmac2 9>; 871 dma-names = "tx", "rx"; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&uart3_xfer>; 874}; 875 876&vpu { 877 power-domains = <&power RK3066_PD_VIDEO>; 878}; 879 880&wdt { 881 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 882}; 883 884&emac { 885 compatible = "rockchip,rk3066-emac"; 886}; 887