1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3066a-cru.h> 10#include <dt-bindings/power/rk3066-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 aliases { 17 gpio4 = &gpio4; 18 gpio6 = &gpio6; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-method = "rockchip,rk3066-smp"; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a9"; 29 next-level-cache = <&L2>; 30 reg = <0x0>; 31 operating-points = 32 /* kHz uV */ 33 <1416000 1300000>, 34 <1200000 1175000>, 35 <1008000 1125000>, 36 <816000 1125000>, 37 <600000 1100000>, 38 <504000 1100000>, 39 <312000 1075000>; 40 clock-latency = <40000>; 41 clocks = <&cru ARMCLK>; 42 }; 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a9"; 46 next-level-cache = <&L2>; 47 reg = <0x1>; 48 }; 49 }; 50 51 display-subsystem { 52 compatible = "rockchip,display-subsystem"; 53 ports = <&vop0_out>, <&vop1_out>; 54 }; 55 56 hdmi_sound: hdmi-sound { 57 compatible = "simple-audio-card"; 58 simple-audio-card,name = "HDMI"; 59 simple-audio-card,format = "i2s"; 60 simple-audio-card,mclk-fs = <256>; 61 status = "disabled"; 62 63 simple-audio-card,codec { 64 sound-dai = <&hdmi>; 65 }; 66 67 simple-audio-card,cpu { 68 sound-dai = <&i2s0>; 69 }; 70 }; 71 72 sram: sram@10080000 { 73 compatible = "mmio-sram"; 74 reg = <0x10080000 0x10000>; 75 #address-cells = <1>; 76 #size-cells = <1>; 77 ranges = <0 0x10080000 0x10000>; 78 79 smp-sram@0 { 80 compatible = "rockchip,rk3066-smp-sram"; 81 reg = <0x0 0x50>; 82 }; 83 }; 84 85 vop0: vop@1010c000 { 86 compatible = "rockchip,rk3066-vop"; 87 reg = <0x1010c000 0x19c>; 88 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&cru ACLK_LCDC0>, 90 <&cru DCLK_LCDC0>, 91 <&cru HCLK_LCDC0>; 92 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 93 power-domains = <&power RK3066_PD_VIO>; 94 resets = <&cru SRST_LCDC0_AXI>, 95 <&cru SRST_LCDC0_AHB>, 96 <&cru SRST_LCDC0_DCLK>; 97 reset-names = "axi", "ahb", "dclk"; 98 status = "disabled"; 99 100 vop0_out: port { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 104 vop0_out_hdmi: endpoint@0 { 105 reg = <0>; 106 remote-endpoint = <&hdmi_in_vop0>; 107 }; 108 }; 109 }; 110 111 vop1: vop@1010e000 { 112 compatible = "rockchip,rk3066-vop"; 113 reg = <0x1010e000 0x19c>; 114 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&cru ACLK_LCDC1>, 116 <&cru DCLK_LCDC1>, 117 <&cru HCLK_LCDC1>; 118 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 119 power-domains = <&power RK3066_PD_VIO>; 120 resets = <&cru SRST_LCDC1_AXI>, 121 <&cru SRST_LCDC1_AHB>, 122 <&cru SRST_LCDC1_DCLK>; 123 reset-names = "axi", "ahb", "dclk"; 124 status = "disabled"; 125 126 vop1_out: port { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 130 vop1_out_hdmi: endpoint@0 { 131 reg = <0>; 132 remote-endpoint = <&hdmi_in_vop1>; 133 }; 134 }; 135 }; 136 137 hdmi: hdmi@10116000 { 138 compatible = "rockchip,rk3066-hdmi"; 139 reg = <0x10116000 0x2000>; 140 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&cru HCLK_HDMI>; 142 clock-names = "hclk"; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; 145 power-domains = <&power RK3066_PD_VIO>; 146 rockchip,grf = <&grf>; 147 status = "disabled"; 148 149 ports { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 hdmi_in: port@0 { 154 reg = <0>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 hdmi_in_vop0: endpoint@0 { 159 reg = <0>; 160 remote-endpoint = <&vop0_out_hdmi>; 161 }; 162 163 hdmi_in_vop1: endpoint@1 { 164 reg = <1>; 165 remote-endpoint = <&vop1_out_hdmi>; 166 }; 167 }; 168 169 hdmi_out: port@1 { 170 reg = <1>; 171 }; 172 }; 173 }; 174 175 i2s0: i2s@10118000 { 176 compatible = "rockchip,rk3066-i2s"; 177 reg = <0x10118000 0x2000>; 178 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&i2s0_bus>; 181 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 182 clock-names = "i2s_clk", "i2s_hclk"; 183 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 184 dma-names = "tx", "rx"; 185 rockchip,playback-channels = <8>; 186 rockchip,capture-channels = <2>; 187 #sound-dai-cells = <0>; 188 status = "disabled"; 189 }; 190 191 i2s1: i2s@1011a000 { 192 compatible = "rockchip,rk3066-i2s"; 193 reg = <0x1011a000 0x2000>; 194 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&i2s1_bus>; 197 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 198 clock-names = "i2s_clk", "i2s_hclk"; 199 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 200 dma-names = "tx", "rx"; 201 rockchip,playback-channels = <2>; 202 rockchip,capture-channels = <2>; 203 #sound-dai-cells = <0>; 204 status = "disabled"; 205 }; 206 207 i2s2: i2s@1011c000 { 208 compatible = "rockchip,rk3066-i2s"; 209 reg = <0x1011c000 0x2000>; 210 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&i2s2_bus>; 213 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 214 clock-names = "i2s_clk", "i2s_hclk"; 215 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 216 dma-names = "tx", "rx"; 217 rockchip,playback-channels = <2>; 218 rockchip,capture-channels = <2>; 219 #sound-dai-cells = <0>; 220 status = "disabled"; 221 }; 222 223 cru: clock-controller@20000000 { 224 compatible = "rockchip,rk3066a-cru"; 225 reg = <0x20000000 0x1000>; 226 clocks = <&xin24m>; 227 clock-names = "xin24m"; 228 rockchip,grf = <&grf>; 229 #clock-cells = <1>; 230 #reset-cells = <1>; 231 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, 232 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 233 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 234 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 235 assigned-clock-rates = <400000000>, <594000000>, 236 <300000000>, <150000000>, 237 <75000000>, <300000000>, 238 <150000000>, <75000000>; 239 }; 240 241 timer2: timer@2000e000 { 242 compatible = "snps,dw-apb-timer"; 243 reg = <0x2000e000 0x100>; 244 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 246 clock-names = "timer", "pclk"; 247 }; 248 249 efuse: efuse@20010000 { 250 compatible = "rockchip,rk3066a-efuse"; 251 reg = <0x20010000 0x4000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 clocks = <&cru PCLK_EFUSE>; 255 clock-names = "pclk_efuse"; 256 257 cpu_leakage: cpu_leakage@17 { 258 reg = <0x17 0x1>; 259 }; 260 }; 261 262 timer0: timer@20038000 { 263 compatible = "snps,dw-apb-timer"; 264 reg = <0x20038000 0x100>; 265 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 267 clock-names = "timer", "pclk"; 268 }; 269 270 timer1: timer@2003a000 { 271 compatible = "snps,dw-apb-timer"; 272 reg = <0x2003a000 0x100>; 273 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 275 clock-names = "timer", "pclk"; 276 }; 277 278 tsadc: tsadc@20060000 { 279 compatible = "rockchip,rk3066-tsadc"; 280 reg = <0x20060000 0x100>; 281 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 282 clock-names = "saradc", "apb_pclk"; 283 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 284 #io-channel-cells = <1>; 285 resets = <&cru SRST_TSADC>; 286 reset-names = "saradc-apb"; 287 status = "disabled"; 288 }; 289 290 pinctrl: pinctrl { 291 compatible = "rockchip,rk3066a-pinctrl"; 292 rockchip,grf = <&grf>; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 ranges; 296 297 gpio0: gpio@20034000 { 298 compatible = "rockchip,gpio-bank"; 299 reg = <0x20034000 0x100>; 300 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cru PCLK_GPIO0>; 302 303 gpio-controller; 304 #gpio-cells = <2>; 305 306 interrupt-controller; 307 #interrupt-cells = <2>; 308 }; 309 310 gpio1: gpio@2003c000 { 311 compatible = "rockchip,gpio-bank"; 312 reg = <0x2003c000 0x100>; 313 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru PCLK_GPIO1>; 315 316 gpio-controller; 317 #gpio-cells = <2>; 318 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 }; 322 323 gpio2: gpio@2003e000 { 324 compatible = "rockchip,gpio-bank"; 325 reg = <0x2003e000 0x100>; 326 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cru PCLK_GPIO2>; 328 329 gpio-controller; 330 #gpio-cells = <2>; 331 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 gpio3: gpio@20080000 { 337 compatible = "rockchip,gpio-bank"; 338 reg = <0x20080000 0x100>; 339 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cru PCLK_GPIO3>; 341 342 gpio-controller; 343 #gpio-cells = <2>; 344 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 }; 348 349 gpio4: gpio@20084000 { 350 compatible = "rockchip,gpio-bank"; 351 reg = <0x20084000 0x100>; 352 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&cru PCLK_GPIO4>; 354 355 gpio-controller; 356 #gpio-cells = <2>; 357 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 }; 361 362 gpio6: gpio@2000a000 { 363 compatible = "rockchip,gpio-bank"; 364 reg = <0x2000a000 0x100>; 365 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&cru PCLK_GPIO6>; 367 368 gpio-controller; 369 #gpio-cells = <2>; 370 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 }; 374 375 pcfg_pull_default: pcfg-pull-default { 376 bias-pull-pin-default; 377 }; 378 379 pcfg_pull_none: pcfg-pull-none { 380 bias-disable; 381 }; 382 383 emac { 384 emac_xfer: emac-xfer { 385 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ 386 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ 387 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ 388 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ 389 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ 390 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ 391 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ 392 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ 393 }; 394 395 emac_mdio: emac-mdio { 396 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ 397 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ 398 }; 399 }; 400 401 emmc { 402 emmc_clk: emmc-clk { 403 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; 404 }; 405 406 emmc_cmd: emmc-cmd { 407 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; 408 }; 409 410 emmc_rst: emmc-rst { 411 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; 412 }; 413 414 /* 415 * The data pins are shared between nandc and emmc and 416 * not accessible through pinctrl. Also they should've 417 * been already set correctly by firmware, as 418 * flash/emmc is the boot-device. 419 */ 420 }; 421 422 hdmi { 423 hdmi_hpd: hdmi-hpd { 424 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; 425 }; 426 427 hdmii2c_xfer: hdmii2c-xfer { 428 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, 429 <0 RK_PA2 1 &pcfg_pull_none>; 430 }; 431 }; 432 433 i2c0 { 434 i2c0_xfer: i2c0-xfer { 435 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, 436 <2 RK_PD5 1 &pcfg_pull_none>; 437 }; 438 }; 439 440 i2c1 { 441 i2c1_xfer: i2c1-xfer { 442 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, 443 <2 RK_PD7 1 &pcfg_pull_none>; 444 }; 445 }; 446 447 i2c2 { 448 i2c2_xfer: i2c2-xfer { 449 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, 450 <3 RK_PA1 1 &pcfg_pull_none>; 451 }; 452 }; 453 454 i2c3 { 455 i2c3_xfer: i2c3-xfer { 456 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, 457 <3 RK_PA3 2 &pcfg_pull_none>; 458 }; 459 }; 460 461 i2c4 { 462 i2c4_xfer: i2c4-xfer { 463 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 464 <3 RK_PA5 1 &pcfg_pull_none>; 465 }; 466 }; 467 468 pwm0 { 469 pwm0_out: pwm0-out { 470 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 471 }; 472 }; 473 474 pwm1 { 475 pwm1_out: pwm1-out { 476 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 477 }; 478 }; 479 480 pwm2 { 481 pwm2_out: pwm2-out { 482 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 483 }; 484 }; 485 486 pwm3 { 487 pwm3_out: pwm3-out { 488 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 489 }; 490 }; 491 492 spi0 { 493 spi0_clk: spi0-clk { 494 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; 495 }; 496 spi0_cs0: spi0-cs0 { 497 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; 498 }; 499 spi0_tx: spi0-tx { 500 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; 501 }; 502 spi0_rx: spi0-rx { 503 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; 504 }; 505 spi0_cs1: spi0-cs1 { 506 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; 507 }; 508 }; 509 510 spi1 { 511 spi1_clk: spi1-clk { 512 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; 513 }; 514 spi1_cs0: spi1-cs0 { 515 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; 516 }; 517 spi1_rx: spi1-rx { 518 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; 519 }; 520 spi1_tx: spi1-tx { 521 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; 522 }; 523 spi1_cs1: spi1-cs1 { 524 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; 525 }; 526 }; 527 528 uart0 { 529 uart0_xfer: uart0-xfer { 530 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 531 <1 RK_PA1 1 &pcfg_pull_default>; 532 }; 533 534 uart0_cts: uart0-cts { 535 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 536 }; 537 538 uart0_rts: uart0-rts { 539 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 540 }; 541 }; 542 543 uart1 { 544 uart1_xfer: uart1-xfer { 545 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, 546 <1 RK_PA5 1 &pcfg_pull_default>; 547 }; 548 549 uart1_cts: uart1-cts { 550 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; 551 }; 552 553 uart1_rts: uart1-rts { 554 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 555 }; 556 }; 557 558 uart2 { 559 uart2_xfer: uart2-xfer { 560 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 561 <1 RK_PB1 1 &pcfg_pull_default>; 562 }; 563 /* no rts / cts for uart2 */ 564 }; 565 566 uart3 { 567 uart3_xfer: uart3-xfer { 568 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, 569 <3 RK_PD4 1 &pcfg_pull_default>; 570 }; 571 572 uart3_cts: uart3-cts { 573 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; 574 }; 575 576 uart3_rts: uart3-rts { 577 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; 578 }; 579 }; 580 581 sd0 { 582 sd0_clk: sd0-clk { 583 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; 584 }; 585 586 sd0_cmd: sd0-cmd { 587 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; 588 }; 589 590 sd0_cd: sd0-cd { 591 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; 592 }; 593 594 sd0_wp: sd0-wp { 595 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; 596 }; 597 598 sd0_bus1: sd0-bus-width1 { 599 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; 600 }; 601 602 sd0_bus4: sd0-bus-width4 { 603 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, 604 <3 RK_PB3 1 &pcfg_pull_default>, 605 <3 RK_PB4 1 &pcfg_pull_default>, 606 <3 RK_PB5 1 &pcfg_pull_default>; 607 }; 608 }; 609 610 sd1 { 611 sd1_clk: sd1-clk { 612 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; 613 }; 614 615 sd1_cmd: sd1-cmd { 616 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; 617 }; 618 619 sd1_cd: sd1-cd { 620 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; 621 }; 622 623 sd1_wp: sd1-wp { 624 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; 625 }; 626 627 sd1_bus1: sd1-bus-width1 { 628 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; 629 }; 630 631 sd1_bus4: sd1-bus-width4 { 632 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, 633 <3 RK_PC2 1 &pcfg_pull_default>, 634 <3 RK_PC3 1 &pcfg_pull_default>, 635 <3 RK_PC4 1 &pcfg_pull_default>; 636 }; 637 }; 638 639 i2s0 { 640 i2s0_bus: i2s0-bus { 641 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, 642 <0 RK_PB0 1 &pcfg_pull_default>, 643 <0 RK_PB1 1 &pcfg_pull_default>, 644 <0 RK_PB2 1 &pcfg_pull_default>, 645 <0 RK_PB3 1 &pcfg_pull_default>, 646 <0 RK_PB4 1 &pcfg_pull_default>, 647 <0 RK_PB5 1 &pcfg_pull_default>, 648 <0 RK_PB6 1 &pcfg_pull_default>, 649 <0 RK_PB7 1 &pcfg_pull_default>; 650 }; 651 }; 652 653 i2s1 { 654 i2s1_bus: i2s1-bus { 655 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 656 <0 RK_PC1 1 &pcfg_pull_default>, 657 <0 RK_PC2 1 &pcfg_pull_default>, 658 <0 RK_PC3 1 &pcfg_pull_default>, 659 <0 RK_PC4 1 &pcfg_pull_default>, 660 <0 RK_PC5 1 &pcfg_pull_default>; 661 }; 662 }; 663 664 i2s2 { 665 i2s2_bus: i2s2-bus { 666 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, 667 <0 RK_PD1 1 &pcfg_pull_default>, 668 <0 RK_PD2 1 &pcfg_pull_default>, 669 <0 RK_PD3 1 &pcfg_pull_default>, 670 <0 RK_PD4 1 &pcfg_pull_default>, 671 <0 RK_PD5 1 &pcfg_pull_default>; 672 }; 673 }; 674 }; 675}; 676 677&gpu { 678 compatible = "rockchip,rk3066-mali", "arm,mali-400"; 679 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "gp", 690 "gpmmu", 691 "pp0", 692 "ppmmu0", 693 "pp1", 694 "ppmmu1", 695 "pp2", 696 "ppmmu2", 697 "pp3", 698 "ppmmu3"; 699 power-domains = <&power RK3066_PD_GPU>; 700}; 701 702&grf { 703 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; 704 705 usbphy: usbphy { 706 compatible = "rockchip,rk3066a-usb-phy"; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 status = "disabled"; 710 711 usbphy0: usb-phy@17c { 712 reg = <0x17c>; 713 clocks = <&cru SCLK_OTGPHY0>; 714 clock-names = "phyclk"; 715 #clock-cells = <0>; 716 #phy-cells = <0>; 717 }; 718 719 usbphy1: usb-phy@188 { 720 reg = <0x188>; 721 clocks = <&cru SCLK_OTGPHY1>; 722 clock-names = "phyclk"; 723 #clock-cells = <0>; 724 #phy-cells = <0>; 725 }; 726 }; 727}; 728 729&i2c0 { 730 pinctrl-names = "default"; 731 pinctrl-0 = <&i2c0_xfer>; 732}; 733 734&i2c1 { 735 pinctrl-names = "default"; 736 pinctrl-0 = <&i2c1_xfer>; 737}; 738 739&i2c2 { 740 pinctrl-names = "default"; 741 pinctrl-0 = <&i2c2_xfer>; 742}; 743 744&i2c3 { 745 pinctrl-names = "default"; 746 pinctrl-0 = <&i2c3_xfer>; 747}; 748 749&i2c4 { 750 pinctrl-names = "default"; 751 pinctrl-0 = <&i2c4_xfer>; 752}; 753 754&mmc0 { 755 clock-frequency = <50000000>; 756 dmas = <&dmac2 1>; 757 dma-names = "rx-tx"; 758 max-frequency = <50000000>; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 761}; 762 763&mmc1 { 764 dmas = <&dmac2 3>; 765 dma-names = "rx-tx"; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 768}; 769 770&emmc { 771 dmas = <&dmac2 4>; 772 dma-names = "rx-tx"; 773}; 774 775&pmu { 776 power: power-controller { 777 compatible = "rockchip,rk3066-power-controller"; 778 #power-domain-cells = <1>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 782 power-domain@RK3066_PD_VIO { 783 reg = <RK3066_PD_VIO>; 784 clocks = <&cru ACLK_LCDC0>, 785 <&cru ACLK_LCDC1>, 786 <&cru DCLK_LCDC0>, 787 <&cru DCLK_LCDC1>, 788 <&cru HCLK_LCDC0>, 789 <&cru HCLK_LCDC1>, 790 <&cru SCLK_CIF1>, 791 <&cru ACLK_CIF1>, 792 <&cru HCLK_CIF1>, 793 <&cru SCLK_CIF0>, 794 <&cru ACLK_CIF0>, 795 <&cru HCLK_CIF0>, 796 <&cru HCLK_HDMI>, 797 <&cru ACLK_IPP>, 798 <&cru HCLK_IPP>, 799 <&cru ACLK_RGA>, 800 <&cru HCLK_RGA>; 801 pm_qos = <&qos_lcdc0>, 802 <&qos_lcdc1>, 803 <&qos_cif0>, 804 <&qos_cif1>, 805 <&qos_ipp>, 806 <&qos_rga>; 807 #power-domain-cells = <0>; 808 }; 809 810 power-domain@RK3066_PD_VIDEO { 811 reg = <RK3066_PD_VIDEO>; 812 clocks = <&cru ACLK_VDPU>, 813 <&cru ACLK_VEPU>, 814 <&cru HCLK_VDPU>, 815 <&cru HCLK_VEPU>; 816 pm_qos = <&qos_vpu>; 817 #power-domain-cells = <0>; 818 }; 819 820 power-domain@RK3066_PD_GPU { 821 reg = <RK3066_PD_GPU>; 822 clocks = <&cru ACLK_GPU>; 823 pm_qos = <&qos_gpu>; 824 #power-domain-cells = <0>; 825 }; 826 }; 827}; 828 829&pwm0 { 830 pinctrl-names = "default"; 831 pinctrl-0 = <&pwm0_out>; 832}; 833 834&pwm1 { 835 pinctrl-names = "default"; 836 pinctrl-0 = <&pwm1_out>; 837}; 838 839&pwm2 { 840 pinctrl-names = "default"; 841 pinctrl-0 = <&pwm2_out>; 842}; 843 844&pwm3 { 845 pinctrl-names = "default"; 846 pinctrl-0 = <&pwm3_out>; 847}; 848 849&spi0 { 850 pinctrl-names = "default"; 851 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 852}; 853 854&spi1 { 855 pinctrl-names = "default"; 856 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 857}; 858 859&uart0 { 860 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 861 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 862 dma-names = "tx", "rx"; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&uart0_xfer>; 865}; 866 867&uart1 { 868 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 869 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 870 dma-names = "tx", "rx"; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&uart1_xfer>; 873}; 874 875&uart2 { 876 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 877 dmas = <&dmac2 6>, <&dmac2 7>; 878 dma-names = "tx", "rx"; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&uart2_xfer>; 881}; 882 883&uart3 { 884 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 885 dmas = <&dmac2 8>, <&dmac2 9>; 886 dma-names = "tx", "rx"; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&uart3_xfer>; 889}; 890 891&vpu { 892 power-domains = <&power RK3066_PD_VIDEO>; 893}; 894 895&wdt { 896 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 897}; 898 899&emac { 900 compatible = "rockchip,rk3066-emac"; 901}; 902