1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring 3*724ba675SRob Herring/dts-v1/; 4*724ba675SRob Herring 5*724ba675SRob Herring#include "rk3036.dtsi" 6*724ba675SRob Herring 7*724ba675SRob Herring/ { 8*724ba675SRob Herring model = "Rockchip RK3036 Evaluation board"; 9*724ba675SRob Herring compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; 10*724ba675SRob Herring 11*724ba675SRob Herring memory@60000000 { 12*724ba675SRob Herring device_type = "memory"; 13*724ba675SRob Herring reg = <0x60000000 0x40000000>; 14*724ba675SRob Herring }; 15*724ba675SRob Herring}; 16*724ba675SRob Herring 17*724ba675SRob Herring&emac { 18*724ba675SRob Herring phy = <&phy0>; 19*724ba675SRob Herring phy-reset-duration = <10>; /* millisecond */ 20*724ba675SRob Herring phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ 21*724ba675SRob Herring pinctrl-names = "default"; 22*724ba675SRob Herring pinctrl-0 = <&emac_xfer>, <&emac_mdio>; 23*724ba675SRob Herring status = "okay"; 24*724ba675SRob Herring 25*724ba675SRob Herring mdio { 26*724ba675SRob Herring #address-cells = <1>; 27*724ba675SRob Herring #size-cells = <0>; 28*724ba675SRob Herring 29*724ba675SRob Herring phy0: ethernet-phy@0 { 30*724ba675SRob Herring reg = <0>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring }; 33*724ba675SRob Herring}; 34*724ba675SRob Herring 35*724ba675SRob Herring&i2c1 { 36*724ba675SRob Herring status = "okay"; 37*724ba675SRob Herring 38*724ba675SRob Herring hym8563: rtc@51 { 39*724ba675SRob Herring compatible = "haoyu,hym8563"; 40*724ba675SRob Herring reg = <0x51>; 41*724ba675SRob Herring #clock-cells = <0>; 42*724ba675SRob Herring clock-output-names = "xin32k"; 43*724ba675SRob Herring }; 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&uart2 { 47*724ba675SRob Herring status = "okay"; 48*724ba675SRob Herring}; 49