1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2012 Renesas Solutions Corp. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/clock/sh73a0-clock.h> 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring compatible = "renesas,sh73a0"; 14*724ba675SRob Herring interrupt-parent = <&gic>; 15*724ba675SRob Herring #address-cells = <1>; 16*724ba675SRob Herring #size-cells = <1>; 17*724ba675SRob Herring 18*724ba675SRob Herring cpus { 19*724ba675SRob Herring #address-cells = <1>; 20*724ba675SRob Herring #size-cells = <0>; 21*724ba675SRob Herring 22*724ba675SRob Herring cpu0: cpu@0 { 23*724ba675SRob Herring device_type = "cpu"; 24*724ba675SRob Herring compatible = "arm,cortex-a9"; 25*724ba675SRob Herring reg = <0>; 26*724ba675SRob Herring clock-frequency = <1196000000>; 27*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_Z>; 28*724ba675SRob Herring power-domains = <&pd_a2sl>; 29*724ba675SRob Herring next-level-cache = <&L2>; 30*724ba675SRob Herring }; 31*724ba675SRob Herring cpu1: cpu@1 { 32*724ba675SRob Herring device_type = "cpu"; 33*724ba675SRob Herring compatible = "arm,cortex-a9"; 34*724ba675SRob Herring reg = <1>; 35*724ba675SRob Herring clock-frequency = <1196000000>; 36*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_Z>; 37*724ba675SRob Herring power-domains = <&pd_a2sl>; 38*724ba675SRob Herring next-level-cache = <&L2>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring }; 41*724ba675SRob Herring 42*724ba675SRob Herring timer@f0000200 { 43*724ba675SRob Herring compatible = "arm,cortex-a9-global-timer"; 44*724ba675SRob Herring reg = <0xf0000200 0x100>; 45*724ba675SRob Herring interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 46*724ba675SRob Herring clocks = <&periph_clk>; 47*724ba675SRob Herring }; 48*724ba675SRob Herring 49*724ba675SRob Herring timer@f0000600 { 50*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 51*724ba675SRob Herring reg = <0xf0000600 0x20>; 52*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 53*724ba675SRob Herring clocks = <&periph_clk>; 54*724ba675SRob Herring }; 55*724ba675SRob Herring 56*724ba675SRob Herring gic: interrupt-controller@f0001000 { 57*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 58*724ba675SRob Herring #interrupt-cells = <3>; 59*724ba675SRob Herring interrupt-controller; 60*724ba675SRob Herring reg = <0xf0001000 0x1000>, 61*724ba675SRob Herring <0xf0000100 0x100>; 62*724ba675SRob Herring }; 63*724ba675SRob Herring 64*724ba675SRob Herring L2: cache-controller@f0100000 { 65*724ba675SRob Herring compatible = "arm,pl310-cache"; 66*724ba675SRob Herring reg = <0xf0100000 0x1000>; 67*724ba675SRob Herring interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 68*724ba675SRob Herring power-domains = <&pd_a3sm>; 69*724ba675SRob Herring arm,data-latency = <3 3 3>; 70*724ba675SRob Herring arm,tag-latency = <2 2 2>; 71*724ba675SRob Herring arm,shared-override; 72*724ba675SRob Herring cache-unified; 73*724ba675SRob Herring cache-level = <2>; 74*724ba675SRob Herring }; 75*724ba675SRob Herring 76*724ba675SRob Herring sbsc2: memory-controller@fb400000 { 77*724ba675SRob Herring compatible = "renesas,sbsc-sh73a0"; 78*724ba675SRob Herring reg = <0xfb400000 0x400>; 79*724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 80*724ba675SRob Herring <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 81*724ba675SRob Herring interrupt-names = "sec", "temp"; 82*724ba675SRob Herring power-domains = <&pd_a4bc1>; 83*724ba675SRob Herring }; 84*724ba675SRob Herring 85*724ba675SRob Herring sbsc1: memory-controller@fe400000 { 86*724ba675SRob Herring compatible = "renesas,sbsc-sh73a0"; 87*724ba675SRob Herring reg = <0xfe400000 0x400>; 88*724ba675SRob Herring interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 89*724ba675SRob Herring <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 90*724ba675SRob Herring interrupt-names = "sec", "temp"; 91*724ba675SRob Herring power-domains = <&pd_a4bc0>; 92*724ba675SRob Herring }; 93*724ba675SRob Herring 94*724ba675SRob Herring pmu { 95*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 96*724ba675SRob Herring interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 97*724ba675SRob Herring <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 98*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring cmt1: timer@e6138000 { 102*724ba675SRob Herring compatible = "renesas,sh73a0-cmt1"; 103*724ba675SRob Herring reg = <0xe6138000 0x200>; 104*724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 105*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_CMT1>; 106*724ba675SRob Herring clock-names = "fck"; 107*724ba675SRob Herring power-domains = <&pd_c5>; 108*724ba675SRob Herring status = "disabled"; 109*724ba675SRob Herring }; 110*724ba675SRob Herring 111*724ba675SRob Herring irqpin0: interrupt-controller@e6900000 { 112*724ba675SRob Herring compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; 113*724ba675SRob Herring #interrupt-cells = <2>; 114*724ba675SRob Herring interrupt-controller; 115*724ba675SRob Herring reg = <0xe6900000 4>, 116*724ba675SRob Herring <0xe6900010 4>, 117*724ba675SRob Herring <0xe6900020 1>, 118*724ba675SRob Herring <0xe6900040 1>, 119*724ba675SRob Herring <0xe6900060 1>; 120*724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 121*724ba675SRob Herring <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 122*724ba675SRob Herring <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 123*724ba675SRob Herring <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 124*724ba675SRob Herring <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 125*724ba675SRob Herring <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 126*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 127*724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 128*724ba675SRob Herring clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 129*724ba675SRob Herring power-domains = <&pd_a4s>; 130*724ba675SRob Herring control-parent; 131*724ba675SRob Herring }; 132*724ba675SRob Herring 133*724ba675SRob Herring irqpin1: interrupt-controller@e6900004 { 134*724ba675SRob Herring compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; 135*724ba675SRob Herring #interrupt-cells = <2>; 136*724ba675SRob Herring interrupt-controller; 137*724ba675SRob Herring reg = <0xe6900004 4>, 138*724ba675SRob Herring <0xe6900014 4>, 139*724ba675SRob Herring <0xe6900024 1>, 140*724ba675SRob Herring <0xe6900044 1>, 141*724ba675SRob Herring <0xe6900064 1>; 142*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 143*724ba675SRob Herring <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 144*724ba675SRob Herring <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 145*724ba675SRob Herring <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 146*724ba675SRob Herring <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 147*724ba675SRob Herring <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 148*724ba675SRob Herring <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 149*724ba675SRob Herring <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 150*724ba675SRob Herring clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 151*724ba675SRob Herring power-domains = <&pd_a4s>; 152*724ba675SRob Herring control-parent; 153*724ba675SRob Herring }; 154*724ba675SRob Herring 155*724ba675SRob Herring irqpin2: interrupt-controller@e6900008 { 156*724ba675SRob Herring compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; 157*724ba675SRob Herring #interrupt-cells = <2>; 158*724ba675SRob Herring interrupt-controller; 159*724ba675SRob Herring reg = <0xe6900008 4>, 160*724ba675SRob Herring <0xe6900018 4>, 161*724ba675SRob Herring <0xe6900028 1>, 162*724ba675SRob Herring <0xe6900048 1>, 163*724ba675SRob Herring <0xe6900068 1>; 164*724ba675SRob Herring interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 165*724ba675SRob Herring <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 166*724ba675SRob Herring <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 167*724ba675SRob Herring <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 168*724ba675SRob Herring <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 169*724ba675SRob Herring <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 170*724ba675SRob Herring <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 171*724ba675SRob Herring <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 172*724ba675SRob Herring clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 173*724ba675SRob Herring power-domains = <&pd_a4s>; 174*724ba675SRob Herring control-parent; 175*724ba675SRob Herring }; 176*724ba675SRob Herring 177*724ba675SRob Herring irqpin3: interrupt-controller@e690000c { 178*724ba675SRob Herring compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; 179*724ba675SRob Herring #interrupt-cells = <2>; 180*724ba675SRob Herring interrupt-controller; 181*724ba675SRob Herring reg = <0xe690000c 4>, 182*724ba675SRob Herring <0xe690001c 4>, 183*724ba675SRob Herring <0xe690002c 1>, 184*724ba675SRob Herring <0xe690004c 1>, 185*724ba675SRob Herring <0xe690006c 1>; 186*724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 187*724ba675SRob Herring <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 188*724ba675SRob Herring <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 189*724ba675SRob Herring <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 190*724ba675SRob Herring <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 191*724ba675SRob Herring <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 192*724ba675SRob Herring <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 193*724ba675SRob Herring <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 194*724ba675SRob Herring clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 195*724ba675SRob Herring power-domains = <&pd_a4s>; 196*724ba675SRob Herring control-parent; 197*724ba675SRob Herring }; 198*724ba675SRob Herring 199*724ba675SRob Herring i2c0: i2c@e6820000 { 200*724ba675SRob Herring #address-cells = <1>; 201*724ba675SRob Herring #size-cells = <0>; 202*724ba675SRob Herring compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; 203*724ba675SRob Herring reg = <0xe6820000 0x425>; 204*724ba675SRob Herring interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 205*724ba675SRob Herring <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 206*724ba675SRob Herring <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 207*724ba675SRob Herring <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 208*724ba675SRob Herring clocks = <&mstp1_clks SH73A0_CLK_IIC0>; 209*724ba675SRob Herring power-domains = <&pd_a3sp>; 210*724ba675SRob Herring status = "disabled"; 211*724ba675SRob Herring }; 212*724ba675SRob Herring 213*724ba675SRob Herring i2c1: i2c@e6822000 { 214*724ba675SRob Herring #address-cells = <1>; 215*724ba675SRob Herring #size-cells = <0>; 216*724ba675SRob Herring compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; 217*724ba675SRob Herring reg = <0xe6822000 0x425>; 218*724ba675SRob Herring interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 219*724ba675SRob Herring <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 220*724ba675SRob Herring <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 221*724ba675SRob Herring <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 222*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_IIC1>; 223*724ba675SRob Herring power-domains = <&pd_a3sp>; 224*724ba675SRob Herring status = "disabled"; 225*724ba675SRob Herring }; 226*724ba675SRob Herring 227*724ba675SRob Herring i2c2: i2c@e6824000 { 228*724ba675SRob Herring #address-cells = <1>; 229*724ba675SRob Herring #size-cells = <0>; 230*724ba675SRob Herring compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; 231*724ba675SRob Herring reg = <0xe6824000 0x425>; 232*724ba675SRob Herring interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 233*724ba675SRob Herring <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 234*724ba675SRob Herring <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 235*724ba675SRob Herring <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 236*724ba675SRob Herring clocks = <&mstp0_clks SH73A0_CLK_IIC2>; 237*724ba675SRob Herring power-domains = <&pd_a3sp>; 238*724ba675SRob Herring status = "disabled"; 239*724ba675SRob Herring }; 240*724ba675SRob Herring 241*724ba675SRob Herring i2c3: i2c@e6826000 { 242*724ba675SRob Herring #address-cells = <1>; 243*724ba675SRob Herring #size-cells = <0>; 244*724ba675SRob Herring compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; 245*724ba675SRob Herring reg = <0xe6826000 0x425>; 246*724ba675SRob Herring interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 247*724ba675SRob Herring <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 248*724ba675SRob Herring <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 249*724ba675SRob Herring <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 250*724ba675SRob Herring clocks = <&mstp4_clks SH73A0_CLK_IIC3>; 251*724ba675SRob Herring power-domains = <&pd_a3sp>; 252*724ba675SRob Herring status = "disabled"; 253*724ba675SRob Herring }; 254*724ba675SRob Herring 255*724ba675SRob Herring i2c4: i2c@e6828000 { 256*724ba675SRob Herring #address-cells = <1>; 257*724ba675SRob Herring #size-cells = <0>; 258*724ba675SRob Herring compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; 259*724ba675SRob Herring reg = <0xe6828000 0x425>; 260*724ba675SRob Herring interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 261*724ba675SRob Herring <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 262*724ba675SRob Herring <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 263*724ba675SRob Herring <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 264*724ba675SRob Herring clocks = <&mstp4_clks SH73A0_CLK_IIC4>; 265*724ba675SRob Herring power-domains = <&pd_c5>; 266*724ba675SRob Herring status = "disabled"; 267*724ba675SRob Herring }; 268*724ba675SRob Herring 269*724ba675SRob Herring mmcif: mmc@e6bd0000 { 270*724ba675SRob Herring compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif"; 271*724ba675SRob Herring reg = <0xe6bd0000 0x100>; 272*724ba675SRob Herring interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 273*724ba675SRob Herring <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 274*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; 275*724ba675SRob Herring power-domains = <&pd_a3sp>; 276*724ba675SRob Herring status = "disabled"; 277*724ba675SRob Herring }; 278*724ba675SRob Herring 279*724ba675SRob Herring msiof0: spi@e6e20000 { 280*724ba675SRob Herring compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; 281*724ba675SRob Herring reg = <0xe6e20000 0x0064>; 282*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 283*724ba675SRob Herring clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; 284*724ba675SRob Herring power-domains = <&pd_a3sp>; 285*724ba675SRob Herring #address-cells = <1>; 286*724ba675SRob Herring #size-cells = <0>; 287*724ba675SRob Herring status = "disabled"; 288*724ba675SRob Herring }; 289*724ba675SRob Herring 290*724ba675SRob Herring msiof1: spi@e6e10000 { 291*724ba675SRob Herring compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; 292*724ba675SRob Herring reg = <0xe6e10000 0x0064>; 293*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 294*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; 295*724ba675SRob Herring power-domains = <&pd_a3sp>; 296*724ba675SRob Herring #address-cells = <1>; 297*724ba675SRob Herring #size-cells = <0>; 298*724ba675SRob Herring status = "disabled"; 299*724ba675SRob Herring }; 300*724ba675SRob Herring 301*724ba675SRob Herring msiof2: spi@e6e00000 { 302*724ba675SRob Herring compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; 303*724ba675SRob Herring reg = <0xe6e00000 0x0064>; 304*724ba675SRob Herring interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 305*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; 306*724ba675SRob Herring power-domains = <&pd_a3sp>; 307*724ba675SRob Herring #address-cells = <1>; 308*724ba675SRob Herring #size-cells = <0>; 309*724ba675SRob Herring status = "disabled"; 310*724ba675SRob Herring }; 311*724ba675SRob Herring 312*724ba675SRob Herring msiof3: spi@e6c90000 { 313*724ba675SRob Herring compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; 314*724ba675SRob Herring reg = <0xe6c90000 0x0064>; 315*724ba675SRob Herring interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 316*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; 317*724ba675SRob Herring power-domains = <&pd_a3sp>; 318*724ba675SRob Herring #address-cells = <1>; 319*724ba675SRob Herring #size-cells = <0>; 320*724ba675SRob Herring status = "disabled"; 321*724ba675SRob Herring }; 322*724ba675SRob Herring 323*724ba675SRob Herring sdhi0: mmc@ee100000 { 324*724ba675SRob Herring compatible = "renesas,sdhi-sh73a0"; 325*724ba675SRob Herring reg = <0xee100000 0x100>; 326*724ba675SRob Herring interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 327*724ba675SRob Herring <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 328*724ba675SRob Herring <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 329*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; 330*724ba675SRob Herring power-domains = <&pd_a3sp>; 331*724ba675SRob Herring cap-sd-highspeed; 332*724ba675SRob Herring status = "disabled"; 333*724ba675SRob Herring }; 334*724ba675SRob Herring 335*724ba675SRob Herring /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ 336*724ba675SRob Herring sdhi1: mmc@ee120000 { 337*724ba675SRob Herring compatible = "renesas,sdhi-sh73a0"; 338*724ba675SRob Herring reg = <0xee120000 0x100>; 339*724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 340*724ba675SRob Herring <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 341*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; 342*724ba675SRob Herring power-domains = <&pd_a3sp>; 343*724ba675SRob Herring disable-wp; 344*724ba675SRob Herring cap-sd-highspeed; 345*724ba675SRob Herring status = "disabled"; 346*724ba675SRob Herring }; 347*724ba675SRob Herring 348*724ba675SRob Herring sdhi2: mmc@ee140000 { 349*724ba675SRob Herring compatible = "renesas,sdhi-sh73a0"; 350*724ba675SRob Herring reg = <0xee140000 0x100>; 351*724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 352*724ba675SRob Herring <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 353*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; 354*724ba675SRob Herring power-domains = <&pd_a3sp>; 355*724ba675SRob Herring disable-wp; 356*724ba675SRob Herring cap-sd-highspeed; 357*724ba675SRob Herring status = "disabled"; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring scifa0: serial@e6c40000 { 361*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 362*724ba675SRob Herring reg = <0xe6c40000 0x100>; 363*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 364*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; 365*724ba675SRob Herring clock-names = "fck"; 366*724ba675SRob Herring power-domains = <&pd_a3sp>; 367*724ba675SRob Herring status = "disabled"; 368*724ba675SRob Herring }; 369*724ba675SRob Herring 370*724ba675SRob Herring scifa1: serial@e6c50000 { 371*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 372*724ba675SRob Herring reg = <0xe6c50000 0x100>; 373*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 374*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; 375*724ba675SRob Herring clock-names = "fck"; 376*724ba675SRob Herring power-domains = <&pd_a3sp>; 377*724ba675SRob Herring status = "disabled"; 378*724ba675SRob Herring }; 379*724ba675SRob Herring 380*724ba675SRob Herring scifa2: serial@e6c60000 { 381*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 382*724ba675SRob Herring reg = <0xe6c60000 0x100>; 383*724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 384*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; 385*724ba675SRob Herring clock-names = "fck"; 386*724ba675SRob Herring power-domains = <&pd_a3sp>; 387*724ba675SRob Herring status = "disabled"; 388*724ba675SRob Herring }; 389*724ba675SRob Herring 390*724ba675SRob Herring scifa3: serial@e6c70000 { 391*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 392*724ba675SRob Herring reg = <0xe6c70000 0x100>; 393*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 394*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; 395*724ba675SRob Herring clock-names = "fck"; 396*724ba675SRob Herring power-domains = <&pd_a3sp>; 397*724ba675SRob Herring status = "disabled"; 398*724ba675SRob Herring }; 399*724ba675SRob Herring 400*724ba675SRob Herring scifa4: serial@e6c80000 { 401*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 402*724ba675SRob Herring reg = <0xe6c80000 0x100>; 403*724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 404*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; 405*724ba675SRob Herring clock-names = "fck"; 406*724ba675SRob Herring power-domains = <&pd_a3sp>; 407*724ba675SRob Herring status = "disabled"; 408*724ba675SRob Herring }; 409*724ba675SRob Herring 410*724ba675SRob Herring scifa5: serial@e6cb0000 { 411*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 412*724ba675SRob Herring reg = <0xe6cb0000 0x100>; 413*724ba675SRob Herring interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 414*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; 415*724ba675SRob Herring clock-names = "fck"; 416*724ba675SRob Herring power-domains = <&pd_a3sp>; 417*724ba675SRob Herring status = "disabled"; 418*724ba675SRob Herring }; 419*724ba675SRob Herring 420*724ba675SRob Herring scifa6: serial@e6cc0000 { 421*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 422*724ba675SRob Herring reg = <0xe6cc0000 0x100>; 423*724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 424*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; 425*724ba675SRob Herring clock-names = "fck"; 426*724ba675SRob Herring power-domains = <&pd_a3sp>; 427*724ba675SRob Herring status = "disabled"; 428*724ba675SRob Herring }; 429*724ba675SRob Herring 430*724ba675SRob Herring scifa7: serial@e6cd0000 { 431*724ba675SRob Herring compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 432*724ba675SRob Herring reg = <0xe6cd0000 0x100>; 433*724ba675SRob Herring interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 434*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; 435*724ba675SRob Herring clock-names = "fck"; 436*724ba675SRob Herring power-domains = <&pd_a3sp>; 437*724ba675SRob Herring status = "disabled"; 438*724ba675SRob Herring }; 439*724ba675SRob Herring 440*724ba675SRob Herring scifb: serial@e6c30000 { 441*724ba675SRob Herring compatible = "renesas,scifb-sh73a0", "renesas,scifb"; 442*724ba675SRob Herring reg = <0xe6c30000 0x100>; 443*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 444*724ba675SRob Herring clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; 445*724ba675SRob Herring clock-names = "fck"; 446*724ba675SRob Herring power-domains = <&pd_a3sp>; 447*724ba675SRob Herring status = "disabled"; 448*724ba675SRob Herring }; 449*724ba675SRob Herring 450*724ba675SRob Herring pfc: pinctrl@e6050000 { 451*724ba675SRob Herring compatible = "renesas,pfc-sh73a0"; 452*724ba675SRob Herring reg = <0xe6050000 0x8000>, 453*724ba675SRob Herring <0xe605801c 0x1c>; 454*724ba675SRob Herring gpio-controller; 455*724ba675SRob Herring #gpio-cells = <2>; 456*724ba675SRob Herring gpio-ranges = 457*724ba675SRob Herring <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, 458*724ba675SRob Herring <&pfc 288 288 22>; 459*724ba675SRob Herring interrupts-extended = 460*724ba675SRob Herring <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, 461*724ba675SRob Herring <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, 462*724ba675SRob Herring <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, 463*724ba675SRob Herring <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, 464*724ba675SRob Herring <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, 465*724ba675SRob Herring <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 466*724ba675SRob Herring <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 467*724ba675SRob Herring <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 468*724ba675SRob Herring power-domains = <&pd_c5>; 469*724ba675SRob Herring }; 470*724ba675SRob Herring 471*724ba675SRob Herring sysc: system-controller@e6180000 { 472*724ba675SRob Herring compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; 473*724ba675SRob Herring reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; 474*724ba675SRob Herring 475*724ba675SRob Herring pm-domains { 476*724ba675SRob Herring pd_c5: c5 { 477*724ba675SRob Herring #address-cells = <1>; 478*724ba675SRob Herring #size-cells = <0>; 479*724ba675SRob Herring #power-domain-cells = <0>; 480*724ba675SRob Herring 481*724ba675SRob Herring pd_c4: c4@0 { 482*724ba675SRob Herring reg = <0>; 483*724ba675SRob Herring #power-domain-cells = <0>; 484*724ba675SRob Herring }; 485*724ba675SRob Herring 486*724ba675SRob Herring pd_d4: d4@1 { 487*724ba675SRob Herring reg = <1>; 488*724ba675SRob Herring #power-domain-cells = <0>; 489*724ba675SRob Herring }; 490*724ba675SRob Herring 491*724ba675SRob Herring pd_a4bc0: a4bc0@4 { 492*724ba675SRob Herring reg = <4>; 493*724ba675SRob Herring #power-domain-cells = <0>; 494*724ba675SRob Herring }; 495*724ba675SRob Herring 496*724ba675SRob Herring pd_a4bc1: a4bc1@5 { 497*724ba675SRob Herring reg = <5>; 498*724ba675SRob Herring #power-domain-cells = <0>; 499*724ba675SRob Herring }; 500*724ba675SRob Herring 501*724ba675SRob Herring pd_a4lc0: a4lc0@6 { 502*724ba675SRob Herring reg = <6>; 503*724ba675SRob Herring #power-domain-cells = <0>; 504*724ba675SRob Herring }; 505*724ba675SRob Herring 506*724ba675SRob Herring pd_a4lc1: a4lc1@7 { 507*724ba675SRob Herring reg = <7>; 508*724ba675SRob Herring #power-domain-cells = <0>; 509*724ba675SRob Herring }; 510*724ba675SRob Herring 511*724ba675SRob Herring pd_a4mp: a4mp@8 { 512*724ba675SRob Herring reg = <8>; 513*724ba675SRob Herring #address-cells = <1>; 514*724ba675SRob Herring #size-cells = <0>; 515*724ba675SRob Herring #power-domain-cells = <0>; 516*724ba675SRob Herring 517*724ba675SRob Herring pd_a3mp: a3mp@9 { 518*724ba675SRob Herring reg = <9>; 519*724ba675SRob Herring #power-domain-cells = <0>; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring pd_a3vc: a3vc@10 { 523*724ba675SRob Herring reg = <10>; 524*724ba675SRob Herring #power-domain-cells = <0>; 525*724ba675SRob Herring }; 526*724ba675SRob Herring }; 527*724ba675SRob Herring 528*724ba675SRob Herring pd_a4rm: a4rm@12 { 529*724ba675SRob Herring reg = <12>; 530*724ba675SRob Herring #address-cells = <1>; 531*724ba675SRob Herring #size-cells = <0>; 532*724ba675SRob Herring #power-domain-cells = <0>; 533*724ba675SRob Herring 534*724ba675SRob Herring pd_a3r: a3r@13 { 535*724ba675SRob Herring reg = <13>; 536*724ba675SRob Herring #address-cells = <1>; 537*724ba675SRob Herring #size-cells = <0>; 538*724ba675SRob Herring #power-domain-cells = <0>; 539*724ba675SRob Herring 540*724ba675SRob Herring pd_a2rv: a2rv@14 { 541*724ba675SRob Herring reg = <14>; 542*724ba675SRob Herring #address-cells = <1>; 543*724ba675SRob Herring #size-cells = <0>; 544*724ba675SRob Herring #power-domain-cells = <0>; 545*724ba675SRob Herring }; 546*724ba675SRob Herring }; 547*724ba675SRob Herring }; 548*724ba675SRob Herring 549*724ba675SRob Herring pd_a4s: a4s@16 { 550*724ba675SRob Herring reg = <16>; 551*724ba675SRob Herring #address-cells = <1>; 552*724ba675SRob Herring #size-cells = <0>; 553*724ba675SRob Herring #power-domain-cells = <0>; 554*724ba675SRob Herring 555*724ba675SRob Herring pd_a3sp: a3sp@17 { 556*724ba675SRob Herring reg = <17>; 557*724ba675SRob Herring #power-domain-cells = <0>; 558*724ba675SRob Herring }; 559*724ba675SRob Herring 560*724ba675SRob Herring pd_a3sg: a3sg@18 { 561*724ba675SRob Herring reg = <18>; 562*724ba675SRob Herring #power-domain-cells = <0>; 563*724ba675SRob Herring }; 564*724ba675SRob Herring 565*724ba675SRob Herring pd_a3sm: a3sm@19 { 566*724ba675SRob Herring reg = <19>; 567*724ba675SRob Herring #address-cells = <1>; 568*724ba675SRob Herring #size-cells = <0>; 569*724ba675SRob Herring #power-domain-cells = <0>; 570*724ba675SRob Herring 571*724ba675SRob Herring pd_a2sl: a2sl@20 { 572*724ba675SRob Herring reg = <20>; 573*724ba675SRob Herring #power-domain-cells = <0>; 574*724ba675SRob Herring }; 575*724ba675SRob Herring }; 576*724ba675SRob Herring }; 577*724ba675SRob Herring }; 578*724ba675SRob Herring }; 579*724ba675SRob Herring }; 580*724ba675SRob Herring 581*724ba675SRob Herring sh_fsi2: sound@ec230000 { 582*724ba675SRob Herring #sound-dai-cells = <1>; 583*724ba675SRob Herring compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; 584*724ba675SRob Herring reg = <0xec230000 0x400>; 585*724ba675SRob Herring interrupts = <GIC_SPI 146 0x4>; 586*724ba675SRob Herring clocks = <&mstp3_clks SH73A0_CLK_FSI>; 587*724ba675SRob Herring power-domains = <&pd_a4mp>; 588*724ba675SRob Herring status = "disabled"; 589*724ba675SRob Herring }; 590*724ba675SRob Herring 591*724ba675SRob Herring bsc: bus@fec10000 { 592*724ba675SRob Herring compatible = "renesas,bsc-sh73a0", "renesas,bsc", 593*724ba675SRob Herring "simple-pm-bus"; 594*724ba675SRob Herring #address-cells = <1>; 595*724ba675SRob Herring #size-cells = <1>; 596*724ba675SRob Herring ranges = <0 0 0x20000000>; 597*724ba675SRob Herring reg = <0xfec10000 0x400>; 598*724ba675SRob Herring interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 599*724ba675SRob Herring clocks = <&zb_clk>; 600*724ba675SRob Herring power-domains = <&pd_a4s>; 601*724ba675SRob Herring }; 602*724ba675SRob Herring 603*724ba675SRob Herring clocks { 604*724ba675SRob Herring #address-cells = <1>; 605*724ba675SRob Herring #size-cells = <1>; 606*724ba675SRob Herring ranges; 607*724ba675SRob Herring 608*724ba675SRob Herring /* External root clocks */ 609*724ba675SRob Herring extalr_clk: extalr { 610*724ba675SRob Herring compatible = "fixed-clock"; 611*724ba675SRob Herring #clock-cells = <0>; 612*724ba675SRob Herring clock-frequency = <32768>; 613*724ba675SRob Herring }; 614*724ba675SRob Herring extal1_clk: extal1 { 615*724ba675SRob Herring compatible = "fixed-clock"; 616*724ba675SRob Herring #clock-cells = <0>; 617*724ba675SRob Herring clock-frequency = <26000000>; 618*724ba675SRob Herring }; 619*724ba675SRob Herring extal2_clk: extal2 { 620*724ba675SRob Herring compatible = "fixed-clock"; 621*724ba675SRob Herring #clock-cells = <0>; 622*724ba675SRob Herring /* This value must be overridden by the board. */ 623*724ba675SRob Herring clock-frequency = <0>; 624*724ba675SRob Herring }; 625*724ba675SRob Herring extcki_clk: extcki { 626*724ba675SRob Herring compatible = "fixed-clock"; 627*724ba675SRob Herring #clock-cells = <0>; 628*724ba675SRob Herring /* This value can be overridden by the board. */ 629*724ba675SRob Herring clock-frequency = <0>; 630*724ba675SRob Herring }; 631*724ba675SRob Herring fsiack_clk: fsiack { 632*724ba675SRob Herring compatible = "fixed-clock"; 633*724ba675SRob Herring #clock-cells = <0>; 634*724ba675SRob Herring /* This value can be overridden by the board. */ 635*724ba675SRob Herring clock-frequency = <0>; 636*724ba675SRob Herring }; 637*724ba675SRob Herring fsibck_clk: fsibck { 638*724ba675SRob Herring compatible = "fixed-clock"; 639*724ba675SRob Herring #clock-cells = <0>; 640*724ba675SRob Herring /* This value can be overridden by the board. */ 641*724ba675SRob Herring clock-frequency = <0>; 642*724ba675SRob Herring }; 643*724ba675SRob Herring 644*724ba675SRob Herring /* Special CPG clocks */ 645*724ba675SRob Herring cpg_clocks: cpg_clocks@e6150000 { 646*724ba675SRob Herring compatible = "renesas,sh73a0-cpg-clocks"; 647*724ba675SRob Herring reg = <0xe6150000 0x10000>; 648*724ba675SRob Herring clocks = <&extal1_clk>, <&extal2_clk>; 649*724ba675SRob Herring #clock-cells = <1>; 650*724ba675SRob Herring clock-output-names = "main", "pll0", "pll1", "pll2", 651*724ba675SRob Herring "pll3", "dsi0phy", "dsi1phy", 652*724ba675SRob Herring "zg", "m3", "b", "m1", "m2", 653*724ba675SRob Herring "z", "zx", "hp"; 654*724ba675SRob Herring }; 655*724ba675SRob Herring 656*724ba675SRob Herring /* Variable factor clocks (DIV6) */ 657*724ba675SRob Herring vclk1_clk: vclk1@e6150008 { 658*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 659*724ba675SRob Herring reg = <0xe6150008 4>; 660*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 661*724ba675SRob Herring <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, 662*724ba675SRob Herring <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, 663*724ba675SRob Herring <0>; 664*724ba675SRob Herring #clock-cells = <0>; 665*724ba675SRob Herring }; 666*724ba675SRob Herring vclk2_clk: vclk2@e615000c { 667*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 668*724ba675SRob Herring reg = <0xe615000c 4>; 669*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 670*724ba675SRob Herring <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, 671*724ba675SRob Herring <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, 672*724ba675SRob Herring <0>; 673*724ba675SRob Herring #clock-cells = <0>; 674*724ba675SRob Herring }; 675*724ba675SRob Herring vclk3_clk: vclk3@e615001c { 676*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 677*724ba675SRob Herring reg = <0xe615001c 4>; 678*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 679*724ba675SRob Herring <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, 680*724ba675SRob Herring <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, 681*724ba675SRob Herring <0>; 682*724ba675SRob Herring #clock-cells = <0>; 683*724ba675SRob Herring }; 684*724ba675SRob Herring zb_clk: zb_clk@e6150010 { 685*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 686*724ba675SRob Herring reg = <0xe6150010 4>; 687*724ba675SRob Herring clocks = <&pll1_div2_clk>, <0>, 688*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_PLL2>, <0>; 689*724ba675SRob Herring #clock-cells = <0>; 690*724ba675SRob Herring clock-output-names = "zb"; 691*724ba675SRob Herring }; 692*724ba675SRob Herring flctl_clk: flctlck@e6150014 { 693*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 694*724ba675SRob Herring reg = <0xe6150014 4>; 695*724ba675SRob Herring clocks = <&pll1_div2_clk>, <0>, 696*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_PLL2>, <0>; 697*724ba675SRob Herring #clock-cells = <0>; 698*724ba675SRob Herring }; 699*724ba675SRob Herring sdhi0_clk: sdhi0ck@e6150074 { 700*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 701*724ba675SRob Herring reg = <0xe6150074 4>; 702*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 703*724ba675SRob Herring <&pll1_div13_clk>, <0>; 704*724ba675SRob Herring #clock-cells = <0>; 705*724ba675SRob Herring }; 706*724ba675SRob Herring sdhi1_clk: sdhi1ck@e6150078 { 707*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 708*724ba675SRob Herring reg = <0xe6150078 4>; 709*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 710*724ba675SRob Herring <&pll1_div13_clk>, <0>; 711*724ba675SRob Herring #clock-cells = <0>; 712*724ba675SRob Herring }; 713*724ba675SRob Herring sdhi2_clk: sdhi2ck@e615007c { 714*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 715*724ba675SRob Herring reg = <0xe615007c 4>; 716*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 717*724ba675SRob Herring <&pll1_div13_clk>, <0>; 718*724ba675SRob Herring #clock-cells = <0>; 719*724ba675SRob Herring }; 720*724ba675SRob Herring fsia_clk: fsia@e6150018 { 721*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 722*724ba675SRob Herring reg = <0xe6150018 4>; 723*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 724*724ba675SRob Herring <&fsiack_clk>, <&fsiack_clk>; 725*724ba675SRob Herring #clock-cells = <0>; 726*724ba675SRob Herring }; 727*724ba675SRob Herring fsib_clk: fsib@e6150090 { 728*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 729*724ba675SRob Herring reg = <0xe6150090 4>; 730*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 731*724ba675SRob Herring <&fsibck_clk>, <&fsibck_clk>; 732*724ba675SRob Herring #clock-cells = <0>; 733*724ba675SRob Herring }; 734*724ba675SRob Herring sub_clk: sub@e6150080 { 735*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 736*724ba675SRob Herring reg = <0xe6150080 4>; 737*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 738*724ba675SRob Herring <&extal2_clk>, <&extal2_clk>; 739*724ba675SRob Herring #clock-cells = <0>; 740*724ba675SRob Herring }; 741*724ba675SRob Herring spua_clk: spua@e6150084 { 742*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 743*724ba675SRob Herring reg = <0xe6150084 4>; 744*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 745*724ba675SRob Herring <&extal2_clk>, <&extal2_clk>; 746*724ba675SRob Herring #clock-cells = <0>; 747*724ba675SRob Herring }; 748*724ba675SRob Herring spuv_clk: spuv@e6150094 { 749*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 750*724ba675SRob Herring reg = <0xe6150094 4>; 751*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 752*724ba675SRob Herring <&extal2_clk>, <&extal2_clk>; 753*724ba675SRob Herring #clock-cells = <0>; 754*724ba675SRob Herring }; 755*724ba675SRob Herring msu_clk: msu@e6150088 { 756*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 757*724ba675SRob Herring reg = <0xe6150088 4>; 758*724ba675SRob Herring clocks = <&pll1_div2_clk>, <0>, 759*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_PLL2>, <0>; 760*724ba675SRob Herring #clock-cells = <0>; 761*724ba675SRob Herring }; 762*724ba675SRob Herring hsi_clk: hsi@e615008c { 763*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 764*724ba675SRob Herring reg = <0xe615008c 4>; 765*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 766*724ba675SRob Herring <&pll1_div7_clk>, <0>; 767*724ba675SRob Herring #clock-cells = <0>; 768*724ba675SRob Herring }; 769*724ba675SRob Herring mfg1_clk: mfg1@e6150098 { 770*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 771*724ba675SRob Herring reg = <0xe6150098 4>; 772*724ba675SRob Herring clocks = <&pll1_div2_clk>, <0>, 773*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_PLL2>, <0>; 774*724ba675SRob Herring #clock-cells = <0>; 775*724ba675SRob Herring }; 776*724ba675SRob Herring mfg2_clk: mfg2@e615009c { 777*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 778*724ba675SRob Herring reg = <0xe615009c 4>; 779*724ba675SRob Herring clocks = <&pll1_div2_clk>, <0>, 780*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_PLL2>, <0>; 781*724ba675SRob Herring #clock-cells = <0>; 782*724ba675SRob Herring }; 783*724ba675SRob Herring dsit_clk: dsit@e6150060 { 784*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 785*724ba675SRob Herring reg = <0xe6150060 4>; 786*724ba675SRob Herring clocks = <&pll1_div2_clk>, <0>, 787*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_PLL2>, <0>; 788*724ba675SRob Herring #clock-cells = <0>; 789*724ba675SRob Herring }; 790*724ba675SRob Herring dsi0p_clk: dsi0pck@e6150064 { 791*724ba675SRob Herring compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 792*724ba675SRob Herring reg = <0xe6150064 4>; 793*724ba675SRob Herring clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, 794*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, 795*724ba675SRob Herring <&extcki_clk>, <0>, <0>, <0>; 796*724ba675SRob Herring #clock-cells = <0>; 797*724ba675SRob Herring }; 798*724ba675SRob Herring 799*724ba675SRob Herring /* Fixed factor clocks */ 800*724ba675SRob Herring main_div2_clk: main_div2 { 801*724ba675SRob Herring compatible = "fixed-factor-clock"; 802*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_MAIN>; 803*724ba675SRob Herring #clock-cells = <0>; 804*724ba675SRob Herring clock-div = <2>; 805*724ba675SRob Herring clock-mult = <1>; 806*724ba675SRob Herring }; 807*724ba675SRob Herring pll1_div2_clk: pll1_div2 { 808*724ba675SRob Herring compatible = "fixed-factor-clock"; 809*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_PLL1>; 810*724ba675SRob Herring #clock-cells = <0>; 811*724ba675SRob Herring clock-div = <2>; 812*724ba675SRob Herring clock-mult = <1>; 813*724ba675SRob Herring }; 814*724ba675SRob Herring pll1_div7_clk: pll1_div7 { 815*724ba675SRob Herring compatible = "fixed-factor-clock"; 816*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_PLL1>; 817*724ba675SRob Herring #clock-cells = <0>; 818*724ba675SRob Herring clock-div = <7>; 819*724ba675SRob Herring clock-mult = <1>; 820*724ba675SRob Herring }; 821*724ba675SRob Herring pll1_div13_clk: pll1_div13 { 822*724ba675SRob Herring compatible = "fixed-factor-clock"; 823*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_PLL1>; 824*724ba675SRob Herring #clock-cells = <0>; 825*724ba675SRob Herring clock-div = <13>; 826*724ba675SRob Herring clock-mult = <1>; 827*724ba675SRob Herring }; 828*724ba675SRob Herring periph_clk: periph { 829*724ba675SRob Herring compatible = "fixed-factor-clock"; 830*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_Z>; 831*724ba675SRob Herring #clock-cells = <0>; 832*724ba675SRob Herring clock-div = <4>; 833*724ba675SRob Herring clock-mult = <1>; 834*724ba675SRob Herring }; 835*724ba675SRob Herring 836*724ba675SRob Herring /* Gate clocks */ 837*724ba675SRob Herring mstp0_clks: mstp0_clks@e6150130 { 838*724ba675SRob Herring compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; 839*724ba675SRob Herring reg = <0xe6150130 4>, <0xe6150030 4>; 840*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; 841*724ba675SRob Herring #clock-cells = <1>; 842*724ba675SRob Herring clock-indices = < 843*724ba675SRob Herring SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 844*724ba675SRob Herring >; 845*724ba675SRob Herring clock-output-names = 846*724ba675SRob Herring "iic2", "msiof0"; 847*724ba675SRob Herring }; 848*724ba675SRob Herring mstp1_clks: mstp1_clks@e6150134 { 849*724ba675SRob Herring compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; 850*724ba675SRob Herring reg = <0xe6150134 4>, <0xe6150038 4>; 851*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_B>, 852*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_B>, 853*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_B>, 854*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_B>, 855*724ba675SRob Herring <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, 856*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_HP>, 857*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_ZG>, 858*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_B>; 859*724ba675SRob Herring #clock-cells = <1>; 860*724ba675SRob Herring clock-indices = < 861*724ba675SRob Herring SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 862*724ba675SRob Herring SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 863*724ba675SRob Herring SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 864*724ba675SRob Herring SH73A0_CLK_IIC0 SH73A0_CLK_SGX 865*724ba675SRob Herring SH73A0_CLK_LCDC0 866*724ba675SRob Herring >; 867*724ba675SRob Herring clock-output-names = 868*724ba675SRob Herring "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", 869*724ba675SRob Herring "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; 870*724ba675SRob Herring }; 871*724ba675SRob Herring mstp2_clks: mstp2_clks@e6150138 { 872*724ba675SRob Herring compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; 873*724ba675SRob Herring reg = <0xe6150138 4>, <0xe6150040 4>; 874*724ba675SRob Herring clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, 875*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, 876*724ba675SRob Herring <&sub_clk>, <&sub_clk>, <&sub_clk>, 877*724ba675SRob Herring <&sub_clk>, <&sub_clk>, <&sub_clk>, 878*724ba675SRob Herring <&sub_clk>, <&sub_clk>, <&sub_clk>; 879*724ba675SRob Herring #clock-cells = <1>; 880*724ba675SRob Herring clock-indices = < 881*724ba675SRob Herring SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC 882*724ba675SRob Herring SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 883*724ba675SRob Herring SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 884*724ba675SRob Herring SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 885*724ba675SRob Herring SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 886*724ba675SRob Herring SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 887*724ba675SRob Herring SH73A0_CLK_SCIFA4 888*724ba675SRob Herring >; 889*724ba675SRob Herring clock-output-names = 890*724ba675SRob Herring "scifa7", "sy_dmac", "mp_dmac", "msiof3", 891*724ba675SRob Herring "msiof1", "scifa5", "scifb", "msiof2", 892*724ba675SRob Herring "scifa0", "scifa1", "scifa2", "scifa3", 893*724ba675SRob Herring "scifa4"; 894*724ba675SRob Herring }; 895*724ba675SRob Herring mstp3_clks: mstp3_clks@e615013c { 896*724ba675SRob Herring compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; 897*724ba675SRob Herring reg = <0xe615013c 4>, <0xe6150048 4>; 898*724ba675SRob Herring clocks = <&sub_clk>, <&extalr_clk>, 899*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, 900*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_HP>, 901*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, 902*724ba675SRob Herring <&sdhi0_clk>, <&sdhi1_clk>, 903*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, 904*724ba675SRob Herring <&main_div2_clk>, <&main_div2_clk>, 905*724ba675SRob Herring <&main_div2_clk>, <&main_div2_clk>, 906*724ba675SRob Herring <&main_div2_clk>; 907*724ba675SRob Herring #clock-cells = <1>; 908*724ba675SRob Herring clock-indices = < 909*724ba675SRob Herring SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 910*724ba675SRob Herring SH73A0_CLK_FSI SH73A0_CLK_IRDA 911*724ba675SRob Herring SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL 912*724ba675SRob Herring SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 913*724ba675SRob Herring SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 914*724ba675SRob Herring SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 915*724ba675SRob Herring SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 916*724ba675SRob Herring SH73A0_CLK_TPU4 917*724ba675SRob Herring >; 918*724ba675SRob Herring clock-output-names = 919*724ba675SRob Herring "scifa6", "cmt1", "fsi", "irda", "iic1", 920*724ba675SRob Herring "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", 921*724ba675SRob Herring "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; 922*724ba675SRob Herring }; 923*724ba675SRob Herring mstp4_clks: mstp4_clks@e6150140 { 924*724ba675SRob Herring compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; 925*724ba675SRob Herring reg = <0xe6150140 4>, <0xe615004c 4>; 926*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_HP>, 927*724ba675SRob Herring <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; 928*724ba675SRob Herring #clock-cells = <1>; 929*724ba675SRob Herring clock-indices = < 930*724ba675SRob Herring SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 931*724ba675SRob Herring SH73A0_CLK_KEYSC 932*724ba675SRob Herring >; 933*724ba675SRob Herring clock-output-names = 934*724ba675SRob Herring "iic3", "iic4", "keysc"; 935*724ba675SRob Herring }; 936*724ba675SRob Herring mstp5_clks: mstp5_clks@e6150144 { 937*724ba675SRob Herring compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; 938*724ba675SRob Herring reg = <0xe6150144 4>, <0xe615003c 4>; 939*724ba675SRob Herring clocks = <&cpg_clocks SH73A0_CLK_HP>; 940*724ba675SRob Herring #clock-cells = <1>; 941*724ba675SRob Herring clock-indices = < 942*724ba675SRob Herring SH73A0_CLK_INTCA0 943*724ba675SRob Herring >; 944*724ba675SRob Herring clock-output-names = 945*724ba675SRob Herring "intca0"; 946*724ba675SRob Herring }; 947*724ba675SRob Herring }; 948*724ba675SRob Herring}; 949