xref: /linux/scripts/dtc/include-prefixes/arm/renesas/r8a7792.dtsi (revision 60675d4ca1ef0857e44eba5849b74a3a998d0c0f)
1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2724ba675SRob Herring/*
3724ba675SRob Herring * Device Tree Source for the R-Car V2H (R8A77920) SoC
4724ba675SRob Herring *
5724ba675SRob Herring * Copyright (C) 2016 Cogent Embedded Inc.
6724ba675SRob Herring */
7724ba675SRob Herring
8724ba675SRob Herring#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
9724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h>
10724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h>
11724ba675SRob Herring#include <dt-bindings/power/r8a7792-sysc.h>
12724ba675SRob Herring
13724ba675SRob Herring/ {
14724ba675SRob Herring	compatible = "renesas,r8a7792";
15724ba675SRob Herring	#address-cells = <2>;
16724ba675SRob Herring	#size-cells = <2>;
17724ba675SRob Herring
18724ba675SRob Herring	aliases {
19724ba675SRob Herring		i2c0 = &i2c0;
20724ba675SRob Herring		i2c1 = &i2c1;
21724ba675SRob Herring		i2c2 = &i2c2;
22724ba675SRob Herring		i2c3 = &i2c3;
23724ba675SRob Herring		i2c4 = &i2c4;
24724ba675SRob Herring		i2c5 = &i2c5;
25724ba675SRob Herring		i2c6 = &iic3;
26724ba675SRob Herring		spi0 = &qspi;
27724ba675SRob Herring		spi1 = &msiof0;
28724ba675SRob Herring		spi2 = &msiof1;
29724ba675SRob Herring		vin0 = &vin0;
30724ba675SRob Herring		vin1 = &vin1;
31724ba675SRob Herring		vin2 = &vin2;
32724ba675SRob Herring		vin3 = &vin3;
33724ba675SRob Herring		vin4 = &vin4;
34724ba675SRob Herring		vin5 = &vin5;
35724ba675SRob Herring	};
36724ba675SRob Herring
37724ba675SRob Herring	/* External CAN clock */
38724ba675SRob Herring	can_clk: can {
39724ba675SRob Herring		compatible = "fixed-clock";
40724ba675SRob Herring		#clock-cells = <0>;
41724ba675SRob Herring		/* This value must be overridden by the board. */
42724ba675SRob Herring		clock-frequency = <0>;
43724ba675SRob Herring	};
44724ba675SRob Herring
45724ba675SRob Herring	cpus {
46724ba675SRob Herring		#address-cells = <1>;
47724ba675SRob Herring		#size-cells = <0>;
48724ba675SRob Herring
49724ba675SRob Herring		cpu0: cpu@0 {
50724ba675SRob Herring			device_type = "cpu";
51724ba675SRob Herring			compatible = "arm,cortex-a15";
52724ba675SRob Herring			reg = <0>;
53724ba675SRob Herring			clock-frequency = <1000000000>;
54724ba675SRob Herring			clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
55724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
56724ba675SRob Herring			enable-method = "renesas,apmu";
57724ba675SRob Herring			next-level-cache = <&L2_CA15>;
58724ba675SRob Herring		};
59724ba675SRob Herring
60724ba675SRob Herring		cpu1: cpu@1 {
61724ba675SRob Herring			device_type = "cpu";
62724ba675SRob Herring			compatible = "arm,cortex-a15";
63724ba675SRob Herring			reg = <1>;
64724ba675SRob Herring			clock-frequency = <1000000000>;
65724ba675SRob Herring			clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
66724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
67724ba675SRob Herring			enable-method = "renesas,apmu";
68724ba675SRob Herring			next-level-cache = <&L2_CA15>;
69724ba675SRob Herring		};
70724ba675SRob Herring
71724ba675SRob Herring		L2_CA15: cache-controller-0 {
72724ba675SRob Herring			compatible = "cache";
73724ba675SRob Herring			cache-unified;
74724ba675SRob Herring			cache-level = <2>;
75724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_CA15_SCU>;
76724ba675SRob Herring		};
77724ba675SRob Herring	};
78724ba675SRob Herring
79724ba675SRob Herring	/* External root clock */
80724ba675SRob Herring	extal_clk: extal {
81724ba675SRob Herring		compatible = "fixed-clock";
82724ba675SRob Herring		#clock-cells = <0>;
83724ba675SRob Herring		/* This value must be overridden by the board. */
84724ba675SRob Herring		clock-frequency = <0>;
85724ba675SRob Herring	};
86724ba675SRob Herring
87*625d8daaSWolfram Sang	lbsc: bus {
88990da779SGeert Uytterhoeven		compatible = "simple-bus";
89990da779SGeert Uytterhoeven		#address-cells = <1>;
90990da779SGeert Uytterhoeven		#size-cells = <1>;
91990da779SGeert Uytterhoeven		ranges = <0 0 0 0x1c000000>;
92990da779SGeert Uytterhoeven	};
93990da779SGeert Uytterhoeven
94724ba675SRob Herring	pmu {
95724ba675SRob Herring		compatible = "arm,cortex-a15-pmu";
96724ba675SRob Herring		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
97724ba675SRob Herring				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
98724ba675SRob Herring		interrupt-affinity = <&cpu0>, <&cpu1>;
99724ba675SRob Herring	};
100724ba675SRob Herring
101724ba675SRob Herring	/* External SCIF clock */
102724ba675SRob Herring	scif_clk: scif {
103724ba675SRob Herring		compatible = "fixed-clock";
104724ba675SRob Herring		#clock-cells = <0>;
105724ba675SRob Herring		/* This value must be overridden by the board. */
106724ba675SRob Herring		clock-frequency = <0>;
107724ba675SRob Herring	};
108724ba675SRob Herring
109724ba675SRob Herring	soc {
110724ba675SRob Herring		compatible = "simple-bus";
111724ba675SRob Herring		interrupt-parent = <&gic>;
112724ba675SRob Herring
113724ba675SRob Herring		#address-cells = <2>;
114724ba675SRob Herring		#size-cells = <2>;
115724ba675SRob Herring		ranges;
116724ba675SRob Herring
117724ba675SRob Herring		rwdt: watchdog@e6020000 {
118724ba675SRob Herring			compatible = "renesas,r8a7792-wdt",
119724ba675SRob Herring				     "renesas,rcar-gen2-wdt";
120724ba675SRob Herring			reg = <0 0xe6020000 0 0x0c>;
121724ba675SRob Herring			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
122724ba675SRob Herring			clocks = <&cpg CPG_MOD 402>;
123724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
124724ba675SRob Herring			resets = <&cpg 402>;
125724ba675SRob Herring			status = "disabled";
126724ba675SRob Herring		};
127724ba675SRob Herring
128724ba675SRob Herring		gpio0: gpio@e6050000 {
129724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
130724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
131724ba675SRob Herring			reg = <0 0xe6050000 0 0x50>;
132724ba675SRob Herring			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
133724ba675SRob Herring			#gpio-cells = <2>;
134724ba675SRob Herring			gpio-controller;
135724ba675SRob Herring			gpio-ranges = <&pfc 0 0 29>;
136724ba675SRob Herring			#interrupt-cells = <2>;
137724ba675SRob Herring			interrupt-controller;
138724ba675SRob Herring			clocks = <&cpg CPG_MOD 912>;
139724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
140724ba675SRob Herring			resets = <&cpg 912>;
141724ba675SRob Herring		};
142724ba675SRob Herring
143724ba675SRob Herring		gpio1: gpio@e6051000 {
144724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
145724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
146724ba675SRob Herring			reg = <0 0xe6051000 0 0x50>;
147724ba675SRob Herring			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
148724ba675SRob Herring			#gpio-cells = <2>;
149724ba675SRob Herring			gpio-controller;
150724ba675SRob Herring			gpio-ranges = <&pfc 0 32 23>;
151724ba675SRob Herring			#interrupt-cells = <2>;
152724ba675SRob Herring			interrupt-controller;
153724ba675SRob Herring			clocks = <&cpg CPG_MOD 911>;
154724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
155724ba675SRob Herring			resets = <&cpg 911>;
156724ba675SRob Herring		};
157724ba675SRob Herring
158724ba675SRob Herring		gpio2: gpio@e6052000 {
159724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
160724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
161724ba675SRob Herring			reg = <0 0xe6052000 0 0x50>;
162724ba675SRob Herring			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
163724ba675SRob Herring			#gpio-cells = <2>;
164724ba675SRob Herring			gpio-controller;
165724ba675SRob Herring			gpio-ranges = <&pfc 0 64 32>;
166724ba675SRob Herring			#interrupt-cells = <2>;
167724ba675SRob Herring			interrupt-controller;
168724ba675SRob Herring			clocks = <&cpg CPG_MOD 910>;
169724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
170724ba675SRob Herring			resets = <&cpg 910>;
171724ba675SRob Herring		};
172724ba675SRob Herring
173724ba675SRob Herring		gpio3: gpio@e6053000 {
174724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
175724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
176724ba675SRob Herring			reg = <0 0xe6053000 0 0x50>;
177724ba675SRob Herring			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
178724ba675SRob Herring			#gpio-cells = <2>;
179724ba675SRob Herring			gpio-controller;
180724ba675SRob Herring			gpio-ranges = <&pfc 0 96 28>;
181724ba675SRob Herring			#interrupt-cells = <2>;
182724ba675SRob Herring			interrupt-controller;
183724ba675SRob Herring			clocks = <&cpg CPG_MOD 909>;
184724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
185724ba675SRob Herring			resets = <&cpg 909>;
186724ba675SRob Herring		};
187724ba675SRob Herring
188724ba675SRob Herring		gpio4: gpio@e6054000 {
189724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
190724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
191724ba675SRob Herring			reg = <0 0xe6054000 0 0x50>;
192724ba675SRob Herring			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
193724ba675SRob Herring			#gpio-cells = <2>;
194724ba675SRob Herring			gpio-controller;
195724ba675SRob Herring			gpio-ranges = <&pfc 0 128 17>;
196724ba675SRob Herring			#interrupt-cells = <2>;
197724ba675SRob Herring			interrupt-controller;
198724ba675SRob Herring			clocks = <&cpg CPG_MOD 908>;
199724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
200724ba675SRob Herring			resets = <&cpg 908>;
201724ba675SRob Herring		};
202724ba675SRob Herring
203724ba675SRob Herring		gpio5: gpio@e6055000 {
204724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
205724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
206724ba675SRob Herring			reg = <0 0xe6055000 0 0x50>;
207724ba675SRob Herring			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
208724ba675SRob Herring			#gpio-cells = <2>;
209724ba675SRob Herring			gpio-controller;
210724ba675SRob Herring			gpio-ranges = <&pfc 0 160 17>;
211724ba675SRob Herring			#interrupt-cells = <2>;
212724ba675SRob Herring			interrupt-controller;
213724ba675SRob Herring			clocks = <&cpg CPG_MOD 907>;
214724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
215724ba675SRob Herring			resets = <&cpg 907>;
216724ba675SRob Herring		};
217724ba675SRob Herring
218724ba675SRob Herring		gpio6: gpio@e6055100 {
219724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
220724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
221724ba675SRob Herring			reg = <0 0xe6055100 0 0x50>;
222724ba675SRob Herring			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
223724ba675SRob Herring			#gpio-cells = <2>;
224724ba675SRob Herring			gpio-controller;
225724ba675SRob Herring			gpio-ranges = <&pfc 0 192 17>;
226724ba675SRob Herring			#interrupt-cells = <2>;
227724ba675SRob Herring			interrupt-controller;
228724ba675SRob Herring			clocks = <&cpg CPG_MOD 905>;
229724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
230724ba675SRob Herring			resets = <&cpg 905>;
231724ba675SRob Herring		};
232724ba675SRob Herring
233724ba675SRob Herring		gpio7: gpio@e6055200 {
234724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
235724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
236724ba675SRob Herring			reg = <0 0xe6055200 0 0x50>;
237724ba675SRob Herring			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
238724ba675SRob Herring			#gpio-cells = <2>;
239724ba675SRob Herring			gpio-controller;
240724ba675SRob Herring			gpio-ranges = <&pfc 0 224 17>;
241724ba675SRob Herring			#interrupt-cells = <2>;
242724ba675SRob Herring			interrupt-controller;
243724ba675SRob Herring			clocks = <&cpg CPG_MOD 904>;
244724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
245724ba675SRob Herring			resets = <&cpg 904>;
246724ba675SRob Herring		};
247724ba675SRob Herring
248724ba675SRob Herring		gpio8: gpio@e6055300 {
249724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
250724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
251724ba675SRob Herring			reg = <0 0xe6055300 0 0x50>;
252724ba675SRob Herring			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
253724ba675SRob Herring			#gpio-cells = <2>;
254724ba675SRob Herring			gpio-controller;
255724ba675SRob Herring			gpio-ranges = <&pfc 0 256 17>;
256724ba675SRob Herring			#interrupt-cells = <2>;
257724ba675SRob Herring			interrupt-controller;
258724ba675SRob Herring			clocks = <&cpg CPG_MOD 921>;
259724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
260724ba675SRob Herring			resets = <&cpg 921>;
261724ba675SRob Herring		};
262724ba675SRob Herring
263724ba675SRob Herring		gpio9: gpio@e6055400 {
264724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
265724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
266724ba675SRob Herring			reg = <0 0xe6055400 0 0x50>;
267724ba675SRob Herring			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
268724ba675SRob Herring			#gpio-cells = <2>;
269724ba675SRob Herring			gpio-controller;
270724ba675SRob Herring			gpio-ranges = <&pfc 0 288 17>;
271724ba675SRob Herring			#interrupt-cells = <2>;
272724ba675SRob Herring			interrupt-controller;
273724ba675SRob Herring			clocks = <&cpg CPG_MOD 919>;
274724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
275724ba675SRob Herring			resets = <&cpg 919>;
276724ba675SRob Herring		};
277724ba675SRob Herring
278724ba675SRob Herring		gpio10: gpio@e6055500 {
279724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
280724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
281724ba675SRob Herring			reg = <0 0xe6055500 0 0x50>;
282724ba675SRob Herring			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
283724ba675SRob Herring			#gpio-cells = <2>;
284724ba675SRob Herring			gpio-controller;
285724ba675SRob Herring			gpio-ranges = <&pfc 0 320 32>;
286724ba675SRob Herring			#interrupt-cells = <2>;
287724ba675SRob Herring			interrupt-controller;
288724ba675SRob Herring			clocks = <&cpg CPG_MOD 914>;
289724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
290724ba675SRob Herring			resets = <&cpg 914>;
291724ba675SRob Herring		};
292724ba675SRob Herring
293724ba675SRob Herring		gpio11: gpio@e6055600 {
294724ba675SRob Herring			compatible = "renesas,gpio-r8a7792",
295724ba675SRob Herring				     "renesas,rcar-gen2-gpio";
296724ba675SRob Herring			reg = <0 0xe6055600 0 0x50>;
297724ba675SRob Herring			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
298724ba675SRob Herring			#gpio-cells = <2>;
299724ba675SRob Herring			gpio-controller;
300724ba675SRob Herring			gpio-ranges = <&pfc 0 352 30>;
301724ba675SRob Herring			#interrupt-cells = <2>;
302724ba675SRob Herring			interrupt-controller;
303724ba675SRob Herring			clocks = <&cpg CPG_MOD 913>;
304724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
305724ba675SRob Herring			resets = <&cpg 913>;
306724ba675SRob Herring		};
307724ba675SRob Herring
308724ba675SRob Herring		pfc: pinctrl@e6060000 {
309724ba675SRob Herring			compatible = "renesas,pfc-r8a7792";
310724ba675SRob Herring			reg = <0 0xe6060000 0 0x144>;
311724ba675SRob Herring		};
312724ba675SRob Herring
313724ba675SRob Herring		cpg: clock-controller@e6150000 {
314724ba675SRob Herring			compatible = "renesas,r8a7792-cpg-mssr";
315724ba675SRob Herring			reg = <0 0xe6150000 0 0x1000>;
316724ba675SRob Herring			clocks = <&extal_clk>;
317724ba675SRob Herring			clock-names = "extal";
318724ba675SRob Herring			#clock-cells = <2>;
319724ba675SRob Herring			#power-domain-cells = <0>;
320724ba675SRob Herring			#reset-cells = <1>;
321724ba675SRob Herring		};
322724ba675SRob Herring
323724ba675SRob Herring		apmu@e6152000 {
324724ba675SRob Herring			compatible = "renesas,r8a7792-apmu", "renesas,apmu";
325724ba675SRob Herring			reg = <0 0xe6152000 0 0x188>;
326724ba675SRob Herring			cpus = <&cpu0>, <&cpu1>;
327724ba675SRob Herring		};
328724ba675SRob Herring
329724ba675SRob Herring		rst: reset-controller@e6160000 {
330724ba675SRob Herring			compatible = "renesas,r8a7792-rst";
331724ba675SRob Herring			reg = <0 0xe6160000 0 0x0100>;
332724ba675SRob Herring		};
333724ba675SRob Herring
334724ba675SRob Herring		sysc: system-controller@e6180000 {
335724ba675SRob Herring			compatible = "renesas,r8a7792-sysc";
336724ba675SRob Herring			reg = <0 0xe6180000 0 0x0200>;
337724ba675SRob Herring			#power-domain-cells = <1>;
338724ba675SRob Herring		};
339724ba675SRob Herring
340724ba675SRob Herring		irqc: interrupt-controller@e61c0000 {
341724ba675SRob Herring			compatible = "renesas,irqc-r8a7792", "renesas,irqc";
342724ba675SRob Herring			#interrupt-cells = <2>;
343724ba675SRob Herring			interrupt-controller;
344724ba675SRob Herring			reg = <0 0xe61c0000 0 0x200>;
345724ba675SRob Herring			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
346724ba675SRob Herring				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
347724ba675SRob Herring				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
348724ba675SRob Herring				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
349724ba675SRob Herring			clocks = <&cpg CPG_MOD 407>;
350724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
351724ba675SRob Herring			resets = <&cpg 407>;
352724ba675SRob Herring		};
353724ba675SRob Herring
354b320e8c5SGeert Uytterhoeven		tmu0: timer@e61e0000 {
355b320e8c5SGeert Uytterhoeven			compatible = "renesas,tmu-r8a7792", "renesas,tmu";
356b320e8c5SGeert Uytterhoeven			reg = <0 0xe61e0000 0 0x30>;
357b320e8c5SGeert Uytterhoeven			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
358b320e8c5SGeert Uytterhoeven				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
359b320e8c5SGeert Uytterhoeven				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
360b320e8c5SGeert Uytterhoeven			interrupt-names = "tuni0", "tuni1", "tuni2";
361b320e8c5SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 125>;
362b320e8c5SGeert Uytterhoeven			clock-names = "fck";
363b320e8c5SGeert Uytterhoeven			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
364b320e8c5SGeert Uytterhoeven			resets = <&cpg 125>;
365b320e8c5SGeert Uytterhoeven			status = "disabled";
366b320e8c5SGeert Uytterhoeven		};
367b320e8c5SGeert Uytterhoeven
368b320e8c5SGeert Uytterhoeven		tmu1: timer@fff60000 {
369b320e8c5SGeert Uytterhoeven			compatible = "renesas,tmu-r8a7792", "renesas,tmu";
370b320e8c5SGeert Uytterhoeven			reg = <0 0xfff60000 0 0x30>;
371b320e8c5SGeert Uytterhoeven			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
372b320e8c5SGeert Uytterhoeven				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
373b320e8c5SGeert Uytterhoeven				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
374b320e8c5SGeert Uytterhoeven				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
375b320e8c5SGeert Uytterhoeven			interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
376b320e8c5SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 111>;
377b320e8c5SGeert Uytterhoeven			clock-names = "fck";
378b320e8c5SGeert Uytterhoeven			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
379b320e8c5SGeert Uytterhoeven			resets = <&cpg 111>;
380b320e8c5SGeert Uytterhoeven			status = "disabled";
381b320e8c5SGeert Uytterhoeven		};
382b320e8c5SGeert Uytterhoeven
383b320e8c5SGeert Uytterhoeven		tmu2: timer@fff70000 {
384b320e8c5SGeert Uytterhoeven			compatible = "renesas,tmu-r8a7792", "renesas,tmu";
385b320e8c5SGeert Uytterhoeven			reg = <0 0xfff70000 0 0x30>;
386b320e8c5SGeert Uytterhoeven			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
387b320e8c5SGeert Uytterhoeven				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
388b320e8c5SGeert Uytterhoeven				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
389b320e8c5SGeert Uytterhoeven				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
390b320e8c5SGeert Uytterhoeven			interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
391b320e8c5SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 122>;
392b320e8c5SGeert Uytterhoeven			clock-names = "fck";
393b320e8c5SGeert Uytterhoeven			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
394b320e8c5SGeert Uytterhoeven			resets = <&cpg 122>;
395b320e8c5SGeert Uytterhoeven			status = "disabled";
396b320e8c5SGeert Uytterhoeven		};
397b320e8c5SGeert Uytterhoeven
398b320e8c5SGeert Uytterhoeven		tmu3: timer@fff80000 {
399b320e8c5SGeert Uytterhoeven			compatible = "renesas,tmu-r8a7792", "renesas,tmu";
400b320e8c5SGeert Uytterhoeven			reg = <0 0xfff80000 0 0x30>;
401b320e8c5SGeert Uytterhoeven			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
402b320e8c5SGeert Uytterhoeven				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
403b320e8c5SGeert Uytterhoeven				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
404b320e8c5SGeert Uytterhoeven				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
405b320e8c5SGeert Uytterhoeven			interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
406b320e8c5SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 121>;
407b320e8c5SGeert Uytterhoeven			clock-names = "fck";
408b320e8c5SGeert Uytterhoeven			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
409b320e8c5SGeert Uytterhoeven			resets = <&cpg 121>;
410b320e8c5SGeert Uytterhoeven			status = "disabled";
411b320e8c5SGeert Uytterhoeven		};
412b320e8c5SGeert Uytterhoeven
413724ba675SRob Herring		icram0:	sram@e63a0000 {
414724ba675SRob Herring			compatible = "mmio-sram";
415724ba675SRob Herring			reg = <0 0xe63a0000 0 0x12000>;
416724ba675SRob Herring			#address-cells = <1>;
417724ba675SRob Herring			#size-cells = <1>;
418724ba675SRob Herring			ranges = <0 0 0xe63a0000 0x12000>;
419724ba675SRob Herring		};
420724ba675SRob Herring
421724ba675SRob Herring		icram1:	sram@e63c0000 {
422724ba675SRob Herring			compatible = "mmio-sram";
423724ba675SRob Herring			reg = <0 0xe63c0000 0 0x1000>;
424724ba675SRob Herring			#address-cells = <1>;
425724ba675SRob Herring			#size-cells = <1>;
426724ba675SRob Herring			ranges = <0 0 0xe63c0000 0x1000>;
427724ba675SRob Herring
428724ba675SRob Herring			smp-sram@0 {
429724ba675SRob Herring				compatible = "renesas,smp-sram";
430724ba675SRob Herring				reg = <0 0x100>;
431724ba675SRob Herring			};
432724ba675SRob Herring		};
433724ba675SRob Herring
434724ba675SRob Herring		/* I2C doesn't need pinmux */
435724ba675SRob Herring		i2c0: i2c@e6508000 {
436724ba675SRob Herring			compatible = "renesas,i2c-r8a7792",
437724ba675SRob Herring				     "renesas,rcar-gen2-i2c";
438724ba675SRob Herring			reg = <0 0xe6508000 0 0x40>;
439724ba675SRob Herring			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
440724ba675SRob Herring			clocks = <&cpg CPG_MOD 931>;
441724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
442724ba675SRob Herring			resets = <&cpg 931>;
443724ba675SRob Herring			i2c-scl-internal-delay-ns = <6>;
444724ba675SRob Herring			#address-cells = <1>;
445724ba675SRob Herring			#size-cells = <0>;
446724ba675SRob Herring			status = "disabled";
447724ba675SRob Herring		};
448724ba675SRob Herring
449724ba675SRob Herring		i2c1: i2c@e6518000 {
450724ba675SRob Herring			compatible = "renesas,i2c-r8a7792",
451724ba675SRob Herring				     "renesas,rcar-gen2-i2c";
452724ba675SRob Herring			reg = <0 0xe6518000 0 0x40>;
453724ba675SRob Herring			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
454724ba675SRob Herring			clocks = <&cpg CPG_MOD 930>;
455724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
456724ba675SRob Herring			resets = <&cpg 930>;
457724ba675SRob Herring			i2c-scl-internal-delay-ns = <6>;
458724ba675SRob Herring			#address-cells = <1>;
459724ba675SRob Herring			#size-cells = <0>;
460724ba675SRob Herring			status = "disabled";
461724ba675SRob Herring		};
462724ba675SRob Herring
463724ba675SRob Herring		i2c2: i2c@e6530000 {
464724ba675SRob Herring			compatible = "renesas,i2c-r8a7792",
465724ba675SRob Herring				     "renesas,rcar-gen2-i2c";
466724ba675SRob Herring			reg = <0 0xe6530000 0 0x40>;
467724ba675SRob Herring			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
468724ba675SRob Herring			clocks = <&cpg CPG_MOD 929>;
469724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
470724ba675SRob Herring			resets = <&cpg 929>;
471724ba675SRob Herring			i2c-scl-internal-delay-ns = <6>;
472724ba675SRob Herring			#address-cells = <1>;
473724ba675SRob Herring			#size-cells = <0>;
474724ba675SRob Herring			status = "disabled";
475724ba675SRob Herring		};
476724ba675SRob Herring
477724ba675SRob Herring		i2c3: i2c@e6540000 {
478724ba675SRob Herring			compatible = "renesas,i2c-r8a7792",
479724ba675SRob Herring				     "renesas,rcar-gen2-i2c";
480724ba675SRob Herring			reg = <0 0xe6540000 0 0x40>;
481724ba675SRob Herring			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
482724ba675SRob Herring			clocks = <&cpg CPG_MOD 928>;
483724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
484724ba675SRob Herring			resets = <&cpg 928>;
485724ba675SRob Herring			i2c-scl-internal-delay-ns = <6>;
486724ba675SRob Herring			#address-cells = <1>;
487724ba675SRob Herring			#size-cells = <0>;
488724ba675SRob Herring			status = "disabled";
489724ba675SRob Herring		};
490724ba675SRob Herring
491724ba675SRob Herring		i2c4: i2c@e6520000 {
492724ba675SRob Herring			compatible = "renesas,i2c-r8a7792",
493724ba675SRob Herring				     "renesas,rcar-gen2-i2c";
494724ba675SRob Herring			reg = <0 0xe6520000 0 0x40>;
495724ba675SRob Herring			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
496724ba675SRob Herring			clocks = <&cpg CPG_MOD 927>;
497724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
498724ba675SRob Herring			resets = <&cpg 927>;
499724ba675SRob Herring			i2c-scl-internal-delay-ns = <6>;
500724ba675SRob Herring			#address-cells = <1>;
501724ba675SRob Herring			#size-cells = <0>;
502724ba675SRob Herring			status = "disabled";
503724ba675SRob Herring		};
504724ba675SRob Herring
505724ba675SRob Herring		i2c5: i2c@e6528000 {
506724ba675SRob Herring			compatible = "renesas,i2c-r8a7792",
507724ba675SRob Herring				     "renesas,rcar-gen2-i2c";
508724ba675SRob Herring			reg = <0 0xe6528000 0 0x40>;
509724ba675SRob Herring			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
510724ba675SRob Herring			clocks = <&cpg CPG_MOD 925>;
511724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
512724ba675SRob Herring			resets = <&cpg 925>;
513724ba675SRob Herring			i2c-scl-internal-delay-ns = <110>;
514724ba675SRob Herring			#address-cells = <1>;
515724ba675SRob Herring			#size-cells = <0>;
516724ba675SRob Herring			status = "disabled";
517724ba675SRob Herring		};
518724ba675SRob Herring
519724ba675SRob Herring		iic3: i2c@e60b0000 {
520724ba675SRob Herring			#address-cells = <1>;
521724ba675SRob Herring			#size-cells = <0>;
522724ba675SRob Herring			compatible = "renesas,iic-r8a7792",
523724ba675SRob Herring				     "renesas,rcar-gen2-iic",
524724ba675SRob Herring				     "renesas,rmobile-iic";
525724ba675SRob Herring			reg = <0 0xe60b0000 0 0x425>;
526724ba675SRob Herring			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
527724ba675SRob Herring			clocks = <&cpg CPG_MOD 926>;
528724ba675SRob Herring			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
529724ba675SRob Herring			       <&dmac1 0x77>, <&dmac1 0x78>;
530724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
531724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
532724ba675SRob Herring			resets = <&cpg 926>;
533724ba675SRob Herring			status = "disabled";
534724ba675SRob Herring		};
535724ba675SRob Herring
536724ba675SRob Herring		dmac0: dma-controller@e6700000 {
537724ba675SRob Herring			compatible = "renesas,dmac-r8a7792",
538724ba675SRob Herring				     "renesas,rcar-dmac";
539724ba675SRob Herring			reg = <0 0xe6700000 0 0x20000>;
540724ba675SRob Herring			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
541724ba675SRob Herring				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
542724ba675SRob Herring				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
543724ba675SRob Herring				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
544724ba675SRob Herring				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
545724ba675SRob Herring				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
546724ba675SRob Herring				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
547724ba675SRob Herring				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
548724ba675SRob Herring				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
549724ba675SRob Herring				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
550724ba675SRob Herring				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
551724ba675SRob Herring				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
552724ba675SRob Herring				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
553724ba675SRob Herring				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
554724ba675SRob Herring				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
555724ba675SRob Herring				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
556724ba675SRob Herring			interrupt-names = "error",
557724ba675SRob Herring					  "ch0", "ch1", "ch2", "ch3",
558724ba675SRob Herring					  "ch4", "ch5", "ch6", "ch7",
559724ba675SRob Herring					  "ch8", "ch9", "ch10", "ch11",
560724ba675SRob Herring					  "ch12", "ch13", "ch14";
561724ba675SRob Herring			clocks = <&cpg CPG_MOD 219>;
562724ba675SRob Herring			clock-names = "fck";
563724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
564724ba675SRob Herring			resets = <&cpg 219>;
565724ba675SRob Herring			#dma-cells = <1>;
566724ba675SRob Herring			dma-channels = <15>;
567724ba675SRob Herring		};
568724ba675SRob Herring
569724ba675SRob Herring		dmac1: dma-controller@e6720000 {
570724ba675SRob Herring			compatible = "renesas,dmac-r8a7792",
571724ba675SRob Herring				     "renesas,rcar-dmac";
572724ba675SRob Herring			reg = <0 0xe6720000 0 0x20000>;
573724ba675SRob Herring			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
574724ba675SRob Herring				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
575724ba675SRob Herring				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
576724ba675SRob Herring				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
577724ba675SRob Herring				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
578724ba675SRob Herring				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
579724ba675SRob Herring				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
580724ba675SRob Herring				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
581724ba675SRob Herring				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
582724ba675SRob Herring				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
583724ba675SRob Herring				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
584724ba675SRob Herring				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
585724ba675SRob Herring				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
586724ba675SRob Herring				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
587724ba675SRob Herring				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
588724ba675SRob Herring				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
589724ba675SRob Herring			interrupt-names = "error",
590724ba675SRob Herring					  "ch0", "ch1", "ch2", "ch3",
591724ba675SRob Herring					  "ch4", "ch5", "ch6", "ch7",
592724ba675SRob Herring					  "ch8", "ch9", "ch10", "ch11",
593724ba675SRob Herring					  "ch12", "ch13", "ch14";
594724ba675SRob Herring			clocks = <&cpg CPG_MOD 218>;
595724ba675SRob Herring			clock-names = "fck";
596724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
597724ba675SRob Herring			resets = <&cpg 218>;
598724ba675SRob Herring			#dma-cells = <1>;
599724ba675SRob Herring			dma-channels = <15>;
600724ba675SRob Herring		};
601724ba675SRob Herring
602724ba675SRob Herring		avb: ethernet@e6800000 {
603724ba675SRob Herring			compatible = "renesas,etheravb-r8a7792",
604724ba675SRob Herring				     "renesas,etheravb-rcar-gen2";
605724ba675SRob Herring			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
606724ba675SRob Herring			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
607724ba675SRob Herring			clocks = <&cpg CPG_MOD 812>;
608724ba675SRob Herring			clock-names = "fck";
609724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
610724ba675SRob Herring			resets = <&cpg 812>;
611724ba675SRob Herring			#address-cells = <1>;
612724ba675SRob Herring			#size-cells = <0>;
613724ba675SRob Herring			status = "disabled";
614724ba675SRob Herring		};
615724ba675SRob Herring
616724ba675SRob Herring		qspi: spi@e6b10000 {
617724ba675SRob Herring			compatible = "renesas,qspi-r8a7792", "renesas,qspi";
618724ba675SRob Herring			reg = <0 0xe6b10000 0 0x2c>;
619724ba675SRob Herring			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
620724ba675SRob Herring			clocks = <&cpg CPG_MOD 917>;
621724ba675SRob Herring			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
622724ba675SRob Herring			       <&dmac1 0x17>, <&dmac1 0x18>;
623724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
624724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
625724ba675SRob Herring			resets = <&cpg 917>;
626724ba675SRob Herring			num-cs = <1>;
627724ba675SRob Herring			#address-cells = <1>;
628724ba675SRob Herring			#size-cells = <0>;
629724ba675SRob Herring			status = "disabled";
630724ba675SRob Herring		};
631724ba675SRob Herring
632724ba675SRob Herring		scif0: serial@e6e60000 {
633724ba675SRob Herring			compatible = "renesas,scif-r8a7792",
634724ba675SRob Herring				     "renesas,rcar-gen2-scif", "renesas,scif";
635724ba675SRob Herring			reg = <0 0xe6e60000 0 64>;
636724ba675SRob Herring			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
637724ba675SRob Herring			clocks = <&cpg CPG_MOD 721>,
638724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
639724ba675SRob Herring			clock-names = "fck", "brg_int", "scif_clk";
640724ba675SRob Herring			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
641724ba675SRob Herring			       <&dmac1 0x29>, <&dmac1 0x2a>;
642724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
643724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
644724ba675SRob Herring			resets = <&cpg 721>;
645724ba675SRob Herring			status = "disabled";
646724ba675SRob Herring		};
647724ba675SRob Herring
648724ba675SRob Herring		scif1: serial@e6e68000 {
649724ba675SRob Herring			compatible = "renesas,scif-r8a7792",
650724ba675SRob Herring				     "renesas,rcar-gen2-scif", "renesas,scif";
651724ba675SRob Herring			reg = <0 0xe6e68000 0 64>;
652724ba675SRob Herring			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
653724ba675SRob Herring			clocks = <&cpg CPG_MOD 720>,
654724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
655724ba675SRob Herring			clock-names = "fck", "brg_int", "scif_clk";
656724ba675SRob Herring			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
657724ba675SRob Herring			       <&dmac1 0x2d>, <&dmac1 0x2e>;
658724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
659724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
660724ba675SRob Herring			resets = <&cpg 720>;
661724ba675SRob Herring			status = "disabled";
662724ba675SRob Herring		};
663724ba675SRob Herring
664724ba675SRob Herring		scif2: serial@e6e58000 {
665724ba675SRob Herring			compatible = "renesas,scif-r8a7792",
666724ba675SRob Herring				     "renesas,rcar-gen2-scif", "renesas,scif";
667724ba675SRob Herring			reg = <0 0xe6e58000 0 64>;
668724ba675SRob Herring			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
669724ba675SRob Herring			clocks = <&cpg CPG_MOD 719>,
670724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
671724ba675SRob Herring			clock-names = "fck", "brg_int", "scif_clk";
672724ba675SRob Herring			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
673724ba675SRob Herring			       <&dmac1 0x2b>, <&dmac1 0x2c>;
674724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
675724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
676724ba675SRob Herring			resets = <&cpg 719>;
677724ba675SRob Herring			status = "disabled";
678724ba675SRob Herring		};
679724ba675SRob Herring
680724ba675SRob Herring		scif3: serial@e6ea8000 {
681724ba675SRob Herring			compatible = "renesas,scif-r8a7792",
682724ba675SRob Herring				     "renesas,rcar-gen2-scif", "renesas,scif";
683724ba675SRob Herring			reg = <0 0xe6ea8000 0 64>;
684724ba675SRob Herring			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
685724ba675SRob Herring			clocks = <&cpg CPG_MOD 718>,
686724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
687724ba675SRob Herring			clock-names = "fck", "brg_int", "scif_clk";
688724ba675SRob Herring			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
689724ba675SRob Herring			       <&dmac1 0x2f>, <&dmac1 0x30>;
690724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
691724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
692724ba675SRob Herring			resets = <&cpg 718>;
693724ba675SRob Herring			status = "disabled";
694724ba675SRob Herring		};
695724ba675SRob Herring
696724ba675SRob Herring		hscif0: serial@e62c0000 {
697724ba675SRob Herring			compatible = "renesas,hscif-r8a7792",
698724ba675SRob Herring				     "renesas,rcar-gen2-hscif", "renesas,hscif";
699724ba675SRob Herring			reg = <0 0xe62c0000 0 96>;
700724ba675SRob Herring			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
701724ba675SRob Herring			clocks = <&cpg CPG_MOD 717>,
702724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
703724ba675SRob Herring			clock-names = "fck", "brg_int", "scif_clk";
704724ba675SRob Herring			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
705724ba675SRob Herring			       <&dmac1 0x39>, <&dmac1 0x3a>;
706724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
707724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
708724ba675SRob Herring			resets = <&cpg 717>;
709724ba675SRob Herring			status = "disabled";
710724ba675SRob Herring		};
711724ba675SRob Herring
712724ba675SRob Herring		hscif1: serial@e62c8000 {
713724ba675SRob Herring			compatible = "renesas,hscif-r8a7792",
714724ba675SRob Herring				     "renesas,rcar-gen2-hscif", "renesas,hscif";
715724ba675SRob Herring			reg = <0 0xe62c8000 0 96>;
716724ba675SRob Herring			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
717724ba675SRob Herring			clocks = <&cpg CPG_MOD 716>,
718724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
719724ba675SRob Herring			clock-names = "fck", "brg_int", "scif_clk";
720724ba675SRob Herring			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
721724ba675SRob Herring			       <&dmac1 0x4d>, <&dmac1 0x4e>;
722724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
723724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
724724ba675SRob Herring			resets = <&cpg 716>;
725724ba675SRob Herring			status = "disabled";
726724ba675SRob Herring		};
727724ba675SRob Herring
728724ba675SRob Herring		msiof0: spi@e6e20000 {
729724ba675SRob Herring			compatible = "renesas,msiof-r8a7792",
730724ba675SRob Herring				     "renesas,rcar-gen2-msiof";
731724ba675SRob Herring			reg = <0 0xe6e20000 0 0x0064>;
732724ba675SRob Herring			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
733724ba675SRob Herring			clocks = <&cpg CPG_MOD 000>;
734724ba675SRob Herring			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
735724ba675SRob Herring			       <&dmac1 0x51>, <&dmac1 0x52>;
736724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
737724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
738724ba675SRob Herring			resets = <&cpg 000>;
739724ba675SRob Herring			#address-cells = <1>;
740724ba675SRob Herring			#size-cells = <0>;
741724ba675SRob Herring			status = "disabled";
742724ba675SRob Herring		};
743724ba675SRob Herring
744724ba675SRob Herring		msiof1: spi@e6e10000 {
745724ba675SRob Herring			compatible = "renesas,msiof-r8a7792",
746724ba675SRob Herring				     "renesas,rcar-gen2-msiof";
747724ba675SRob Herring			reg = <0 0xe6e10000 0 0x0064>;
748724ba675SRob Herring			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
749724ba675SRob Herring			clocks = <&cpg CPG_MOD 208>;
750724ba675SRob Herring			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
751724ba675SRob Herring			       <&dmac1 0x55>, <&dmac1 0x56>;
752724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
753724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
754724ba675SRob Herring			resets = <&cpg 208>;
755724ba675SRob Herring			#address-cells = <1>;
756724ba675SRob Herring			#size-cells = <0>;
757724ba675SRob Herring			status = "disabled";
758724ba675SRob Herring		};
759724ba675SRob Herring
760724ba675SRob Herring		can0: can@e6e80000 {
761724ba675SRob Herring			compatible = "renesas,can-r8a7792",
762724ba675SRob Herring				     "renesas,rcar-gen2-can";
763724ba675SRob Herring			reg = <0 0xe6e80000 0 0x1000>;
764724ba675SRob Herring			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
765724ba675SRob Herring			clocks = <&cpg CPG_MOD 916>,
766724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
767724ba675SRob Herring			clock-names = "clkp1", "clkp2", "can_clk";
768724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
769724ba675SRob Herring			resets = <&cpg 916>;
770724ba675SRob Herring			status = "disabled";
771724ba675SRob Herring		};
772724ba675SRob Herring
773724ba675SRob Herring		can1: can@e6e88000 {
774724ba675SRob Herring			compatible = "renesas,can-r8a7792",
775724ba675SRob Herring				     "renesas,rcar-gen2-can";
776724ba675SRob Herring			reg = <0 0xe6e88000 0 0x1000>;
777724ba675SRob Herring			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
778724ba675SRob Herring			clocks = <&cpg CPG_MOD 915>,
779724ba675SRob Herring				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
780724ba675SRob Herring			clock-names = "clkp1", "clkp2", "can_clk";
781724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
782724ba675SRob Herring			resets = <&cpg 915>;
783724ba675SRob Herring			status = "disabled";
784724ba675SRob Herring		};
785724ba675SRob Herring
786724ba675SRob Herring		vin0: video@e6ef0000 {
787724ba675SRob Herring			compatible = "renesas,vin-r8a7792",
788724ba675SRob Herring				     "renesas,rcar-gen2-vin";
789724ba675SRob Herring			reg = <0 0xe6ef0000 0 0x1000>;
790724ba675SRob Herring			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
791724ba675SRob Herring			clocks = <&cpg CPG_MOD 811>;
792724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
793724ba675SRob Herring			resets = <&cpg 811>;
794724ba675SRob Herring			status = "disabled";
795724ba675SRob Herring		};
796724ba675SRob Herring
797724ba675SRob Herring		vin1: video@e6ef1000 {
798724ba675SRob Herring			compatible = "renesas,vin-r8a7792",
799724ba675SRob Herring				     "renesas,rcar-gen2-vin";
800724ba675SRob Herring			reg = <0 0xe6ef1000 0 0x1000>;
801724ba675SRob Herring			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
802724ba675SRob Herring			clocks = <&cpg CPG_MOD 810>;
803724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
804724ba675SRob Herring			resets = <&cpg 810>;
805724ba675SRob Herring			status = "disabled";
806724ba675SRob Herring		};
807724ba675SRob Herring
808724ba675SRob Herring		vin2: video@e6ef2000 {
809724ba675SRob Herring			compatible = "renesas,vin-r8a7792",
810724ba675SRob Herring				     "renesas,rcar-gen2-vin";
811724ba675SRob Herring			reg = <0 0xe6ef2000 0 0x1000>;
812724ba675SRob Herring			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
813724ba675SRob Herring			clocks = <&cpg CPG_MOD 809>;
814724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
815724ba675SRob Herring			resets = <&cpg 809>;
816724ba675SRob Herring			status = "disabled";
817724ba675SRob Herring		};
818724ba675SRob Herring
819724ba675SRob Herring		vin3: video@e6ef3000 {
820724ba675SRob Herring			compatible = "renesas,vin-r8a7792",
821724ba675SRob Herring				     "renesas,rcar-gen2-vin";
822724ba675SRob Herring			reg = <0 0xe6ef3000 0 0x1000>;
823724ba675SRob Herring			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
824724ba675SRob Herring			clocks = <&cpg CPG_MOD 808>;
825724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
826724ba675SRob Herring			resets = <&cpg 808>;
827724ba675SRob Herring			status = "disabled";
828724ba675SRob Herring		};
829724ba675SRob Herring
830724ba675SRob Herring		vin4: video@e6ef4000 {
831724ba675SRob Herring			compatible = "renesas,vin-r8a7792",
832724ba675SRob Herring				     "renesas,rcar-gen2-vin";
833724ba675SRob Herring			reg = <0 0xe6ef4000 0 0x1000>;
834724ba675SRob Herring			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
835724ba675SRob Herring			clocks = <&cpg CPG_MOD 805>;
836724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
837724ba675SRob Herring			resets = <&cpg 805>;
838724ba675SRob Herring			status = "disabled";
839724ba675SRob Herring		};
840724ba675SRob Herring
841724ba675SRob Herring		vin5: video@e6ef5000 {
842724ba675SRob Herring			compatible = "renesas,vin-r8a7792",
843724ba675SRob Herring				     "renesas,rcar-gen2-vin";
844724ba675SRob Herring			reg = <0 0xe6ef5000 0 0x1000>;
845724ba675SRob Herring			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
846724ba675SRob Herring			clocks = <&cpg CPG_MOD 804>;
847724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
848724ba675SRob Herring			resets = <&cpg 804>;
849724ba675SRob Herring			status = "disabled";
850724ba675SRob Herring		};
851724ba675SRob Herring
852724ba675SRob Herring		sdhi0: mmc@ee100000 {
853724ba675SRob Herring			compatible = "renesas,sdhi-r8a7792",
854724ba675SRob Herring				     "renesas,rcar-gen2-sdhi";
855724ba675SRob Herring			reg = <0 0xee100000 0 0x328>;
856724ba675SRob Herring			interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
857724ba675SRob Herring			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
858724ba675SRob Herring			       <&dmac1 0xcd>, <&dmac1 0xce>;
859724ba675SRob Herring			dma-names = "tx", "rx", "tx", "rx";
860724ba675SRob Herring			clocks = <&cpg CPG_MOD 314>;
861724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
862724ba675SRob Herring			resets = <&cpg 314>;
863724ba675SRob Herring			status = "disabled";
864724ba675SRob Herring		};
865724ba675SRob Herring
866724ba675SRob Herring		gic: interrupt-controller@f1001000 {
867724ba675SRob Herring			compatible = "arm,gic-400";
868724ba675SRob Herring			#interrupt-cells = <3>;
869724ba675SRob Herring			interrupt-controller;
870724ba675SRob Herring			reg = <0 0xf1001000 0 0x1000>,
871724ba675SRob Herring			      <0 0xf1002000 0 0x2000>,
872724ba675SRob Herring			      <0 0xf1004000 0 0x2000>,
873724ba675SRob Herring			      <0 0xf1006000 0 0x2000>;
874724ba675SRob Herring			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
875724ba675SRob Herring				      IRQ_TYPE_LEVEL_HIGH)>;
876724ba675SRob Herring			clocks = <&cpg CPG_MOD 408>;
877724ba675SRob Herring			clock-names = "clk";
878724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
879724ba675SRob Herring			resets = <&cpg 408>;
880724ba675SRob Herring		};
881724ba675SRob Herring
882724ba675SRob Herring		vsp@fe928000 {
883724ba675SRob Herring			compatible = "renesas,vsp1";
884724ba675SRob Herring			reg = <0 0xfe928000 0 0x8000>;
885724ba675SRob Herring			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
886724ba675SRob Herring			clocks = <&cpg CPG_MOD 131>;
887724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
888724ba675SRob Herring			resets = <&cpg 131>;
889724ba675SRob Herring		};
890724ba675SRob Herring
891724ba675SRob Herring		vsp@fe930000 {
892724ba675SRob Herring			compatible = "renesas,vsp1";
893724ba675SRob Herring			reg = <0 0xfe930000 0 0x8000>;
894724ba675SRob Herring			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
895724ba675SRob Herring			clocks = <&cpg CPG_MOD 128>;
896724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
897724ba675SRob Herring			resets = <&cpg 128>;
898724ba675SRob Herring		};
899724ba675SRob Herring
900724ba675SRob Herring		vsp@fe938000 {
901724ba675SRob Herring			compatible = "renesas,vsp1";
902724ba675SRob Herring			reg = <0 0xfe938000 0 0x8000>;
903724ba675SRob Herring			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
904724ba675SRob Herring			clocks = <&cpg CPG_MOD 127>;
905724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
906724ba675SRob Herring			resets = <&cpg 127>;
907724ba675SRob Herring		};
908724ba675SRob Herring
909724ba675SRob Herring		jpu: jpeg-codec@fe980000 {
910724ba675SRob Herring			compatible = "renesas,jpu-r8a7792",
911724ba675SRob Herring				     "renesas,rcar-gen2-jpu";
912724ba675SRob Herring			reg = <0 0xfe980000 0 0x10300>;
913724ba675SRob Herring			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
914724ba675SRob Herring			clocks = <&cpg CPG_MOD 106>;
915724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
916724ba675SRob Herring			resets = <&cpg 106>;
917724ba675SRob Herring		};
918724ba675SRob Herring
919724ba675SRob Herring		du: display@feb00000 {
920724ba675SRob Herring			compatible = "renesas,du-r8a7792";
921724ba675SRob Herring			reg = <0 0xfeb00000 0 0x40000>;
922724ba675SRob Herring			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
923724ba675SRob Herring				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
924724ba675SRob Herring			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
925724ba675SRob Herring			clock-names = "du.0", "du.1";
926724ba675SRob Herring			resets = <&cpg 724>;
927724ba675SRob Herring			reset-names = "du.0";
928724ba675SRob Herring			status = "disabled";
929724ba675SRob Herring
930724ba675SRob Herring			ports {
931724ba675SRob Herring				#address-cells = <1>;
932724ba675SRob Herring				#size-cells = <0>;
933724ba675SRob Herring
934724ba675SRob Herring				port@0 {
935724ba675SRob Herring					reg = <0>;
936724ba675SRob Herring					du_out_rgb0: endpoint {
937724ba675SRob Herring					};
938724ba675SRob Herring				};
939724ba675SRob Herring				port@1 {
940724ba675SRob Herring					reg = <1>;
941724ba675SRob Herring					du_out_rgb1: endpoint {
942724ba675SRob Herring					};
943724ba675SRob Herring				};
944724ba675SRob Herring			};
945724ba675SRob Herring		};
946724ba675SRob Herring
947724ba675SRob Herring		prr: chipid@ff000044 {
948724ba675SRob Herring			compatible = "renesas,prr";
949724ba675SRob Herring			reg = <0 0xff000044 0 4>;
950724ba675SRob Herring		};
951724ba675SRob Herring
952724ba675SRob Herring		cmt0: timer@ffca0000 {
953724ba675SRob Herring			compatible = "renesas,r8a7792-cmt0",
954724ba675SRob Herring				     "renesas,rcar-gen2-cmt0";
955724ba675SRob Herring			reg = <0 0xffca0000 0 0x1004>;
956724ba675SRob Herring			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
957724ba675SRob Herring				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
958724ba675SRob Herring			clocks = <&cpg CPG_MOD 124>;
959724ba675SRob Herring			clock-names = "fck";
960724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
961724ba675SRob Herring			resets = <&cpg 124>;
962724ba675SRob Herring
963724ba675SRob Herring			status = "disabled";
964724ba675SRob Herring		};
965724ba675SRob Herring
966724ba675SRob Herring		cmt1: timer@e6130000 {
967724ba675SRob Herring			compatible = "renesas,r8a7792-cmt1",
968724ba675SRob Herring				     "renesas,rcar-gen2-cmt1";
969724ba675SRob Herring			reg = <0 0xe6130000 0 0x1004>;
970724ba675SRob Herring			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
971724ba675SRob Herring				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
972724ba675SRob Herring				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
973724ba675SRob Herring				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
974724ba675SRob Herring				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
975724ba675SRob Herring				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
976724ba675SRob Herring				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
977724ba675SRob Herring				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
978724ba675SRob Herring			clocks = <&cpg CPG_MOD 329>;
979724ba675SRob Herring			clock-names = "fck";
980724ba675SRob Herring			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
981724ba675SRob Herring			resets = <&cpg 329>;
982724ba675SRob Herring
983724ba675SRob Herring			status = "disabled";
984724ba675SRob Herring		};
985724ba675SRob Herring	};
986724ba675SRob Herring
987724ba675SRob Herring	timer {
988724ba675SRob Herring		compatible = "arm,armv7-timer";
989724ba675SRob Herring		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
990724ba675SRob Herring				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
991724ba675SRob Herring				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
992724ba675SRob Herring				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
9939d30bd7bSGeert Uytterhoeven		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
994724ba675SRob Herring	};
995724ba675SRob Herring};
996