xref: /linux/scripts/dtc/include-prefixes/arm/renesas/r8a73a4.dtsi (revision 60675d4ca1ef0857e44eba5849b74a3a998d0c0f)
1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2724ba675SRob Herring/*
3724ba675SRob Herring * Device Tree Source for the r8a73a4 SoC
4724ba675SRob Herring *
5724ba675SRob Herring * Copyright (C) 2013 Renesas Solutions Corp.
6724ba675SRob Herring * Copyright (C) 2013 Magnus Damm
7724ba675SRob Herring */
8724ba675SRob Herring
9724ba675SRob Herring#include <dt-bindings/clock/r8a73a4-clock.h>
10724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h>
11724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h>
12724ba675SRob Herring
13724ba675SRob Herring/ {
14724ba675SRob Herring	compatible = "renesas,r8a73a4";
15724ba675SRob Herring	interrupt-parent = <&gic>;
16724ba675SRob Herring	#address-cells = <2>;
17724ba675SRob Herring	#size-cells = <2>;
18724ba675SRob Herring
19724ba675SRob Herring	cpus {
20724ba675SRob Herring		#address-cells = <1>;
21724ba675SRob Herring		#size-cells = <0>;
22724ba675SRob Herring
23724ba675SRob Herring		cpu0: cpu@0 {
24724ba675SRob Herring			device_type = "cpu";
25724ba675SRob Herring			compatible = "arm,cortex-a15";
26724ba675SRob Herring			reg = <0>;
27724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
28724ba675SRob Herring			clock-frequency = <1500000000>;
29724ba675SRob Herring			power-domains = <&pd_a2sl>;
30724ba675SRob Herring			next-level-cache = <&L2_CA15>;
31724ba675SRob Herring		};
32724ba675SRob Herring
33724ba675SRob Herring		L2_CA15: cache-controller-0 {
34724ba675SRob Herring			compatible = "cache";
35724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
36724ba675SRob Herring			power-domains = <&pd_a3sm>;
37724ba675SRob Herring			cache-unified;
38724ba675SRob Herring			cache-level = <2>;
39724ba675SRob Herring		};
40724ba675SRob Herring
41724ba675SRob Herring		L2_CA7: cache-controller-1 {
42724ba675SRob Herring			compatible = "cache";
43724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
44724ba675SRob Herring			power-domains = <&pd_a3km>;
45724ba675SRob Herring			cache-unified;
46724ba675SRob Herring			cache-level = <2>;
47724ba675SRob Herring		};
48724ba675SRob Herring	};
49724ba675SRob Herring
50724ba675SRob Herring	ptm {
51724ba675SRob Herring		compatible = "arm,coresight-etm3x";
52724ba675SRob Herring		power-domains = <&pd_d4>;
53724ba675SRob Herring	};
54724ba675SRob Herring
55724ba675SRob Herring	timer {
56724ba675SRob Herring		compatible = "arm,armv7-timer";
57724ba675SRob Herring		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
58724ba675SRob Herring			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
59724ba675SRob Herring			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
60724ba675SRob Herring			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
61*9d30bd7bSGeert Uytterhoeven		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
62724ba675SRob Herring	};
63724ba675SRob Herring
64ecc79ab9SGeert Uytterhoeven	tmu0: timer@e61e0000 {
65ecc79ab9SGeert Uytterhoeven		compatible = "renesas,tmu-r8a73a4", "renesas,tmu";
66ecc79ab9SGeert Uytterhoeven		reg = <0 0xe61e0000 0 0x30>;
67ecc79ab9SGeert Uytterhoeven		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
68ecc79ab9SGeert Uytterhoeven			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
69ecc79ab9SGeert Uytterhoeven			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
70ecc79ab9SGeert Uytterhoeven		interrupt-names = "tuni0", "tuni1", "tuni2";
71ecc79ab9SGeert Uytterhoeven		clocks = <&mstp1_clks R8A73A4_CLK_TMU0>;
72ecc79ab9SGeert Uytterhoeven		clock-names = "fck";
73ecc79ab9SGeert Uytterhoeven		power-domains = <&pd_c5>;
74ecc79ab9SGeert Uytterhoeven		status = "disabled";
75ecc79ab9SGeert Uytterhoeven	};
76ecc79ab9SGeert Uytterhoeven
77ecc79ab9SGeert Uytterhoeven	tmu3: timer@fff80000 {
78ecc79ab9SGeert Uytterhoeven		compatible = "renesas,tmu-r8a73a4", "renesas,tmu";
79ecc79ab9SGeert Uytterhoeven		reg = <0 0xfff80000 0 0x30>;
80ecc79ab9SGeert Uytterhoeven		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
81ecc79ab9SGeert Uytterhoeven			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
82ecc79ab9SGeert Uytterhoeven			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
83ecc79ab9SGeert Uytterhoeven		interrupt-names = "tuni0", "tuni1", "tuni2";
84ecc79ab9SGeert Uytterhoeven		clocks = <&mstp1_clks R8A73A4_CLK_TMU3>;
85ecc79ab9SGeert Uytterhoeven		clock-names = "fck";
86ecc79ab9SGeert Uytterhoeven		power-domains = <&pd_a3r>;
87ecc79ab9SGeert Uytterhoeven		status = "disabled";
88ecc79ab9SGeert Uytterhoeven	};
89ecc79ab9SGeert Uytterhoeven
90724ba675SRob Herring	dbsc1: memory-controller@e6790000 {
91724ba675SRob Herring		compatible = "renesas,dbsc-r8a73a4";
92724ba675SRob Herring		reg = <0 0xe6790000 0 0x10000>;
93724ba675SRob Herring		power-domains = <&pd_a3bc>;
94724ba675SRob Herring	};
95724ba675SRob Herring
96724ba675SRob Herring	dbsc2: memory-controller@e67a0000 {
97724ba675SRob Herring		compatible = "renesas,dbsc-r8a73a4";
98724ba675SRob Herring		reg = <0 0xe67a0000 0 0x10000>;
99724ba675SRob Herring		power-domains = <&pd_a3bc>;
100724ba675SRob Herring	};
101724ba675SRob Herring
102724ba675SRob Herring	i2c5: i2c@e60b0000 {
103724ba675SRob Herring		#address-cells = <1>;
104724ba675SRob Herring		#size-cells = <0>;
105724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
106724ba675SRob Herring		reg = <0 0xe60b0000 0 0x428>;
107724ba675SRob Herring		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
108724ba675SRob Herring		clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
109724ba675SRob Herring		power-domains = <&pd_a3sp>;
110724ba675SRob Herring
111724ba675SRob Herring		status = "disabled";
112724ba675SRob Herring	};
113724ba675SRob Herring
114724ba675SRob Herring	cmt1: timer@e6130000 {
115724ba675SRob Herring		compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
116724ba675SRob Herring		reg = <0 0xe6130000 0 0x1004>;
117724ba675SRob Herring		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
118724ba675SRob Herring			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
119724ba675SRob Herring			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
120724ba675SRob Herring			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
121724ba675SRob Herring			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
122724ba675SRob Herring			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
123724ba675SRob Herring			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
124724ba675SRob Herring			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
125724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
126724ba675SRob Herring		clock-names = "fck";
127724ba675SRob Herring		power-domains = <&pd_c5>;
128724ba675SRob Herring		status = "disabled";
129724ba675SRob Herring	};
130724ba675SRob Herring
131724ba675SRob Herring	irqc0: interrupt-controller@e61c0000 {
132724ba675SRob Herring		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
133724ba675SRob Herring		#interrupt-cells = <2>;
134724ba675SRob Herring		interrupt-controller;
135724ba675SRob Herring		reg = <0 0xe61c0000 0 0x200>;
136724ba675SRob Herring		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
137724ba675SRob Herring			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
138724ba675SRob Herring			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
139724ba675SRob Herring			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
140724ba675SRob Herring			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
141724ba675SRob Herring			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
142724ba675SRob Herring			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
143724ba675SRob Herring			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
144724ba675SRob Herring			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
145724ba675SRob Herring			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
146724ba675SRob Herring			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
147724ba675SRob Herring			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
148724ba675SRob Herring			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
149724ba675SRob Herring			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
150724ba675SRob Herring			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
151724ba675SRob Herring			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
152724ba675SRob Herring			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
153724ba675SRob Herring			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
154724ba675SRob Herring			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
155724ba675SRob Herring			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
156724ba675SRob Herring			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
157724ba675SRob Herring			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
158724ba675SRob Herring			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
159724ba675SRob Herring			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
160724ba675SRob Herring			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
161724ba675SRob Herring			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
162724ba675SRob Herring			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
163724ba675SRob Herring			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
164724ba675SRob Herring			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
165724ba675SRob Herring			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
166724ba675SRob Herring			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
167724ba675SRob Herring			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
168724ba675SRob Herring		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
169724ba675SRob Herring		power-domains = <&pd_c4>;
170724ba675SRob Herring	};
171724ba675SRob Herring
172724ba675SRob Herring	irqc1: interrupt-controller@e61c0200 {
173724ba675SRob Herring		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
174724ba675SRob Herring		#interrupt-cells = <2>;
175724ba675SRob Herring		interrupt-controller;
176724ba675SRob Herring		reg = <0 0xe61c0200 0 0x200>;
177724ba675SRob Herring		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
178724ba675SRob Herring			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
179724ba675SRob Herring			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
180724ba675SRob Herring			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
181724ba675SRob Herring			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
182724ba675SRob Herring			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
183724ba675SRob Herring			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
184724ba675SRob Herring			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
185724ba675SRob Herring			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
186724ba675SRob Herring			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
187724ba675SRob Herring			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
188724ba675SRob Herring			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
189724ba675SRob Herring			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
190724ba675SRob Herring			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
191724ba675SRob Herring			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
192724ba675SRob Herring			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
193724ba675SRob Herring			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
194724ba675SRob Herring			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
195724ba675SRob Herring			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
196724ba675SRob Herring			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
197724ba675SRob Herring			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
198724ba675SRob Herring			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
199724ba675SRob Herring			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
200724ba675SRob Herring			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
201724ba675SRob Herring			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
202724ba675SRob Herring			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
203724ba675SRob Herring		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
204724ba675SRob Herring		power-domains = <&pd_c4>;
205724ba675SRob Herring	};
206724ba675SRob Herring
207724ba675SRob Herring	pfc: pinctrl@e6050000 {
208724ba675SRob Herring		compatible = "renesas,pfc-r8a73a4";
209724ba675SRob Herring		reg = <0 0xe6050000 0 0x9000>;
210724ba675SRob Herring		gpio-controller;
211724ba675SRob Herring		#gpio-cells = <2>;
212724ba675SRob Herring		gpio-ranges =
213724ba675SRob Herring			<&pfc 0 0 31>, <&pfc 32 32 9>,
214724ba675SRob Herring			<&pfc 64 64 22>, <&pfc 96 96 31>,
215724ba675SRob Herring			<&pfc 128 128 7>, <&pfc 160 160 19>,
216724ba675SRob Herring			<&pfc 192 192 31>, <&pfc 224 224 27>,
217724ba675SRob Herring			<&pfc 256 256 28>, <&pfc 288 288 21>,
218724ba675SRob Herring			<&pfc 320 320 10>;
219724ba675SRob Herring		interrupts-extended =
220724ba675SRob Herring			<&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
221724ba675SRob Herring			<&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
222724ba675SRob Herring			<&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
223724ba675SRob Herring			<&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
224724ba675SRob Herring			<&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
225724ba675SRob Herring			<&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
226724ba675SRob Herring			<&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
227724ba675SRob Herring			<&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
228724ba675SRob Herring			<&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
229724ba675SRob Herring			<&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
230724ba675SRob Herring			<&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
231724ba675SRob Herring			<&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
232724ba675SRob Herring			<&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
233724ba675SRob Herring			<&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
234724ba675SRob Herring			<&irqc1 24 0>, <&irqc1 25 0>;
235724ba675SRob Herring		power-domains = <&pd_c5>;
236724ba675SRob Herring	};
237724ba675SRob Herring
238724ba675SRob Herring	thermal@e61f0000 {
239724ba675SRob Herring		compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
240724ba675SRob Herring		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
241724ba675SRob Herring			 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
242724ba675SRob Herring		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
243724ba675SRob Herring		clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
244724ba675SRob Herring		power-domains = <&pd_c5>;
245724ba675SRob Herring	};
246724ba675SRob Herring
247724ba675SRob Herring	i2c0: i2c@e6500000 {
248724ba675SRob Herring		#address-cells = <1>;
249724ba675SRob Herring		#size-cells = <0>;
250724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
251724ba675SRob Herring		reg = <0 0xe6500000 0 0x428>;
252724ba675SRob Herring		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
253724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
254724ba675SRob Herring		power-domains = <&pd_a3sp>;
255724ba675SRob Herring		status = "disabled";
256724ba675SRob Herring	};
257724ba675SRob Herring
258724ba675SRob Herring	i2c1: i2c@e6510000 {
259724ba675SRob Herring		#address-cells = <1>;
260724ba675SRob Herring		#size-cells = <0>;
261724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
262724ba675SRob Herring		reg = <0 0xe6510000 0 0x428>;
263724ba675SRob Herring		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
264724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
265724ba675SRob Herring		power-domains = <&pd_a3sp>;
266724ba675SRob Herring		status = "disabled";
267724ba675SRob Herring	};
268724ba675SRob Herring
269724ba675SRob Herring	i2c2: i2c@e6520000 {
270724ba675SRob Herring		#address-cells = <1>;
271724ba675SRob Herring		#size-cells = <0>;
272724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
273724ba675SRob Herring		reg = <0 0xe6520000 0 0x428>;
274724ba675SRob Herring		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
275724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
276724ba675SRob Herring		power-domains = <&pd_a3sp>;
277724ba675SRob Herring		status = "disabled";
278724ba675SRob Herring	};
279724ba675SRob Herring
280724ba675SRob Herring	i2c3: i2c@e6530000 {
281724ba675SRob Herring		#address-cells = <1>;
282724ba675SRob Herring		#size-cells = <0>;
283724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
284724ba675SRob Herring		reg = <0 0xe6530000 0 0x428>;
285724ba675SRob Herring		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
286724ba675SRob Herring		clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
287724ba675SRob Herring		power-domains = <&pd_a3sp>;
288724ba675SRob Herring		status = "disabled";
289724ba675SRob Herring	};
290724ba675SRob Herring
291724ba675SRob Herring	i2c4: i2c@e6540000 {
292724ba675SRob Herring		#address-cells = <1>;
293724ba675SRob Herring		#size-cells = <0>;
294724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
295724ba675SRob Herring		reg = <0 0xe6540000 0 0x428>;
296724ba675SRob Herring		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
297724ba675SRob Herring		clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
298724ba675SRob Herring		power-domains = <&pd_a3sp>;
299724ba675SRob Herring		status = "disabled";
300724ba675SRob Herring	};
301724ba675SRob Herring
302724ba675SRob Herring	i2c6: i2c@e6550000 {
303724ba675SRob Herring		#address-cells = <1>;
304724ba675SRob Herring		#size-cells = <0>;
305724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
306724ba675SRob Herring		reg = <0 0xe6550000 0 0x428>;
307724ba675SRob Herring		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
308724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
309724ba675SRob Herring		power-domains = <&pd_a3sp>;
310724ba675SRob Herring		status = "disabled";
311724ba675SRob Herring	};
312724ba675SRob Herring
313724ba675SRob Herring	i2c7: i2c@e6560000 {
314724ba675SRob Herring		#address-cells = <1>;
315724ba675SRob Herring		#size-cells = <0>;
316724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
317724ba675SRob Herring		reg = <0 0xe6560000 0 0x428>;
318724ba675SRob Herring		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
319724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
320724ba675SRob Herring		power-domains = <&pd_a3sp>;
321724ba675SRob Herring		status = "disabled";
322724ba675SRob Herring	};
323724ba675SRob Herring
324724ba675SRob Herring	i2c8: i2c@e6570000 {
325724ba675SRob Herring		#address-cells = <1>;
326724ba675SRob Herring		#size-cells = <0>;
327724ba675SRob Herring		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
328724ba675SRob Herring		reg = <0 0xe6570000 0 0x428>;
329724ba675SRob Herring		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
330724ba675SRob Herring		clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
331724ba675SRob Herring		power-domains = <&pd_a3sp>;
332724ba675SRob Herring		status = "disabled";
333724ba675SRob Herring	};
334724ba675SRob Herring
335724ba675SRob Herring	scifb0: serial@e6c20000 {
336724ba675SRob Herring		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
337724ba675SRob Herring		reg = <0 0xe6c20000 0 0x100>;
338724ba675SRob Herring		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
339724ba675SRob Herring		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
340724ba675SRob Herring		clock-names = "fck";
341724ba675SRob Herring		power-domains = <&pd_a3sp>;
342724ba675SRob Herring		status = "disabled";
343724ba675SRob Herring	};
344724ba675SRob Herring
345724ba675SRob Herring	scifb1: serial@e6c30000 {
346724ba675SRob Herring		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
347724ba675SRob Herring		reg = <0 0xe6c30000 0 0x100>;
348724ba675SRob Herring		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
349724ba675SRob Herring		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
350724ba675SRob Herring		clock-names = "fck";
351724ba675SRob Herring		power-domains = <&pd_a3sp>;
352724ba675SRob Herring		status = "disabled";
353724ba675SRob Herring	};
354724ba675SRob Herring
355724ba675SRob Herring	scifa0: serial@e6c40000 {
356724ba675SRob Herring		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
357724ba675SRob Herring		reg = <0 0xe6c40000 0 0x100>;
358724ba675SRob Herring		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
359724ba675SRob Herring		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
360724ba675SRob Herring		clock-names = "fck";
361724ba675SRob Herring		power-domains = <&pd_a3sp>;
362724ba675SRob Herring		status = "disabled";
363724ba675SRob Herring	};
364724ba675SRob Herring
365724ba675SRob Herring	scifa1: serial@e6c50000 {
366724ba675SRob Herring		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
367724ba675SRob Herring		reg = <0 0xe6c50000 0 0x100>;
368724ba675SRob Herring		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
369724ba675SRob Herring		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
370724ba675SRob Herring		clock-names = "fck";
371724ba675SRob Herring		power-domains = <&pd_a3sp>;
372724ba675SRob Herring		status = "disabled";
373724ba675SRob Herring	};
374724ba675SRob Herring
375724ba675SRob Herring	scifb2: serial@e6ce0000 {
376724ba675SRob Herring		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
377724ba675SRob Herring		reg = <0 0xe6ce0000 0 0x100>;
378724ba675SRob Herring		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
379724ba675SRob Herring		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
380724ba675SRob Herring		clock-names = "fck";
381724ba675SRob Herring		power-domains = <&pd_a3sp>;
382724ba675SRob Herring		status = "disabled";
383724ba675SRob Herring	};
384724ba675SRob Herring
385724ba675SRob Herring	scifb3: serial@e6cf0000 {
386724ba675SRob Herring		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
387724ba675SRob Herring		reg = <0 0xe6cf0000 0 0x100>;
388724ba675SRob Herring		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
389724ba675SRob Herring		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
390724ba675SRob Herring		clock-names = "fck";
391724ba675SRob Herring		power-domains = <&pd_c4>;
392724ba675SRob Herring		status = "disabled";
393724ba675SRob Herring	};
394724ba675SRob Herring
395724ba675SRob Herring	sdhi0: mmc@ee100000 {
396724ba675SRob Herring		compatible = "renesas,sdhi-r8a73a4";
397724ba675SRob Herring		reg = <0 0xee100000 0 0x100>;
398724ba675SRob Herring		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
399724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
400724ba675SRob Herring		power-domains = <&pd_a3sp>;
401724ba675SRob Herring		cap-sd-highspeed;
402724ba675SRob Herring		status = "disabled";
403724ba675SRob Herring	};
404724ba675SRob Herring
405724ba675SRob Herring	sdhi1: mmc@ee120000 {
406724ba675SRob Herring		compatible = "renesas,sdhi-r8a73a4";
407724ba675SRob Herring		reg = <0 0xee120000 0 0x100>;
408724ba675SRob Herring		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
409724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
410724ba675SRob Herring		power-domains = <&pd_a3sp>;
411724ba675SRob Herring		cap-sd-highspeed;
412724ba675SRob Herring		status = "disabled";
413724ba675SRob Herring	};
414724ba675SRob Herring
415724ba675SRob Herring	sdhi2: mmc@ee140000 {
416724ba675SRob Herring		compatible = "renesas,sdhi-r8a73a4";
417724ba675SRob Herring		reg = <0 0xee140000 0 0x100>;
418724ba675SRob Herring		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
419724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
420724ba675SRob Herring		power-domains = <&pd_a3sp>;
421724ba675SRob Herring		cap-sd-highspeed;
422724ba675SRob Herring		status = "disabled";
423724ba675SRob Herring	};
424724ba675SRob Herring
425724ba675SRob Herring	mmcif0: mmc@ee200000 {
426724ba675SRob Herring		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
427724ba675SRob Herring		reg = <0 0xee200000 0 0x80>;
428724ba675SRob Herring		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
429724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
430724ba675SRob Herring		power-domains = <&pd_a3sp>;
431724ba675SRob Herring		status = "disabled";
432724ba675SRob Herring	};
433724ba675SRob Herring
434724ba675SRob Herring	mmcif1: mmc@ee220000 {
435724ba675SRob Herring		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
436724ba675SRob Herring		reg = <0 0xee220000 0 0x80>;
437724ba675SRob Herring		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
438724ba675SRob Herring		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
439724ba675SRob Herring		power-domains = <&pd_a3sp>;
440724ba675SRob Herring		status = "disabled";
441724ba675SRob Herring	};
442724ba675SRob Herring
443724ba675SRob Herring	gic: interrupt-controller@f1001000 {
444724ba675SRob Herring		compatible = "arm,gic-400";
445724ba675SRob Herring		#interrupt-cells = <3>;
446724ba675SRob Herring		#address-cells = <0>;
447724ba675SRob Herring		interrupt-controller;
448724ba675SRob Herring		reg = <0 0xf1001000 0 0x1000>,
449724ba675SRob Herring			<0 0xf1002000 0 0x2000>,
450724ba675SRob Herring			<0 0xf1004000 0 0x2000>,
451724ba675SRob Herring			<0 0xf1006000 0 0x2000>;
452724ba675SRob Herring		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
453724ba675SRob Herring		clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
454724ba675SRob Herring		clock-names = "clk";
455724ba675SRob Herring		power-domains = <&pd_c4>;
456724ba675SRob Herring	};
457724ba675SRob Herring
458724ba675SRob Herring	bsc: bus@fec10000 {
459724ba675SRob Herring		compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
460724ba675SRob Herring			     "simple-pm-bus";
461724ba675SRob Herring		#address-cells = <1>;
462724ba675SRob Herring		#size-cells = <1>;
463724ba675SRob Herring		ranges = <0 0 0 0x20000000>;
464724ba675SRob Herring		reg = <0 0xfec10000 0 0x400>;
465724ba675SRob Herring		clocks = <&zb_clk>;
466724ba675SRob Herring		power-domains = <&pd_c4>;
467724ba675SRob Herring	};
468724ba675SRob Herring
469724ba675SRob Herring	clocks {
470724ba675SRob Herring		#address-cells = <2>;
471724ba675SRob Herring		#size-cells = <2>;
472724ba675SRob Herring		ranges;
473724ba675SRob Herring
474724ba675SRob Herring		/* External root clocks */
475724ba675SRob Herring		extalr_clk: extalr {
476724ba675SRob Herring			compatible = "fixed-clock";
477724ba675SRob Herring			#clock-cells = <0>;
478090c4094SGeert Uytterhoeven			/* This value must be overridden by the board. */
479090c4094SGeert Uytterhoeven			clock-frequency = <0>;
480724ba675SRob Herring		};
481724ba675SRob Herring		extal1_clk: extal1 {
482724ba675SRob Herring			compatible = "fixed-clock";
483724ba675SRob Herring			#clock-cells = <0>;
484090c4094SGeert Uytterhoeven			/* This value must be overridden by the board. */
485090c4094SGeert Uytterhoeven			clock-frequency = <0>;
486724ba675SRob Herring		};
487724ba675SRob Herring		extal2_clk: extal2 {
488724ba675SRob Herring			compatible = "fixed-clock";
489724ba675SRob Herring			#clock-cells = <0>;
490090c4094SGeert Uytterhoeven			/* This value must be overridden by the board. */
491090c4094SGeert Uytterhoeven			clock-frequency = <0>;
492724ba675SRob Herring		};
493724ba675SRob Herring		fsiack_clk: fsiack {
494724ba675SRob Herring			compatible = "fixed-clock";
495724ba675SRob Herring			#clock-cells = <0>;
496724ba675SRob Herring			/* This value must be overridden by the board. */
497724ba675SRob Herring			clock-frequency = <0>;
498724ba675SRob Herring		};
499724ba675SRob Herring		fsibck_clk: fsibck {
500724ba675SRob Herring			compatible = "fixed-clock";
501724ba675SRob Herring			#clock-cells = <0>;
502724ba675SRob Herring			/* This value must be overridden by the board. */
503724ba675SRob Herring			clock-frequency = <0>;
504724ba675SRob Herring		};
505724ba675SRob Herring
506724ba675SRob Herring		/* Special CPG clocks */
507724ba675SRob Herring		cpg_clocks: cpg_clocks@e6150000 {
508724ba675SRob Herring			compatible = "renesas,r8a73a4-cpg-clocks";
509724ba675SRob Herring			reg = <0 0xe6150000 0 0x10000>;
510724ba675SRob Herring			clocks = <&extal1_clk>, <&extal2_clk>;
511724ba675SRob Herring			#clock-cells = <1>;
512724ba675SRob Herring			clock-output-names = "main", "pll0", "pll1", "pll2",
513724ba675SRob Herring					     "pll2s", "pll2h", "z", "z2",
514724ba675SRob Herring					     "i", "m3", "b", "m1", "m2",
515724ba675SRob Herring					     "zx", "zs", "hp";
516724ba675SRob Herring		};
517724ba675SRob Herring
518724ba675SRob Herring		/* Variable factor clocks (DIV6) */
519724ba675SRob Herring		zb_clk: zb_clk@e6150010 {
520724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
521724ba675SRob Herring			reg = <0 0xe6150010 0 4>;
522724ba675SRob Herring			clocks = <&pll1_div2_clk>, <0>,
523724ba675SRob Herring				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
524724ba675SRob Herring			#clock-cells = <0>;
525724ba675SRob Herring			clock-output-names = "zb";
526724ba675SRob Herring		};
527724ba675SRob Herring		sdhi0_clk: sdhi0ck@e6150074 {
528724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
529724ba675SRob Herring			reg = <0 0xe6150074 0 4>;
530724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
531724ba675SRob Herring				 <0>, <&extal2_clk>;
532724ba675SRob Herring			#clock-cells = <0>;
533724ba675SRob Herring		};
534724ba675SRob Herring		sdhi1_clk: sdhi1ck@e6150078 {
535724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
536724ba675SRob Herring			reg = <0 0xe6150078 0 4>;
537724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
538724ba675SRob Herring				 <0>, <&extal2_clk>;
539724ba675SRob Herring			#clock-cells = <0>;
540724ba675SRob Herring		};
541724ba675SRob Herring		sdhi2_clk: sdhi2ck@e615007c {
542724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
543724ba675SRob Herring			reg = <0 0xe615007c 0 4>;
544724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
545724ba675SRob Herring				 <0>, <&extal2_clk>;
546724ba675SRob Herring			#clock-cells = <0>;
547724ba675SRob Herring		};
548724ba675SRob Herring		mmc0_clk: mmc0@e6150240 {
549724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
550724ba675SRob Herring			reg = <0 0xe6150240 0 4>;
551724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
552724ba675SRob Herring				 <0>, <&extal2_clk>;
553724ba675SRob Herring			#clock-cells = <0>;
554724ba675SRob Herring		};
555724ba675SRob Herring		mmc1_clk: mmc1@e6150244 {
556724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
557724ba675SRob Herring			reg = <0 0xe6150244 0 4>;
558724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
559724ba675SRob Herring				 <0>, <&extal2_clk>;
560724ba675SRob Herring			#clock-cells = <0>;
561724ba675SRob Herring		};
562724ba675SRob Herring		vclk1_clk: vclk1@e6150008 {
563724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
564724ba675SRob Herring			reg = <0 0xe6150008 0 4>;
565724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
566724ba675SRob Herring				 <0>, <&extal2_clk>, <&main_div2_clk>,
567724ba675SRob Herring				 <&extalr_clk>, <0>, <0>;
568724ba675SRob Herring			#clock-cells = <0>;
569724ba675SRob Herring		};
570724ba675SRob Herring		vclk2_clk: vclk2@e615000c {
571724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
572724ba675SRob Herring			reg = <0 0xe615000c 0 4>;
573724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
574724ba675SRob Herring				 <0>, <&extal2_clk>, <&main_div2_clk>,
575724ba675SRob Herring				 <&extalr_clk>, <0>, <0>;
576724ba675SRob Herring			#clock-cells = <0>;
577724ba675SRob Herring		};
578724ba675SRob Herring		vclk3_clk: vclk3@e615001c {
579724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
580724ba675SRob Herring			reg = <0 0xe615001c 0 4>;
581724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
582724ba675SRob Herring				 <0>, <&extal2_clk>, <&main_div2_clk>,
583724ba675SRob Herring				 <&extalr_clk>, <0>, <0>;
584724ba675SRob Herring			#clock-cells = <0>;
585724ba675SRob Herring		};
586724ba675SRob Herring		vclk4_clk: vclk4@e6150014 {
587724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
588724ba675SRob Herring			reg = <0 0xe6150014 0 4>;
589724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
590724ba675SRob Herring				 <0>, <&extal2_clk>, <&main_div2_clk>,
591724ba675SRob Herring				 <&extalr_clk>, <0>, <0>;
592724ba675SRob Herring			#clock-cells = <0>;
593724ba675SRob Herring		};
594724ba675SRob Herring		vclk5_clk: vclk5@e6150034 {
595724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
596724ba675SRob Herring			reg = <0 0xe6150034 0 4>;
597724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
598724ba675SRob Herring				 <0>, <&extal2_clk>, <&main_div2_clk>,
599724ba675SRob Herring				 <&extalr_clk>, <0>, <0>;
600724ba675SRob Herring			#clock-cells = <0>;
601724ba675SRob Herring		};
602724ba675SRob Herring		fsia_clk: fsia@e6150018 {
603724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
604724ba675SRob Herring			reg = <0 0xe6150018 0 4>;
605724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
606724ba675SRob Herring				 <&fsiack_clk>, <0>;
607724ba675SRob Herring			#clock-cells = <0>;
608724ba675SRob Herring		};
609724ba675SRob Herring		fsib_clk: fsib@e6150090 {
610724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
611724ba675SRob Herring			reg = <0 0xe6150090 0 4>;
612724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
613724ba675SRob Herring				 <&fsibck_clk>, <0>;
614724ba675SRob Herring			#clock-cells = <0>;
615724ba675SRob Herring		};
616724ba675SRob Herring		mp_clk: mp@e6150080 {
617724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
618724ba675SRob Herring			reg = <0 0xe6150080 0 4>;
619724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
620724ba675SRob Herring				 <&extal2_clk>, <&extal2_clk>;
621724ba675SRob Herring			#clock-cells = <0>;
622724ba675SRob Herring		};
623724ba675SRob Herring		m4_clk: m4@e6150098 {
624724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
625724ba675SRob Herring			reg = <0 0xe6150098 0 4>;
626724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
627724ba675SRob Herring			#clock-cells = <0>;
628724ba675SRob Herring		};
629724ba675SRob Herring		hsi_clk: hsi@e615026c {
630724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
631724ba675SRob Herring			reg = <0 0xe615026c 0 4>;
632724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
633724ba675SRob Herring				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
634724ba675SRob Herring			#clock-cells = <0>;
635724ba675SRob Herring		};
636724ba675SRob Herring		spuv_clk: spuv@e6150094 {
637724ba675SRob Herring			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
638724ba675SRob Herring			reg = <0 0xe6150094 0 4>;
639724ba675SRob Herring			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
640724ba675SRob Herring				 <&extal2_clk>, <&extal2_clk>;
641724ba675SRob Herring			#clock-cells = <0>;
642724ba675SRob Herring		};
643724ba675SRob Herring
644724ba675SRob Herring		/* Fixed factor clocks */
645724ba675SRob Herring		main_div2_clk: main_div2 {
646724ba675SRob Herring			compatible = "fixed-factor-clock";
647724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
648724ba675SRob Herring			#clock-cells = <0>;
649724ba675SRob Herring			clock-div = <2>;
650724ba675SRob Herring			clock-mult = <1>;
651724ba675SRob Herring		};
652dd9cc6afSGeert Uytterhoeven		cp_clk: cp {
653dd9cc6afSGeert Uytterhoeven			compatible = "fixed-factor-clock";
654dd9cc6afSGeert Uytterhoeven			clocks = <&main_div2_clk>;
655dd9cc6afSGeert Uytterhoeven			#clock-cells = <0>;
656dd9cc6afSGeert Uytterhoeven			clock-div = <1>;
657dd9cc6afSGeert Uytterhoeven			clock-mult = <1>;
658dd9cc6afSGeert Uytterhoeven		};
659724ba675SRob Herring		pll0_div2_clk: pll0_div2 {
660724ba675SRob Herring			compatible = "fixed-factor-clock";
661724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
662724ba675SRob Herring			#clock-cells = <0>;
663724ba675SRob Herring			clock-div = <2>;
664724ba675SRob Herring			clock-mult = <1>;
665724ba675SRob Herring		};
666724ba675SRob Herring		pll1_div2_clk: pll1_div2 {
667724ba675SRob Herring			compatible = "fixed-factor-clock";
668724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
669724ba675SRob Herring			#clock-cells = <0>;
670724ba675SRob Herring			clock-div = <2>;
671724ba675SRob Herring			clock-mult = <1>;
672724ba675SRob Herring		};
673724ba675SRob Herring		extal1_div2_clk: extal1_div2 {
674724ba675SRob Herring			compatible = "fixed-factor-clock";
675724ba675SRob Herring			clocks = <&extal1_clk>;
676724ba675SRob Herring			#clock-cells = <0>;
677724ba675SRob Herring			clock-div = <2>;
678724ba675SRob Herring			clock-mult = <1>;
679724ba675SRob Herring		};
680724ba675SRob Herring
681724ba675SRob Herring		/* Gate clocks */
682ecc79ab9SGeert Uytterhoeven		mstp1_clks: mstp1_clks@e6150134 {
683ecc79ab9SGeert Uytterhoeven			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
684ecc79ab9SGeert Uytterhoeven			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
685ecc79ab9SGeert Uytterhoeven			clocks = <&cp_clk>, <&mp_clk>;
686ecc79ab9SGeert Uytterhoeven			#clock-cells = <1>;
687ecc79ab9SGeert Uytterhoeven			clock-indices = <
688ecc79ab9SGeert Uytterhoeven				R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3
689ecc79ab9SGeert Uytterhoeven			>;
690ecc79ab9SGeert Uytterhoeven			clock-output-names =
691ecc79ab9SGeert Uytterhoeven				"tmu0", "tmu3";
692ecc79ab9SGeert Uytterhoeven		};
693724ba675SRob Herring		mstp2_clks: mstp2_clks@e6150138 {
694724ba675SRob Herring			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
695724ba675SRob Herring			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
696724ba675SRob Herring			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
697724ba675SRob Herring				 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
698724ba675SRob Herring			#clock-cells = <1>;
699724ba675SRob Herring			clock-indices = <
700724ba675SRob Herring				R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
701724ba675SRob Herring				R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
702724ba675SRob Herring				R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
703724ba675SRob Herring				R8A73A4_CLK_DMAC
704724ba675SRob Herring			>;
705724ba675SRob Herring			clock-output-names =
706724ba675SRob Herring				"scifa0", "scifa1", "scifb0", "scifb1",
707724ba675SRob Herring				"scifb2", "scifb3", "dmac";
708724ba675SRob Herring		};
709724ba675SRob Herring		mstp3_clks: mstp3_clks@e615013c {
710724ba675SRob Herring			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
711724ba675SRob Herring			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
712724ba675SRob Herring			clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
713724ba675SRob Herring				 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
714724ba675SRob Herring				 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
715724ba675SRob Herring				 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
716724ba675SRob Herring				 R8A73A4_CLK_HP>, <&cpg_clocks
717724ba675SRob Herring				 R8A73A4_CLK_HP>, <&extalr_clk>;
718724ba675SRob Herring			#clock-cells = <1>;
719724ba675SRob Herring			clock-indices = <
720724ba675SRob Herring				R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
721724ba675SRob Herring				R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
722724ba675SRob Herring				R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
723724ba675SRob Herring				R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
724724ba675SRob Herring				R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
725724ba675SRob Herring				R8A73A4_CLK_CMT1
726724ba675SRob Herring			>;
727724ba675SRob Herring			clock-output-names =
728724ba675SRob Herring				"iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
729724ba675SRob Herring				"mmcif0", "iic6", "iic7", "iic0", "iic1",
730724ba675SRob Herring				"cmt1";
731724ba675SRob Herring		};
732724ba675SRob Herring		mstp4_clks: mstp4_clks@e6150140 {
733724ba675SRob Herring			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
734724ba675SRob Herring			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
735dd9cc6afSGeert Uytterhoeven			clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
736dd9cc6afSGeert Uytterhoeven				 <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
737724ba675SRob Herring				 <&cpg_clocks R8A73A4_CLK_HP>;
738724ba675SRob Herring			#clock-cells = <1>;
739724ba675SRob Herring			clock-indices = <
740724ba675SRob Herring				R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
741724ba675SRob Herring				R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
742724ba675SRob Herring				R8A73A4_CLK_IIC3
743724ba675SRob Herring			>;
744724ba675SRob Herring			clock-output-names =
745724ba675SRob Herring				"irqc", "intc-sys", "iic5", "iic4", "iic3";
746724ba675SRob Herring		};
747724ba675SRob Herring		mstp5_clks: mstp5_clks@e6150144 {
748724ba675SRob Herring			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
749724ba675SRob Herring			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
750d2339555SGeert Uytterhoeven			clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
751724ba675SRob Herring			#clock-cells = <1>;
752724ba675SRob Herring			clock-indices = <
753724ba675SRob Herring				R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
754724ba675SRob Herring			>;
755724ba675SRob Herring			clock-output-names =
756724ba675SRob Herring				"thermal", "iic8";
757724ba675SRob Herring		};
758724ba675SRob Herring	};
759724ba675SRob Herring
760724ba675SRob Herring	prr: chipid@ff000044 {
761724ba675SRob Herring		compatible = "renesas,prr";
762724ba675SRob Herring		reg = <0 0xff000044 0 4>;
763724ba675SRob Herring	};
764724ba675SRob Herring
765724ba675SRob Herring	sysc: system-controller@e6180000 {
766724ba675SRob Herring		compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
767724ba675SRob Herring		reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
768724ba675SRob Herring
769724ba675SRob Herring		pm-domains {
770724ba675SRob Herring			pd_c5: c5 {
771724ba675SRob Herring				#address-cells = <1>;
772724ba675SRob Herring				#size-cells = <0>;
773724ba675SRob Herring				#power-domain-cells = <0>;
774724ba675SRob Herring
775724ba675SRob Herring				pd_c4: c4@0 {
776724ba675SRob Herring					reg = <0>;
777724ba675SRob Herring					#address-cells = <1>;
778724ba675SRob Herring					#size-cells = <0>;
779724ba675SRob Herring					#power-domain-cells = <0>;
780724ba675SRob Herring
781724ba675SRob Herring					pd_a3sg: a3sg@16 {
782724ba675SRob Herring						reg = <16>;
783724ba675SRob Herring						#power-domain-cells = <0>;
784724ba675SRob Herring					};
785724ba675SRob Herring
786724ba675SRob Herring					pd_a3ex: a3ex@17 {
787724ba675SRob Herring						reg = <17>;
788724ba675SRob Herring						#power-domain-cells = <0>;
789724ba675SRob Herring					};
790724ba675SRob Herring
791724ba675SRob Herring					pd_a3sp: a3sp@18 {
792724ba675SRob Herring						reg = <18>;
793724ba675SRob Herring						#address-cells = <1>;
794724ba675SRob Herring						#size-cells = <0>;
795724ba675SRob Herring						#power-domain-cells = <0>;
796724ba675SRob Herring
797724ba675SRob Herring						pd_a2us: a2us@19 {
798724ba675SRob Herring							reg = <19>;
799724ba675SRob Herring							#power-domain-cells = <0>;
800724ba675SRob Herring						};
801724ba675SRob Herring					};
802724ba675SRob Herring
803724ba675SRob Herring					pd_a3sm: a3sm@20 {
804724ba675SRob Herring						reg = <20>;
805724ba675SRob Herring						#address-cells = <1>;
806724ba675SRob Herring						#size-cells = <0>;
807724ba675SRob Herring						#power-domain-cells = <0>;
808724ba675SRob Herring
809724ba675SRob Herring						pd_a2sl: a2sl@21 {
810724ba675SRob Herring							reg = <21>;
811724ba675SRob Herring							#power-domain-cells = <0>;
812724ba675SRob Herring						};
813724ba675SRob Herring					};
814724ba675SRob Herring
815724ba675SRob Herring					pd_a3km: a3km@22 {
816724ba675SRob Herring						reg = <22>;
817724ba675SRob Herring						#address-cells = <1>;
818724ba675SRob Herring						#size-cells = <0>;
819724ba675SRob Herring						#power-domain-cells = <0>;
820724ba675SRob Herring
821724ba675SRob Herring						pd_a2kl: a2kl@23 {
822724ba675SRob Herring							reg = <23>;
823724ba675SRob Herring							#power-domain-cells = <0>;
824724ba675SRob Herring						};
825724ba675SRob Herring					};
826724ba675SRob Herring				};
827724ba675SRob Herring
828724ba675SRob Herring				pd_c4ma: c4ma@1 {
829724ba675SRob Herring					reg = <1>;
830724ba675SRob Herring					#power-domain-cells = <0>;
831724ba675SRob Herring				};
832724ba675SRob Herring
833724ba675SRob Herring				pd_c4cl: c4cl@2 {
834724ba675SRob Herring					reg = <2>;
835724ba675SRob Herring					#power-domain-cells = <0>;
836724ba675SRob Herring				};
837724ba675SRob Herring
838724ba675SRob Herring				pd_d4: d4@3 {
839724ba675SRob Herring					reg = <3>;
840724ba675SRob Herring					#power-domain-cells = <0>;
841724ba675SRob Herring				};
842724ba675SRob Herring
843724ba675SRob Herring				pd_a4bc: a4bc@4 {
844724ba675SRob Herring					reg = <4>;
845724ba675SRob Herring					#address-cells = <1>;
846724ba675SRob Herring					#size-cells = <0>;
847724ba675SRob Herring					#power-domain-cells = <0>;
848724ba675SRob Herring
849724ba675SRob Herring					pd_a3bc: a3bc@5 {
850724ba675SRob Herring						reg = <5>;
851724ba675SRob Herring						#power-domain-cells = <0>;
852724ba675SRob Herring					};
853724ba675SRob Herring				};
854724ba675SRob Herring
855724ba675SRob Herring				pd_a4l: a4l@6 {
856724ba675SRob Herring					reg = <6>;
857724ba675SRob Herring					#power-domain-cells = <0>;
858724ba675SRob Herring				};
859724ba675SRob Herring
860724ba675SRob Herring				pd_a4lc: a4lc@7 {
861724ba675SRob Herring					reg = <7>;
862724ba675SRob Herring					#power-domain-cells = <0>;
863724ba675SRob Herring				};
864724ba675SRob Herring
865724ba675SRob Herring				pd_a4mp: a4mp@8 {
866724ba675SRob Herring					reg = <8>;
867724ba675SRob Herring					#address-cells = <1>;
868724ba675SRob Herring					#size-cells = <0>;
869724ba675SRob Herring					#power-domain-cells = <0>;
870724ba675SRob Herring
871724ba675SRob Herring					pd_a3mp: a3mp@9 {
872724ba675SRob Herring						reg = <9>;
873724ba675SRob Herring						#power-domain-cells = <0>;
874724ba675SRob Herring					};
875724ba675SRob Herring
876724ba675SRob Herring					pd_a3vc: a3vc@10 {
877724ba675SRob Herring						reg = <10>;
878724ba675SRob Herring						#power-domain-cells = <0>;
879724ba675SRob Herring					};
880724ba675SRob Herring				};
881724ba675SRob Herring
882724ba675SRob Herring				pd_a4sf: a4sf@11 {
883724ba675SRob Herring					reg = <11>;
884724ba675SRob Herring					#power-domain-cells = <0>;
885724ba675SRob Herring				};
886724ba675SRob Herring
887724ba675SRob Herring				pd_a3r: a3r@12 {
888724ba675SRob Herring					reg = <12>;
889724ba675SRob Herring					#address-cells = <1>;
890724ba675SRob Herring					#size-cells = <0>;
891724ba675SRob Herring					#power-domain-cells = <0>;
892724ba675SRob Herring
893724ba675SRob Herring					pd_a2rv: a2rv@13 {
894724ba675SRob Herring						reg = <13>;
895724ba675SRob Herring						#power-domain-cells = <0>;
896724ba675SRob Herring					};
897724ba675SRob Herring
898724ba675SRob Herring					pd_a2is: a2is@14 {
899724ba675SRob Herring						reg = <14>;
900724ba675SRob Herring						#power-domain-cells = <0>;
901724ba675SRob Herring					};
902724ba675SRob Herring				};
903724ba675SRob Herring			};
904724ba675SRob Herring		};
905724ba675SRob Herring	};
906724ba675SRob Herring};
907