1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX65 SoC device tree source 4 * 5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx65.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15#include <dt-bindings/interconnect/qcom,sdx65.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; 21 interrupt-parent = <&intc>; 22 23 memory { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 clock-frequency = <76800000>; 32 clock-output-names = "xo_board"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 #clock-cells = <0>; 41 }; 42 43 nand_clk_dummy: nand-clk-dummy { 44 compatible = "fixed-clock"; 45 clock-frequency = <32764>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0x0>; 58 enable-method = "psci"; 59 clocks = <&apcs>; 60 power-domains = <&rpmhpd SDX65_CX_AO>; 61 power-domain-names = "rpmhpd"; 62 operating-points-v2 = <&cpu_opp_table>; 63 }; 64 }; 65 66 firmware { 67 scm { 68 compatible = "qcom,scm-sdx65", "qcom,scm"; 69 }; 70 }; 71 72 mc_virt: interconnect-mc-virt { 73 compatible = "qcom,sdx65-mc-virt"; 74 #interconnect-cells = <1>; 75 qcom,bcm-voters = <&apps_bcm_voter>; 76 }; 77 78 cpu_opp_table: opp-table-cpu { 79 compatible = "operating-points-v2"; 80 opp-shared; 81 82 opp-345600000 { 83 opp-hz = /bits/ 64 <345600000>; 84 required-opps = <&rpmhpd_opp_low_svs>; 85 }; 86 87 opp-576000000 { 88 opp-hz = /bits/ 64 <576000000>; 89 required-opps = <&rpmhpd_opp_svs>; 90 }; 91 92 opp-1094400000 { 93 opp-hz = /bits/ 64 <1094400000>; 94 required-opps = <&rpmhpd_opp_nom>; 95 }; 96 97 opp-1497600000 { 98 opp-hz = /bits/ 64 <1497600000>; 99 required-opps = <&rpmhpd_opp_turbo>; 100 }; 101 }; 102 103 psci { 104 compatible = "arm,psci-1.0"; 105 method = "smc"; 106 }; 107 108 reserved_memory: reserved-memory { 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges; 112 113 tz_heap_mem: memory@8fcad000 { 114 no-map; 115 reg = <0x8fcad000 0x40000>; 116 }; 117 118 secdata_mem: memory@8fcfd000 { 119 no-map; 120 reg = <0x8fcfd000 0x1000>; 121 }; 122 123 hyp_mem: memory@8fd00000 { 124 no-map; 125 reg = <0x8fd00000 0x80000>; 126 }; 127 128 access_control_mem: memory@8fd80000 { 129 no-map; 130 reg = <0x8fd80000 0x80000>; 131 }; 132 133 aop_mem: memory@8fe00000 { 134 no-map; 135 reg = <0x8fe00000 0x20000>; 136 }; 137 138 smem_mem: memory@8fe20000 { 139 compatible = "qcom,smem"; 140 reg = <0x8fe20000 0xc0000>; 141 hwlocks = <&tcsr_mutex 3>; 142 no-map; 143 }; 144 145 cmd_db: reserved-memory@8fee0000 { 146 compatible = "qcom,cmd-db"; 147 reg = <0x8fee0000 0x20000>; 148 no-map; 149 }; 150 151 tz_mem: memory@8ff00000 { 152 no-map; 153 reg = <0x8ff00000 0x100000>; 154 }; 155 156 tz_apps_mem: memory@90000000 { 157 no-map; 158 reg = <0x90000000 0x500000>; 159 }; 160 161 llcc_tcm_mem: memory@15800000 { 162 no-map; 163 reg = <0x15800000 0x800000>; 164 }; 165 }; 166 167 smp2p-mpss { 168 compatible = "qcom,smp2p"; 169 qcom,smem = <435>, <428>; 170 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 171 mboxes = <&apcs 14>; 172 qcom,local-pid = <0>; 173 qcom,remote-pid = <1>; 174 175 modem_smp2p_out: master-kernel { 176 qcom,entry-name = "master-kernel"; 177 #qcom,smem-state-cells = <1>; 178 }; 179 180 modem_smp2p_in: slave-kernel { 181 qcom,entry-name = "slave-kernel"; 182 interrupt-controller; 183 #interrupt-cells = <2>; 184 }; 185 186 ipa_smp2p_out: ipa-ap-to-modem { 187 qcom,entry-name = "ipa"; 188 #qcom,smem-state-cells = <1>; 189 }; 190 191 ipa_smp2p_in: ipa-modem-to-ap { 192 qcom,entry-name = "ipa"; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 }; 196 }; 197 198 soc: soc { 199 #address-cells = <1>; 200 #size-cells = <1>; 201 ranges; 202 compatible = "simple-bus"; 203 204 gcc: clock-controller@100000 { 205 compatible = "qcom,gcc-sdx65"; 206 reg = <0x00100000 0x001f7400>; 207 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; 208 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 209 #power-domain-cells = <1>; 210 #clock-cells = <1>; 211 #reset-cells = <1>; 212 }; 213 214 blsp1_uart3: serial@831000 { 215 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 216 reg = <0x00831000 0x200>; 217 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 219 clock-names = "core", "iface"; 220 status = "disabled"; 221 }; 222 223 usb_hsphy: phy@ff4000 { 224 compatible = "qcom,sdx65-usb-hs-phy", 225 "qcom,usb-snps-hs-7nm-phy"; 226 reg = <0xff4000 0x120>; 227 #phy-cells = <0>; 228 clocks = <&rpmhcc RPMH_CXO_CLK>; 229 clock-names = "ref"; 230 resets = <&gcc GCC_QUSB2PHY_BCR>; 231 status = "disabled"; 232 }; 233 234 usb_qmpphy: phy@ff6000 { 235 compatible = "qcom,sdx65-qmp-usb3-uni-phy"; 236 reg = <0x00ff6000 0x2000>; 237 238 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 239 <&gcc GCC_USB3_PRIM_CLKREF_EN>, 240 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 241 <&gcc GCC_USB3_PHY_PIPE_CLK>; 242 clock-names = "aux", 243 "ref", 244 "cfg_ahb", 245 "pipe"; 246 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 247 #clock-cells = <0>; 248 #phy-cells = <0>; 249 250 resets = <&gcc GCC_USB3_PHY_BCR>, 251 <&gcc GCC_USB3PHY_PHY_BCR>; 252 reset-names = "phy", 253 "phy_phy"; 254 255 status = "disabled"; 256 257 }; 258 259 system_noc: interconnect@1620000 { 260 compatible = "qcom,sdx65-system-noc"; 261 reg = <0x01620000 0x31200>; 262 #interconnect-cells = <1>; 263 qcom,bcm-voters = <&apps_bcm_voter>; 264 }; 265 266 qpic_bam: dma-controller@1b04000 { 267 compatible = "qcom,bam-v1.7.0"; 268 reg = <0x01b04000 0x1c000>; 269 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&rpmhcc RPMH_QPIC_CLK>; 271 clock-names = "bam_clk"; 272 #dma-cells = <1>; 273 qcom,ee = <0>; 274 qcom,controlled-remotely; 275 status = "disabled"; 276 }; 277 278 qpic_nand: nand-controller@1b30000 { 279 compatible = "qcom,sdx55-nand"; 280 reg = <0x01b30000 0x10000>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 clocks = <&rpmhcc RPMH_QPIC_CLK>, 284 <&nand_clk_dummy>; 285 clock-names = "core", "aon"; 286 287 dmas = <&qpic_bam 0>, 288 <&qpic_bam 1>, 289 <&qpic_bam 2>; 290 dma-names = "tx", "rx", "cmd"; 291 status = "disabled"; 292 }; 293 294 pcie_ep: pcie-ep@1c00000 { 295 compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; 296 reg = <0x01c00000 0x3000>, 297 <0x40000000 0xf1d>, 298 <0x40000f20 0xa8>, 299 <0x40001000 0x1000>, 300 <0x40200000 0x100000>, 301 <0x01c03000 0x3000>; 302 reg-names = "parf", 303 "dbi", 304 "elbi", 305 "atu", 306 "addr_space", 307 "mmio"; 308 309 qcom,perst-regs = <&tcsr 0xb258 0xb270>; 310 311 clocks = <&gcc GCC_PCIE_AUX_CLK>, 312 <&gcc GCC_PCIE_CFG_AHB_CLK>, 313 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 314 <&gcc GCC_PCIE_SLV_AXI_CLK>, 315 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 316 <&gcc GCC_PCIE_SLEEP_CLK>, 317 <&gcc GCC_PCIE_0_CLKREF_EN>; 318 clock-names = "aux", 319 "cfg", 320 "bus_master", 321 "bus_slave", 322 "slave_q2a", 323 "sleep", 324 "ref"; 325 326 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 328 interrupt-names = "global", "doorbell"; 329 330 resets = <&gcc GCC_PCIE_BCR>; 331 reset-names = "core"; 332 333 power-domains = <&gcc PCIE_GDSC>; 334 335 phys = <&pcie_phy>; 336 phy-names = "pciephy"; 337 338 max-link-speed = <3>; 339 num-lanes = <2>; 340 341 status = "disabled"; 342 }; 343 344 pcie_phy: phy@1c06000 { 345 compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; 346 reg = <0x01c06000 0x2000>; 347 348 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, 349 <&gcc GCC_PCIE_CFG_AHB_CLK>, 350 <&gcc GCC_PCIE_0_CLKREF_EN>, 351 <&gcc GCC_PCIE_RCHNG_PHY_CLK>, 352 <&gcc GCC_PCIE_PIPE_CLK>; 353 clock-names = "aux", 354 "cfg_ahb", 355 "ref", 356 "rchng", 357 "pipe"; 358 359 resets = <&gcc GCC_PCIE_PHY_BCR>; 360 reset-names = "phy"; 361 362 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; 363 assigned-clock-rates = <100000000>; 364 365 power-domains = <&gcc PCIE_GDSC>; 366 367 #clock-cells = <0>; 368 clock-output-names = "pcie_pipe_clk"; 369 370 #phy-cells = <0>; 371 372 status = "disabled"; 373 }; 374 375 tcsr_mutex: hwlock@1f40000 { 376 compatible = "qcom,tcsr-mutex"; 377 reg = <0x01f40000 0x40000>; 378 #hwlock-cells = <1>; 379 }; 380 381 tcsr: syscon@1fcb000 { 382 compatible = "qcom,sdx65-tcsr", "syscon"; 383 reg = <0x01fc0000 0x1000>; 384 }; 385 386 ipa: ipa@3f40000 { 387 compatible = "qcom,sdx65-ipa"; 388 389 reg = <0x03f40000 0x10000>, 390 <0x03f50000 0x5000>, 391 <0x03e04000 0xfc000>; 392 reg-names = "ipa-reg", 393 "ipa-shared", 394 "gsi"; 395 396 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 397 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 398 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 399 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 400 interrupt-names = "ipa", 401 "gsi", 402 "ipa-clock-query", 403 "ipa-setup-ready"; 404 405 iommus = <&apps_smmu 0x5e0 0x0>, 406 <&apps_smmu 0x5e2 0x0>; 407 408 clocks = <&rpmhcc RPMH_IPA_CLK>; 409 clock-names = "core"; 410 411 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 412 <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; 413 interconnect-names = "memory", 414 "config"; 415 416 qcom,smem-states = <&ipa_smp2p_out 0>, 417 <&ipa_smp2p_out 1>; 418 qcom,smem-state-names = "ipa-clock-enabled-valid", 419 "ipa-clock-enabled"; 420 421 status = "disabled"; 422 }; 423 424 remoteproc_mpss: remoteproc@4080000 { 425 compatible = "qcom,sdx55-mpss-pas"; 426 reg = <0x04080000 0x4040>; 427 428 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 429 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 430 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 431 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 432 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 433 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 434 interrupt-names = "wdog", "fatal", "ready", "handover", 435 "stop-ack", "shutdown-ack"; 436 437 clocks = <&rpmhcc RPMH_CXO_CLK>; 438 clock-names = "xo"; 439 440 power-domains = <&rpmhpd SDX65_CX>, 441 <&rpmhpd SDX65_MSS>; 442 power-domain-names = "cx", "mss"; 443 444 qcom,smem-states = <&modem_smp2p_out 0>; 445 qcom,smem-state-names = "stop"; 446 447 status = "disabled"; 448 449 glink-edge { 450 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 451 label = "mpss"; 452 qcom,remote-pid = <1>; 453 mboxes = <&apcs 15>; 454 }; 455 }; 456 457 sdhc_1: mmc@8804000 { 458 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 459 reg = <0x08804000 0x1000>; 460 reg-names = "hc"; 461 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "hc_irq", "pwr_irq"; 464 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 465 <&gcc GCC_SDCC1_APPS_CLK>; 466 clock-names = "iface", "core"; 467 status = "disabled"; 468 }; 469 470 mem_noc: interconnect@9680000 { 471 compatible = "qcom,sdx65-mem-noc"; 472 reg = <0x09680000 0x27200>; 473 #interconnect-cells = <1>; 474 qcom,bcm-voters = <&apps_bcm_voter>; 475 }; 476 477 usb: usb@a6f8800 { 478 compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; 479 reg = <0x0a6f8800 0x400>; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 ranges; 483 484 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 485 <&gcc GCC_USB30_MASTER_CLK>, 486 <&gcc GCC_USB30_MSTR_AXI_CLK>, 487 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 488 <&gcc GCC_USB30_SLEEP_CLK>; 489 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 490 "sleep"; 491 492 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 493 <&gcc GCC_USB30_MASTER_CLK>; 494 assigned-clock-rates = <19200000>, <200000000>; 495 496 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 497 <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, 498 <&pdc 18 IRQ_TYPE_EDGE_BOTH>, 499 <&pdc 19 IRQ_TYPE_EDGE_BOTH>; 500 interrupt-names = "hs_phy_irq", 501 "ss_phy_irq", 502 "dm_hs_phy_irq", 503 "dp_hs_phy_irq"; 504 505 power-domains = <&gcc USB30_GDSC>; 506 507 resets = <&gcc GCC_USB30_BCR>; 508 509 status = "disabled"; 510 511 usb_dwc3: usb@a600000 { 512 compatible = "snps,dwc3"; 513 reg = <0x0a600000 0xcd00>; 514 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 515 iommus = <&apps_smmu 0x1a0 0x0>; 516 snps,dis_u2_susphy_quirk; 517 snps,dis_enblslpm_quirk; 518 phys = <&usb_hsphy>, <&usb_qmpphy>; 519 phy-names = "usb2-phy", "usb3-phy"; 520 }; 521 }; 522 523 restart@c264000 { 524 compatible = "qcom,pshold"; 525 reg = <0x0c264000 0x1000>; 526 }; 527 528 spmi_bus: qcom,spmi@c440000 { 529 compatible = "qcom,spmi-pmic-arb"; 530 reg = <0xc440000 0xd00>, 531 <0xc600000 0x2000000>, 532 <0xe600000 0x100000>, 533 <0xe700000 0xa0000>, 534 <0xc40a000 0x26000>; 535 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 536 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 537 interrupt-names = "periph_irq"; 538 interrupt-controller; 539 #interrupt-cells = <4>; 540 #address-cells = <2>; 541 #size-cells = <0>; 542 qcom,channel = <0>; 543 qcom,ee = <0>; 544 }; 545 546 tlmm: pinctrl@f100000 { 547 compatible = "qcom,sdx65-tlmm"; 548 reg = <0xf100000 0x300000>; 549 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 gpio-ranges = <&tlmm 0 0 109>; 553 interrupt-controller; 554 interrupt-parent = <&intc>; 555 #interrupt-cells = <2>; 556 }; 557 558 pdc: interrupt-controller@b210000 { 559 compatible = "qcom,sdx65-pdc", "qcom,pdc"; 560 reg = <0xb210000 0x10000>; 561 qcom,pdc-ranges = <0 147 52>, <52 266 32>; 562 #interrupt-cells = <2>; 563 interrupt-parent = <&intc>; 564 interrupt-controller; 565 }; 566 567 sram@1468f000 { 568 compatible = "qcom,sdx65-imem", "syscon", "simple-mfd"; 569 reg = <0x1468f000 0x1000>; 570 ranges = <0x0 0x1468f000 0x1000>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 574 pil-reloc@94c { 575 compatible = "qcom,pil-reloc-info"; 576 reg = <0x94c 0xc8>; 577 }; 578 }; 579 580 apps_smmu: iommu@15000000 { 581 compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 582 reg = <0x15000000 0x40000>; 583 #iommu-cells = <2>; 584 #global-interrupts = <1>; 585 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 618 }; 619 620 intc: interrupt-controller@17800000 { 621 compatible = "qcom,msm-qgic2"; 622 interrupt-controller; 623 interrupt-parent = <&intc>; 624 #interrupt-cells = <3>; 625 reg = <0x17800000 0x1000>, 626 <0x17802000 0x1000>; 627 }; 628 629 a7pll: clock@17808000 { 630 compatible = "qcom,sdx55-a7pll"; 631 reg = <0x17808000 0x1000>; 632 clocks = <&rpmhcc RPMH_CXO_CLK>; 633 clock-names = "bi_tcxo"; 634 #clock-cells = <0>; 635 }; 636 637 apcs: mailbox@17810000 { 638 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 639 reg = <0x17810000 0x2000>; 640 #mbox-cells = <1>; 641 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 642 clock-names = "ref", "pll", "aux"; 643 #clock-cells = <0>; 644 }; 645 646 watchdog@17817000 { 647 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; 648 reg = <0x17817000 0x1000>; 649 clocks = <&sleep_clk>; 650 }; 651 652 timer@17820000 { 653 #address-cells = <1>; 654 #size-cells = <1>; 655 ranges; 656 compatible = "arm,armv7-timer-mem"; 657 reg = <0x17820000 0x1000>; 658 clock-frequency = <19200000>; 659 660 frame@17821000 { 661 frame-number = <0>; 662 interrupts = <GIC_SPI 7 0x4>, 663 <GIC_SPI 6 0x4>; 664 reg = <0x17821000 0x1000>, 665 <0x17822000 0x1000>; 666 }; 667 668 frame@17823000 { 669 frame-number = <1>; 670 interrupts = <GIC_SPI 8 0x4>; 671 reg = <0x17823000 0x1000>; 672 status = "disabled"; 673 }; 674 675 frame@17824000 { 676 frame-number = <2>; 677 interrupts = <GIC_SPI 9 0x4>; 678 reg = <0x17824000 0x1000>; 679 status = "disabled"; 680 }; 681 682 frame@17825000 { 683 frame-number = <3>; 684 interrupts = <GIC_SPI 10 0x4>; 685 reg = <0x17825000 0x1000>; 686 status = "disabled"; 687 }; 688 689 frame@17826000 { 690 frame-number = <4>; 691 interrupts = <GIC_SPI 11 0x4>; 692 reg = <0x17826000 0x1000>; 693 status = "disabled"; 694 }; 695 696 frame@17827000 { 697 frame-number = <5>; 698 interrupts = <GIC_SPI 12 0x4>; 699 reg = <0x17827000 0x1000>; 700 status = "disabled"; 701 }; 702 703 frame@17828000 { 704 frame-number = <6>; 705 interrupts = <GIC_SPI 13 0x4>; 706 reg = <0x17828000 0x1000>; 707 status = "disabled"; 708 }; 709 710 frame@17829000 { 711 frame-number = <7>; 712 interrupts = <GIC_SPI 14 0x4>; 713 reg = <0x17829000 0x1000>; 714 status = "disabled"; 715 }; 716 }; 717 718 apps_rsc: rsc@17830000 { 719 label = "apps_rsc"; 720 compatible = "qcom,rpmh-rsc"; 721 reg = <0x17830000 0x10000>, 722 <0x17840000 0x10000>; 723 reg-names = "drv-0", "drv-1"; 724 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 726 qcom,tcs-offset = <0xd00>; 727 qcom,drv-id = <1>; 728 qcom,tcs-config = <ACTIVE_TCS 2>, 729 <SLEEP_TCS 2>, 730 <WAKE_TCS 2>, 731 <CONTROL_TCS 1>; 732 733 rpmhcc: clock-controller { 734 compatible = "qcom,sdx65-rpmh-clk"; 735 #clock-cells = <1>; 736 clock-names = "xo"; 737 clocks = <&xo_board>; 738 }; 739 740 rpmhpd: power-controller { 741 compatible = "qcom,sdx65-rpmhpd"; 742 #power-domain-cells = <1>; 743 operating-points-v2 = <&rpmhpd_opp_table>; 744 745 rpmhpd_opp_table: opp-table { 746 compatible = "operating-points-v2"; 747 748 rpmhpd_opp_ret: opp1 { 749 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 750 }; 751 752 rpmhpd_opp_min_svs: opp2 { 753 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 754 }; 755 756 rpmhpd_opp_low_svs: opp3 { 757 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 758 }; 759 760 rpmhpd_opp_svs: opp4 { 761 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 762 }; 763 764 rpmhpd_opp_svs_l1: opp5 { 765 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 766 }; 767 768 rpmhpd_opp_nom: opp6 { 769 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 770 }; 771 772 rpmhpd_opp_nom_l1: opp7 { 773 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 774 }; 775 776 rpmhpd_opp_nom_l2: opp8 { 777 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 778 }; 779 780 rpmhpd_opp_turbo: opp9 { 781 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 782 }; 783 784 rpmhpd_opp_turbo_l1: opp10 { 785 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 786 }; 787 }; 788 }; 789 790 apps_bcm_voter: bcm-voter { 791 compatible = "qcom,bcm-voter"; 792 }; 793 794 }; 795 }; 796 797 timer { 798 compatible = "arm,armv7-timer"; 799 interrupts = <1 13 0xf08>, 800 <1 12 0xf08>, 801 <1 10 0xf08>, 802 <1 11 0xf08>; 803 clock-frequency = <19200000>; 804 }; 805}; 806