1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX55 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2020, Linaro Ltd. 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx55.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,sdx55.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; 21 interrupt-parent = <&intc>; 22 23 memory { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <38400000>; 33 clock-output-names = "xo_board"; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32000>; 40 }; 41 42 nand_clk_dummy: nand-clk-dummy { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <32000>; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0x0>; 57 enable-method = "psci"; 58 clocks = <&apcs>; 59 power-domains = <&rpmhpd SDX55_CX>; 60 power-domain-names = "rpmhpd"; 61 operating-points-v2 = <&cpu_opp_table>; 62 }; 63 }; 64 65 firmware { 66 scm { 67 compatible = "qcom,scm-sdx55", "qcom,scm"; 68 }; 69 }; 70 71 cpu_opp_table: opp-table-cpu { 72 compatible = "operating-points-v2"; 73 opp-shared; 74 75 opp-345600000 { 76 opp-hz = /bits/ 64 <345600000>; 77 required-opps = <&rpmhpd_opp_low_svs>; 78 }; 79 80 opp-576000000 { 81 opp-hz = /bits/ 64 <576000000>; 82 required-opps = <&rpmhpd_opp_svs>; 83 }; 84 85 opp-1094400000 { 86 opp-hz = /bits/ 64 <1094400000>; 87 required-opps = <&rpmhpd_opp_nom>; 88 }; 89 90 opp-1555200000 { 91 opp-hz = /bits/ 64 <1555200000>; 92 required-opps = <&rpmhpd_opp_turbo>; 93 }; 94 }; 95 96 psci { 97 compatible = "arm,psci-1.0"; 98 method = "smc"; 99 }; 100 101 reserved-memory { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges; 105 106 hyp_mem: memory@8fc00000 { 107 no-map; 108 reg = <0x8fc00000 0x80000>; 109 }; 110 111 ac_db_mem: memory@8fc80000 { 112 no-map; 113 reg = <0x8fc80000 0x40000>; 114 }; 115 116 secdata_mem: memory@8fcfd000 { 117 no-map; 118 reg = <0x8fcfd000 0x1000>; 119 }; 120 121 sbl_mem: memory@8fd00000 { 122 no-map; 123 reg = <0x8fd00000 0x100000>; 124 }; 125 126 aop_image: memory@8fe00000 { 127 no-map; 128 reg = <0x8fe00000 0x20000>; 129 }; 130 131 aop_cmd_db: memory@8fe20000 { 132 compatible = "qcom,cmd-db"; 133 reg = <0x8fe20000 0x20000>; 134 no-map; 135 }; 136 137 smem_mem: memory@8fe40000 { 138 no-map; 139 reg = <0x8fe40000 0xc0000>; 140 }; 141 142 tz_mem: memory@8ff00000 { 143 no-map; 144 reg = <0x8ff00000 0x100000>; 145 }; 146 147 tz_apps_mem: memory@90000000 { 148 no-map; 149 reg = <0x90000000 0x500000>; 150 }; 151 }; 152 153 smem { 154 compatible = "qcom,smem"; 155 memory-region = <&smem_mem>; 156 hwlocks = <&tcsr_mutex 3>; 157 }; 158 159 smp2p-mpss { 160 compatible = "qcom,smp2p"; 161 qcom,smem = <435>, <428>; 162 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 163 mboxes = <&apcs 14>; 164 qcom,local-pid = <0>; 165 qcom,remote-pid = <1>; 166 167 modem_smp2p_out: master-kernel { 168 qcom,entry-name = "master-kernel"; 169 #qcom,smem-state-cells = <1>; 170 }; 171 172 modem_smp2p_in: slave-kernel { 173 qcom,entry-name = "slave-kernel"; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 }; 177 178 ipa_smp2p_out: ipa-ap-to-modem { 179 qcom,entry-name = "ipa"; 180 #qcom,smem-state-cells = <1>; 181 }; 182 183 ipa_smp2p_in: ipa-modem-to-ap { 184 qcom,entry-name = "ipa"; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 }; 188 }; 189 190 soc: soc { 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges; 194 compatible = "simple-bus"; 195 196 gcc: clock-controller@100000 { 197 compatible = "qcom,gcc-sdx55"; 198 reg = <0x100000 0x1f0000>; 199 #clock-cells = <1>; 200 #reset-cells = <1>; 201 #power-domain-cells = <1>; 202 clock-names = "bi_tcxo", "sleep_clk"; 203 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 204 }; 205 206 blsp1_uart3: serial@831000 { 207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 208 reg = <0x00831000 0x200>; 209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&gcc 30>, 211 <&gcc 9>; 212 clock-names = "core", "iface"; 213 status = "disabled"; 214 }; 215 216 usb_hsphy: phy@ff4000 { 217 compatible = "qcom,sdx55-usb-hs-phy", 218 "qcom,usb-snps-hs-7nm-phy"; 219 reg = <0x00ff4000 0x114>; 220 status = "disabled"; 221 #phy-cells = <0>; 222 223 clocks = <&rpmhcc RPMH_CXO_CLK>; 224 clock-names = "ref"; 225 226 resets = <&gcc GCC_QUSB2PHY_BCR>; 227 }; 228 229 usb_qmpphy: phy@ff6000 { 230 compatible = "qcom,sdx55-qmp-usb3-uni-phy"; 231 reg = <0x00ff6000 0x1000>; 232 233 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 234 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 235 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 236 <&gcc GCC_USB3_PHY_PIPE_CLK>; 237 clock-names = "aux", 238 "ref", 239 "cfg_ahb", 240 "pipe"; 241 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 242 #clock-cells = <0>; 243 #phy-cells = <0>; 244 245 resets = <&gcc GCC_USB3_PHY_BCR>, 246 <&gcc GCC_USB3PHY_PHY_BCR>; 247 reset-names = "phy", 248 "phy_phy"; 249 250 status = "disabled"; 251 }; 252 253 mc_virt: interconnect@1100000 { 254 compatible = "qcom,sdx55-mc-virt"; 255 reg = <0x01100000 0x400000>; 256 #interconnect-cells = <1>; 257 qcom,bcm-voters = <&apps_bcm_voter>; 258 }; 259 260 mem_noc: interconnect@9680000 { 261 compatible = "qcom,sdx55-mem-noc"; 262 reg = <0x09680000 0x40000>; 263 #interconnect-cells = <1>; 264 qcom,bcm-voters = <&apps_bcm_voter>; 265 }; 266 267 system_noc: interconnect@162c000 { 268 compatible = "qcom,sdx55-system-noc"; 269 reg = <0x0162c000 0x31200>; 270 #interconnect-cells = <1>; 271 qcom,bcm-voters = <&apps_bcm_voter>; 272 }; 273 274 qpic_bam: dma-controller@1b04000 { 275 compatible = "qcom,bam-v1.7.0"; 276 reg = <0x01b04000 0x1c000>; 277 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&rpmhcc RPMH_QPIC_CLK>; 279 clock-names = "bam_clk"; 280 #dma-cells = <1>; 281 qcom,ee = <0>; 282 qcom,controlled-remotely; 283 status = "disabled"; 284 }; 285 286 qpic_nand: nand-controller@1b30000 { 287 compatible = "qcom,sdx55-nand"; 288 reg = <0x01b30000 0x10000>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 clocks = <&rpmhcc RPMH_QPIC_CLK>, 292 <&nand_clk_dummy>; 293 clock-names = "core", "aon"; 294 295 dmas = <&qpic_bam 0>, 296 <&qpic_bam 1>, 297 <&qpic_bam 2>; 298 dma-names = "tx", "rx", "cmd"; 299 status = "disabled"; 300 }; 301 302 pcie_rc: pcie@1c00000 { 303 compatible = "qcom,pcie-sdx55"; 304 reg = <0x01c00000 0x3000>, 305 <0x40000000 0xf1d>, 306 <0x40000f20 0xc8>, 307 <0x40001000 0x1000>, 308 <0x40100000 0x100000>; 309 reg-names = "parf", 310 "dbi", 311 "elbi", 312 "atu", 313 "config"; 314 device_type = "pci"; 315 linux,pci-domain = <0>; 316 bus-range = <0x00 0xff>; 317 num-lanes = <1>; 318 319 #address-cells = <3>; 320 #size-cells = <2>; 321 322 ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, 323 <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; 324 325 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 333 interrupt-names = "msi", 334 "msi2", 335 "msi3", 336 "msi4", 337 "msi5", 338 "msi6", 339 "msi7", 340 "msi8"; 341 #interrupt-cells = <1>; 342 interrupt-map-mask = <0 0 0 0x7>; 343 interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 344 <0 0 0 2 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 345 <0 0 0 3 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 346 <0 0 0 4 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 347 348 clocks = <&gcc GCC_PCIE_PIPE_CLK>, 349 <&gcc GCC_PCIE_AUX_CLK>, 350 <&gcc GCC_PCIE_CFG_AHB_CLK>, 351 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 352 <&gcc GCC_PCIE_SLV_AXI_CLK>, 353 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 354 <&gcc GCC_PCIE_SLEEP_CLK>; 355 clock-names = "pipe", 356 "aux", 357 "cfg", 358 "bus_master", 359 "bus_slave", 360 "slave_q2a", 361 "sleep"; 362 363 assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; 364 assigned-clock-rates = <19200000>; 365 366 iommu-map = <0x0 &apps_smmu 0x0200 0x1>, 367 <0x100 &apps_smmu 0x0201 0x1>, 368 <0x200 &apps_smmu 0x0202 0x1>, 369 <0x300 &apps_smmu 0x0203 0x1>, 370 <0x400 &apps_smmu 0x0204 0x1>; 371 372 resets = <&gcc GCC_PCIE_BCR>; 373 reset-names = "pci"; 374 375 power-domains = <&gcc PCIE_GDSC>; 376 377 phys = <&pcie_phy>; 378 phy-names = "pciephy"; 379 380 status = "disabled"; 381 }; 382 383 pcie_ep: pcie-ep@1c00000 { 384 compatible = "qcom,sdx55-pcie-ep"; 385 reg = <0x01c00000 0x3000>, 386 <0x40000000 0xf1d>, 387 <0x40000f20 0xc8>, 388 <0x40001000 0x1000>, 389 <0x40200000 0x100000>, 390 <0x01c03000 0x3000>; 391 reg-names = "parf", 392 "dbi", 393 "elbi", 394 "atu", 395 "addr_space", 396 "mmio"; 397 398 qcom,perst-regs = <&tcsr 0xb258 0xb270>; 399 400 clocks = <&gcc GCC_PCIE_AUX_CLK>, 401 <&gcc GCC_PCIE_CFG_AHB_CLK>, 402 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 403 <&gcc GCC_PCIE_SLV_AXI_CLK>, 404 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 405 <&gcc GCC_PCIE_SLEEP_CLK>, 406 <&gcc GCC_PCIE_0_CLKREF_CLK>; 407 clock-names = "aux", 408 "cfg", 409 "bus_master", 410 "bus_slave", 411 "slave_q2a", 412 "sleep", 413 "ref"; 414 415 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-names = "global", 418 "doorbell"; 419 420 interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; 421 interconnect-names = "pcie-mem"; 422 423 resets = <&gcc GCC_PCIE_BCR>; 424 reset-names = "core"; 425 power-domains = <&gcc PCIE_GDSC>; 426 phys = <&pcie_phy>; 427 phy-names = "pciephy"; 428 max-link-speed = <3>; 429 num-lanes = <2>; 430 431 status = "disabled"; 432 }; 433 434 pcie_phy: phy@1c06000 { 435 compatible = "qcom,sdx55-qmp-pcie-phy"; 436 reg = <0x01c06000 0x2000>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges; 440 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, 441 <&gcc GCC_PCIE_CFG_AHB_CLK>, 442 <&gcc GCC_PCIE_0_CLKREF_CLK>, 443 <&gcc GCC_PCIE_RCHNG_PHY_CLK>, 444 <&gcc GCC_PCIE_PIPE_CLK>; 445 clock-names = "aux", 446 "cfg_ahb", 447 "ref", 448 "refgen", 449 "pipe"; 450 451 clock-output-names = "pcie_pipe_clk"; 452 #clock-cells = <0>; 453 454 #phy-cells = <0>; 455 456 resets = <&gcc GCC_PCIE_PHY_BCR>; 457 reset-names = "phy"; 458 459 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; 460 assigned-clock-rates = <100000000>; 461 462 status = "disabled"; 463 }; 464 465 ipa: ipa@1e40000 { 466 compatible = "qcom,sdx55-ipa"; 467 468 iommus = <&apps_smmu 0x5e0 0x0>, 469 <&apps_smmu 0x5e2 0x0>; 470 reg = <0x1e40000 0x7000>, 471 <0x1e50000 0x4b20>, 472 <0x1e04000 0x2c000>; 473 reg-names = "ipa-reg", 474 "ipa-shared", 475 "gsi"; 476 477 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 478 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 479 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 480 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 481 interrupt-names = "ipa", 482 "gsi", 483 "ipa-clock-query", 484 "ipa-setup-ready"; 485 486 clocks = <&rpmhcc RPMH_IPA_CLK>; 487 clock-names = "core"; 488 489 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, 490 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, 491 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; 492 interconnect-names = "memory", 493 "imem", 494 "config"; 495 496 qcom,smem-states = <&ipa_smp2p_out 0>, 497 <&ipa_smp2p_out 1>; 498 qcom,smem-state-names = "ipa-clock-enabled-valid", 499 "ipa-clock-enabled"; 500 501 status = "disabled"; 502 }; 503 504 tcsr_mutex: hwlock@1f40000 { 505 compatible = "qcom,tcsr-mutex"; 506 reg = <0x01f40000 0x40000>; 507 #hwlock-cells = <1>; 508 }; 509 510 tcsr: syscon@1fc0000 { 511 compatible = "qcom,sdx55-tcsr", "syscon"; 512 reg = <0x01fc0000 0x1000>; 513 }; 514 515 sdhc_1: mmc@8804000 { 516 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; 517 reg = <0x08804000 0x1000>; 518 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 520 interrupt-names = "hc_irq", "pwr_irq"; 521 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 522 <&gcc GCC_SDCC1_APPS_CLK>; 523 clock-names = "iface", "core"; 524 status = "disabled"; 525 }; 526 527 remoteproc_mpss: remoteproc@4080000 { 528 compatible = "qcom,sdx55-mpss-pas"; 529 reg = <0x04080000 0x4040>; 530 531 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 532 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 533 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 534 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 535 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 536 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 537 interrupt-names = "wdog", "fatal", "ready", "handover", 538 "stop-ack", "shutdown-ack"; 539 540 clocks = <&rpmhcc RPMH_CXO_CLK>; 541 clock-names = "xo"; 542 543 power-domains = <&rpmhpd SDX55_CX>, 544 <&rpmhpd SDX55_MSS>; 545 power-domain-names = "cx", "mss"; 546 547 qcom,smem-states = <&modem_smp2p_out 0>; 548 qcom,smem-state-names = "stop"; 549 550 status = "disabled"; 551 552 glink-edge { 553 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 554 label = "mpss"; 555 qcom,remote-pid = <1>; 556 mboxes = <&apcs 15>; 557 }; 558 }; 559 560 usb: usb@a6f8800 { 561 compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; 562 reg = <0x0a6f8800 0x400>; 563 status = "disabled"; 564 #address-cells = <1>; 565 #size-cells = <1>; 566 ranges; 567 568 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 569 <&gcc GCC_USB30_MASTER_CLK>, 570 <&gcc GCC_USB30_MSTR_AXI_CLK>, 571 <&gcc GCC_USB30_SLEEP_CLK>, 572 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 573 clock-names = "cfg_noc", 574 "core", 575 "iface", 576 "sleep", 577 "mock_utmi"; 578 579 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 580 <&gcc GCC_USB30_MASTER_CLK>; 581 assigned-clock-rates = <19200000>, <200000000>; 582 583 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 584 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 585 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 586 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 587 <&pdc 51 IRQ_TYPE_LEVEL_HIGH>; 588 interrupt-names = "pwr_event", 589 "hs_phy_irq", 590 "dp_hs_phy_irq", 591 "dm_hs_phy_irq", 592 "ss_phy_irq"; 593 594 power-domains = <&gcc USB30_GDSC>; 595 596 resets = <&gcc GCC_USB30_BCR>; 597 598 usb_dwc3: usb@a600000 { 599 compatible = "snps,dwc3"; 600 reg = <0x0a600000 0xcd00>; 601 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 602 iommus = <&apps_smmu 0x1a0 0x0>; 603 snps,dis_u2_susphy_quirk; 604 snps,dis_enblslpm_quirk; 605 phys = <&usb_hsphy>, <&usb_qmpphy>; 606 phy-names = "usb2-phy", "usb3-phy"; 607 }; 608 }; 609 610 pdc: interrupt-controller@b210000 { 611 compatible = "qcom,sdx55-pdc", "qcom,pdc"; 612 reg = <0x0b210000 0x30000>; 613 qcom,pdc-ranges = <0 179 52>; 614 #interrupt-cells = <2>; 615 interrupt-parent = <&intc>; 616 interrupt-controller; 617 }; 618 619 restart@c264000 { 620 compatible = "qcom,pshold"; 621 reg = <0x0c264000 0x1000>; 622 }; 623 624 spmi_bus: spmi@c440000 { 625 compatible = "qcom,spmi-pmic-arb"; 626 reg = <0x0c440000 0x0000d00>, 627 <0x0c600000 0x2000000>, 628 <0x0e600000 0x0100000>, 629 <0x0e700000 0x00a0000>, 630 <0x0c40a000 0x0000700>; 631 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 632 interrupt-names = "periph_irq"; 633 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 634 qcom,ee = <0>; 635 qcom,channel = <0>; 636 #address-cells = <2>; 637 #size-cells = <0>; 638 interrupt-controller; 639 #interrupt-cells = <4>; 640 }; 641 642 tlmm: pinctrl@f100000 { 643 compatible = "qcom,sdx55-pinctrl"; 644 reg = <0xf100000 0x300000>; 645 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 646 gpio-controller; 647 #gpio-cells = <2>; 648 interrupt-controller; 649 #interrupt-cells = <2>; 650 gpio-ranges = <&tlmm 0 0 108>; 651 }; 652 653 sram@1468f000 { 654 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; 655 reg = <0x1468f000 0x1000>; 656 657 #address-cells = <1>; 658 #size-cells = <1>; 659 660 ranges = <0x0 0x1468f000 0x1000>; 661 662 pil-reloc@94c { 663 compatible = "qcom,pil-reloc-info"; 664 reg = <0x94c 0x200>; 665 }; 666 }; 667 668 apps_smmu: iommu@15000000 { 669 compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 670 reg = <0x15000000 0x20000>; 671 #iommu-cells = <2>; 672 #global-interrupts = <1>; 673 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 690 }; 691 692 intc: interrupt-controller@17800000 { 693 compatible = "qcom,msm-qgic2"; 694 interrupt-controller; 695 interrupt-parent = <&intc>; 696 #interrupt-cells = <3>; 697 reg = <0x17800000 0x1000>, 698 <0x17802000 0x1000>; 699 }; 700 701 a7pll: clock@17808000 { 702 compatible = "qcom,sdx55-a7pll"; 703 reg = <0x17808000 0x1000>; 704 clocks = <&rpmhcc RPMH_CXO_CLK>; 705 clock-names = "bi_tcxo"; 706 #clock-cells = <0>; 707 }; 708 709 apcs: mailbox@17810000 { 710 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 711 reg = <0x17810000 0x2000>; 712 #mbox-cells = <1>; 713 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 714 clock-names = "ref", "pll", "aux"; 715 #clock-cells = <0>; 716 }; 717 718 watchdog@17817000 { 719 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; 720 reg = <0x17817000 0x1000>; 721 clocks = <&sleep_clk>; 722 }; 723 724 timer@17820000 { 725 #address-cells = <1>; 726 #size-cells = <1>; 727 ranges; 728 compatible = "arm,armv7-timer-mem"; 729 reg = <0x17820000 0x1000>; 730 clock-frequency = <19200000>; 731 732 frame@17821000 { 733 frame-number = <0>; 734 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 736 reg = <0x17821000 0x1000>, 737 <0x17822000 0x1000>; 738 }; 739 740 frame@17823000 { 741 frame-number = <1>; 742 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 743 reg = <0x17823000 0x1000>; 744 status = "disabled"; 745 }; 746 747 frame@17824000 { 748 frame-number = <2>; 749 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 750 reg = <0x17824000 0x1000>; 751 status = "disabled"; 752 }; 753 754 frame@17825000 { 755 frame-number = <3>; 756 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 757 reg = <0x17825000 0x1000>; 758 status = "disabled"; 759 }; 760 761 frame@17826000 { 762 frame-number = <4>; 763 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 764 reg = <0x17826000 0x1000>; 765 status = "disabled"; 766 }; 767 768 frame@17827000 { 769 frame-number = <5>; 770 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 771 reg = <0x17827000 0x1000>; 772 status = "disabled"; 773 }; 774 775 frame@17828000 { 776 frame-number = <6>; 777 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0x17828000 0x1000>; 779 status = "disabled"; 780 }; 781 782 frame@17829000 { 783 frame-number = <7>; 784 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 785 reg = <0x17829000 0x1000>; 786 status = "disabled"; 787 }; 788 }; 789 790 apps_rsc: rsc@17830000 { 791 compatible = "qcom,rpmh-rsc"; 792 reg = <0x17830000 0x10000>, <0x17840000 0x10000>; 793 reg-names = "drv-0", "drv-1"; 794 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 796 qcom,tcs-offset = <0xd00>; 797 qcom,drv-id = <1>; 798 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>, 799 <WAKE_TCS 2>, <CONTROL_TCS 1>; 800 801 rpmhcc: clock-controller { 802 compatible = "qcom,sdx55-rpmh-clk"; 803 #clock-cells = <1>; 804 clock-names = "xo"; 805 clocks = <&xo_board>; 806 }; 807 808 rpmhpd: power-controller { 809 compatible = "qcom,sdx55-rpmhpd"; 810 #power-domain-cells = <1>; 811 operating-points-v2 = <&rpmhpd_opp_table>; 812 813 rpmhpd_opp_table: opp-table { 814 compatible = "operating-points-v2"; 815 816 rpmhpd_opp_ret: opp1 { 817 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 818 }; 819 820 rpmhpd_opp_min_svs: opp2 { 821 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 822 }; 823 824 rpmhpd_opp_low_svs: opp3 { 825 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 826 }; 827 828 rpmhpd_opp_svs: opp4 { 829 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 830 }; 831 832 rpmhpd_opp_svs_l1: opp5 { 833 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 834 }; 835 836 rpmhpd_opp_nom: opp6 { 837 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 838 }; 839 840 rpmhpd_opp_nom_l1: opp7 { 841 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 842 }; 843 844 rpmhpd_opp_nom_l2: opp8 { 845 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 846 }; 847 848 rpmhpd_opp_turbo: opp9 { 849 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 850 }; 851 852 rpmhpd_opp_turbo_l1: opp10 { 853 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 854 }; 855 }; 856 }; 857 858 apps_bcm_voter: bcm-voter { 859 compatible = "qcom,bcm-voter"; 860 }; 861 }; 862 }; 863 864 timer { 865 compatible = "arm,armv7-timer"; 866 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 867 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 868 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 869 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 870 clock-frequency = <19200000>; 871 }; 872}; 873