1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX55 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2020, Linaro Ltd. 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx55.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,sdx55.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; 21 interrupt-parent = <&intc>; 22 23 memory { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <38400000>; 33 clock-output-names = "xo_board"; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32000>; 40 }; 41 42 nand_clk_dummy: nand-clk-dummy { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <32000>; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0x0>; 57 enable-method = "psci"; 58 clocks = <&apcs>; 59 power-domains = <&rpmhpd SDX55_CX>; 60 power-domain-names = "rpmhpd"; 61 operating-points-v2 = <&cpu_opp_table>; 62 }; 63 }; 64 65 firmware { 66 scm { 67 compatible = "qcom,scm-sdx55", "qcom,scm"; 68 }; 69 }; 70 71 cpu_opp_table: opp-table-cpu { 72 compatible = "operating-points-v2"; 73 opp-shared; 74 75 opp-345600000 { 76 opp-hz = /bits/ 64 <345600000>; 77 required-opps = <&rpmhpd_opp_low_svs>; 78 }; 79 80 opp-576000000 { 81 opp-hz = /bits/ 64 <576000000>; 82 required-opps = <&rpmhpd_opp_svs>; 83 }; 84 85 opp-1094400000 { 86 opp-hz = /bits/ 64 <1094400000>; 87 required-opps = <&rpmhpd_opp_nom>; 88 }; 89 90 opp-1555200000 { 91 opp-hz = /bits/ 64 <1555200000>; 92 required-opps = <&rpmhpd_opp_turbo>; 93 }; 94 }; 95 96 psci { 97 compatible = "arm,psci-1.0"; 98 method = "smc"; 99 }; 100 101 reserved-memory { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges; 105 106 hyp_mem: memory@8fc00000 { 107 no-map; 108 reg = <0x8fc00000 0x80000>; 109 }; 110 111 ac_db_mem: memory@8fc80000 { 112 no-map; 113 reg = <0x8fc80000 0x40000>; 114 }; 115 116 secdata_mem: memory@8fcfd000 { 117 no-map; 118 reg = <0x8fcfd000 0x1000>; 119 }; 120 121 sbl_mem: memory@8fd00000 { 122 no-map; 123 reg = <0x8fd00000 0x100000>; 124 }; 125 126 aop_image: memory@8fe00000 { 127 no-map; 128 reg = <0x8fe00000 0x20000>; 129 }; 130 131 aop_cmd_db: memory@8fe20000 { 132 compatible = "qcom,cmd-db"; 133 reg = <0x8fe20000 0x20000>; 134 no-map; 135 }; 136 137 smem_mem: memory@8fe40000 { 138 no-map; 139 reg = <0x8fe40000 0xc0000>; 140 }; 141 142 tz_mem: memory@8ff00000 { 143 no-map; 144 reg = <0x8ff00000 0x100000>; 145 }; 146 147 tz_apps_mem: memory@90000000 { 148 no-map; 149 reg = <0x90000000 0x500000>; 150 }; 151 }; 152 153 smem { 154 compatible = "qcom,smem"; 155 memory-region = <&smem_mem>; 156 hwlocks = <&tcsr_mutex 3>; 157 }; 158 159 smp2p-mpss { 160 compatible = "qcom,smp2p"; 161 qcom,smem = <435>, <428>; 162 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 163 mboxes = <&apcs 14>; 164 qcom,local-pid = <0>; 165 qcom,remote-pid = <1>; 166 167 modem_smp2p_out: master-kernel { 168 qcom,entry-name = "master-kernel"; 169 #qcom,smem-state-cells = <1>; 170 }; 171 172 modem_smp2p_in: slave-kernel { 173 qcom,entry-name = "slave-kernel"; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 }; 177 178 ipa_smp2p_out: ipa-ap-to-modem { 179 qcom,entry-name = "ipa"; 180 #qcom,smem-state-cells = <1>; 181 }; 182 183 ipa_smp2p_in: ipa-modem-to-ap { 184 qcom,entry-name = "ipa"; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 }; 188 }; 189 190 soc: soc { 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges; 194 compatible = "simple-bus"; 195 196 gcc: clock-controller@100000 { 197 compatible = "qcom,gcc-sdx55"; 198 reg = <0x100000 0x1f0000>; 199 #clock-cells = <1>; 200 #reset-cells = <1>; 201 #power-domain-cells = <1>; 202 clock-names = "bi_tcxo", "sleep_clk"; 203 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 204 }; 205 206 blsp1_uart3: serial@831000 { 207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 208 reg = <0x00831000 0x200>; 209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&gcc 30>, 211 <&gcc 9>; 212 clock-names = "core", "iface"; 213 status = "disabled"; 214 }; 215 216 usb_hsphy: phy@ff4000 { 217 compatible = "qcom,sdx55-usb-hs-phy", 218 "qcom,usb-snps-hs-7nm-phy"; 219 reg = <0x00ff4000 0x114>; 220 status = "disabled"; 221 #phy-cells = <0>; 222 223 clocks = <&rpmhcc RPMH_CXO_CLK>; 224 clock-names = "ref"; 225 226 resets = <&gcc GCC_QUSB2PHY_BCR>; 227 }; 228 229 usb_qmpphy: phy@ff6000 { 230 compatible = "qcom,sdx55-qmp-usb3-uni-phy"; 231 reg = <0x00ff6000 0x1c0>; 232 status = "disabled"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges; 236 237 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 238 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 239 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 240 clock-names = "aux", "cfg_ahb", "ref"; 241 242 resets = <&gcc GCC_USB3PHY_PHY_BCR>, 243 <&gcc GCC_USB3_PHY_BCR>; 244 reset-names = "phy", "common"; 245 246 usb_ssphy: phy@ff6200 { 247 reg = <0x00ff6200 0x170>, 248 <0x00ff6400 0x200>, 249 <0x00ff6800 0x800>; 250 #phy-cells = <0>; 251 #clock-cells = <0>; 252 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 253 clock-names = "pipe0"; 254 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 255 }; 256 }; 257 258 mc_virt: interconnect@1100000 { 259 compatible = "qcom,sdx55-mc-virt"; 260 reg = <0x01100000 0x400000>; 261 #interconnect-cells = <1>; 262 qcom,bcm-voters = <&apps_bcm_voter>; 263 }; 264 265 mem_noc: interconnect@9680000 { 266 compatible = "qcom,sdx55-mem-noc"; 267 reg = <0x09680000 0x40000>; 268 #interconnect-cells = <1>; 269 qcom,bcm-voters = <&apps_bcm_voter>; 270 }; 271 272 system_noc: interconnect@162c000 { 273 compatible = "qcom,sdx55-system-noc"; 274 reg = <0x0162c000 0x31200>; 275 #interconnect-cells = <1>; 276 qcom,bcm-voters = <&apps_bcm_voter>; 277 }; 278 279 qpic_bam: dma-controller@1b04000 { 280 compatible = "qcom,bam-v1.7.0"; 281 reg = <0x01b04000 0x1c000>; 282 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&rpmhcc RPMH_QPIC_CLK>; 284 clock-names = "bam_clk"; 285 #dma-cells = <1>; 286 qcom,ee = <0>; 287 qcom,controlled-remotely; 288 status = "disabled"; 289 }; 290 291 qpic_nand: nand-controller@1b30000 { 292 compatible = "qcom,sdx55-nand"; 293 reg = <0x01b30000 0x10000>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 clocks = <&rpmhcc RPMH_QPIC_CLK>, 297 <&nand_clk_dummy>; 298 clock-names = "core", "aon"; 299 300 dmas = <&qpic_bam 0>, 301 <&qpic_bam 1>, 302 <&qpic_bam 2>; 303 dma-names = "tx", "rx", "cmd"; 304 status = "disabled"; 305 }; 306 307 pcie_rc: pcie@1c00000 { 308 compatible = "qcom,pcie-sdx55"; 309 reg = <0x01c00000 0x3000>, 310 <0x40000000 0xf1d>, 311 <0x40000f20 0xc8>, 312 <0x40001000 0x1000>, 313 <0x40100000 0x100000>; 314 reg-names = "parf", 315 "dbi", 316 "elbi", 317 "atu", 318 "config"; 319 device_type = "pci"; 320 linux,pci-domain = <0>; 321 bus-range = <0x00 0xff>; 322 num-lanes = <1>; 323 324 #address-cells = <3>; 325 #size-cells = <2>; 326 327 ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, 328 <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; 329 330 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 338 interrupt-names = "msi", 339 "msi2", 340 "msi3", 341 "msi4", 342 "msi5", 343 "msi6", 344 "msi7", 345 "msi8"; 346 #interrupt-cells = <1>; 347 interrupt-map-mask = <0 0 0 0x7>; 348 interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 349 <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 350 <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 351 <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 352 353 clocks = <&gcc GCC_PCIE_PIPE_CLK>, 354 <&gcc GCC_PCIE_AUX_CLK>, 355 <&gcc GCC_PCIE_CFG_AHB_CLK>, 356 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 357 <&gcc GCC_PCIE_SLV_AXI_CLK>, 358 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 359 <&gcc GCC_PCIE_SLEEP_CLK>; 360 clock-names = "pipe", 361 "aux", 362 "cfg", 363 "bus_master", 364 "bus_slave", 365 "slave_q2a", 366 "sleep"; 367 368 assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; 369 assigned-clock-rates = <19200000>; 370 371 iommu-map = <0x0 &apps_smmu 0x0200 0x1>, 372 <0x100 &apps_smmu 0x0201 0x1>, 373 <0x200 &apps_smmu 0x0202 0x1>, 374 <0x300 &apps_smmu 0x0203 0x1>, 375 <0x400 &apps_smmu 0x0204 0x1>; 376 377 resets = <&gcc GCC_PCIE_BCR>; 378 reset-names = "pci"; 379 380 power-domains = <&gcc PCIE_GDSC>; 381 382 phys = <&pcie_phy>; 383 phy-names = "pciephy"; 384 385 status = "disabled"; 386 }; 387 388 pcie_ep: pcie-ep@1c00000 { 389 compatible = "qcom,sdx55-pcie-ep"; 390 reg = <0x01c00000 0x3000>, 391 <0x40000000 0xf1d>, 392 <0x40000f20 0xc8>, 393 <0x40001000 0x1000>, 394 <0x40200000 0x100000>, 395 <0x01c03000 0x3000>; 396 reg-names = "parf", 397 "dbi", 398 "elbi", 399 "atu", 400 "addr_space", 401 "mmio"; 402 403 qcom,perst-regs = <&tcsr 0xb258 0xb270>; 404 405 clocks = <&gcc GCC_PCIE_AUX_CLK>, 406 <&gcc GCC_PCIE_CFG_AHB_CLK>, 407 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 408 <&gcc GCC_PCIE_SLV_AXI_CLK>, 409 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 410 <&gcc GCC_PCIE_SLEEP_CLK>, 411 <&gcc GCC_PCIE_0_CLKREF_CLK>; 412 clock-names = "aux", 413 "cfg", 414 "bus_master", 415 "bus_slave", 416 "slave_q2a", 417 "sleep", 418 "ref"; 419 420 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-names = "global", 423 "doorbell"; 424 425 interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; 426 interconnect-names = "pcie-mem"; 427 428 resets = <&gcc GCC_PCIE_BCR>; 429 reset-names = "core"; 430 power-domains = <&gcc PCIE_GDSC>; 431 phys = <&pcie_phy>; 432 phy-names = "pciephy"; 433 max-link-speed = <3>; 434 num-lanes = <2>; 435 436 status = "disabled"; 437 }; 438 439 pcie_phy: phy@1c07000 { 440 compatible = "qcom,sdx55-qmp-pcie-phy"; 441 reg = <0x01c07000 0x2000>; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 ranges; 445 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, 446 <&gcc GCC_PCIE_CFG_AHB_CLK>, 447 <&gcc GCC_PCIE_0_CLKREF_CLK>, 448 <&gcc GCC_PCIE_RCHNG_PHY_CLK>, 449 <&gcc GCC_PCIE_PIPE_CLK>; 450 clock-names = "aux", 451 "cfg_ahb", 452 "ref", 453 "refgen", 454 "pipe"; 455 456 clock-output-names = "pcie_pipe_clk"; 457 #clock-cells = <0>; 458 459 #phy-cells = <0>; 460 461 resets = <&gcc GCC_PCIE_PHY_BCR>; 462 reset-names = "phy"; 463 464 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; 465 assigned-clock-rates = <100000000>; 466 467 status = "disabled"; 468 }; 469 470 ipa: ipa@1e40000 { 471 compatible = "qcom,sdx55-ipa"; 472 473 iommus = <&apps_smmu 0x5e0 0x0>, 474 <&apps_smmu 0x5e2 0x0>; 475 reg = <0x1e40000 0x7000>, 476 <0x1e50000 0x4b20>, 477 <0x1e04000 0x2c000>; 478 reg-names = "ipa-reg", 479 "ipa-shared", 480 "gsi"; 481 482 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 483 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 484 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 485 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 486 interrupt-names = "ipa", 487 "gsi", 488 "ipa-clock-query", 489 "ipa-setup-ready"; 490 491 clocks = <&rpmhcc RPMH_IPA_CLK>; 492 clock-names = "core"; 493 494 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, 495 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, 496 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; 497 interconnect-names = "memory", 498 "imem", 499 "config"; 500 501 qcom,smem-states = <&ipa_smp2p_out 0>, 502 <&ipa_smp2p_out 1>; 503 qcom,smem-state-names = "ipa-clock-enabled-valid", 504 "ipa-clock-enabled"; 505 506 status = "disabled"; 507 }; 508 509 tcsr_mutex: hwlock@1f40000 { 510 compatible = "qcom,tcsr-mutex"; 511 reg = <0x01f40000 0x40000>; 512 #hwlock-cells = <1>; 513 }; 514 515 tcsr: syscon@1fc0000 { 516 compatible = "qcom,sdx55-tcsr", "syscon"; 517 reg = <0x01fc0000 0x1000>; 518 }; 519 520 sdhc_1: mmc@8804000 { 521 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; 522 reg = <0x08804000 0x1000>; 523 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "hc_irq", "pwr_irq"; 526 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 527 <&gcc GCC_SDCC1_APPS_CLK>; 528 clock-names = "iface", "core"; 529 status = "disabled"; 530 }; 531 532 remoteproc_mpss: remoteproc@4080000 { 533 compatible = "qcom,sdx55-mpss-pas"; 534 reg = <0x04080000 0x4040>; 535 536 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 537 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 538 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 539 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 540 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 541 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 542 interrupt-names = "wdog", "fatal", "ready", "handover", 543 "stop-ack", "shutdown-ack"; 544 545 clocks = <&rpmhcc RPMH_CXO_CLK>; 546 clock-names = "xo"; 547 548 power-domains = <&rpmhpd SDX55_CX>, 549 <&rpmhpd SDX55_MSS>; 550 power-domain-names = "cx", "mss"; 551 552 qcom,smem-states = <&modem_smp2p_out 0>; 553 qcom,smem-state-names = "stop"; 554 555 status = "disabled"; 556 557 glink-edge { 558 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 559 label = "mpss"; 560 qcom,remote-pid = <1>; 561 mboxes = <&apcs 15>; 562 }; 563 }; 564 565 usb: usb@a6f8800 { 566 compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; 567 reg = <0x0a6f8800 0x400>; 568 status = "disabled"; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges; 572 573 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 574 <&gcc GCC_USB30_MASTER_CLK>, 575 <&gcc GCC_USB30_MSTR_AXI_CLK>, 576 <&gcc GCC_USB30_SLEEP_CLK>, 577 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 578 clock-names = "cfg_noc", 579 "core", 580 "iface", 581 "sleep", 582 "mock_utmi"; 583 584 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 585 <&gcc GCC_USB30_MASTER_CLK>; 586 assigned-clock-rates = <19200000>, <200000000>; 587 588 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-names = "hs_phy_irq", "ss_phy_irq", 593 "dm_hs_phy_irq", "dp_hs_phy_irq"; 594 595 power-domains = <&gcc USB30_GDSC>; 596 597 resets = <&gcc GCC_USB30_BCR>; 598 599 usb_dwc3: usb@a600000 { 600 compatible = "snps,dwc3"; 601 reg = <0x0a600000 0xcd00>; 602 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 603 iommus = <&apps_smmu 0x1a0 0x0>; 604 snps,dis_u2_susphy_quirk; 605 snps,dis_enblslpm_quirk; 606 phys = <&usb_hsphy>, <&usb_ssphy>; 607 phy-names = "usb2-phy", "usb3-phy"; 608 }; 609 }; 610 611 pdc: interrupt-controller@b210000 { 612 compatible = "qcom,sdx55-pdc", "qcom,pdc"; 613 reg = <0x0b210000 0x30000>; 614 qcom,pdc-ranges = <0 179 52>; 615 #interrupt-cells = <3>; 616 interrupt-parent = <&intc>; 617 interrupt-controller; 618 }; 619 620 restart@c264000 { 621 compatible = "qcom,pshold"; 622 reg = <0x0c264000 0x1000>; 623 }; 624 625 spmi_bus: spmi@c440000 { 626 compatible = "qcom,spmi-pmic-arb"; 627 reg = <0x0c440000 0x0000d00>, 628 <0x0c600000 0x2000000>, 629 <0x0e600000 0x0100000>, 630 <0x0e700000 0x00a0000>, 631 <0x0c40a000 0x0000700>; 632 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 633 interrupt-names = "periph_irq"; 634 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 635 qcom,ee = <0>; 636 qcom,channel = <0>; 637 #address-cells = <2>; 638 #size-cells = <0>; 639 interrupt-controller; 640 #interrupt-cells = <4>; 641 }; 642 643 tlmm: pinctrl@f100000 { 644 compatible = "qcom,sdx55-pinctrl"; 645 reg = <0xf100000 0x300000>; 646 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 647 gpio-controller; 648 #gpio-cells = <2>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 gpio-ranges = <&tlmm 0 0 108>; 652 }; 653 654 sram@1468f000 { 655 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; 656 reg = <0x1468f000 0x1000>; 657 658 #address-cells = <1>; 659 #size-cells = <1>; 660 661 ranges = <0x0 0x1468f000 0x1000>; 662 663 pil-reloc@94c { 664 compatible = "qcom,pil-reloc-info"; 665 reg = <0x94c 0x200>; 666 }; 667 }; 668 669 apps_smmu: iommu@15000000 { 670 compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 671 reg = <0x15000000 0x20000>; 672 #iommu-cells = <2>; 673 #global-interrupts = <1>; 674 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 691 }; 692 693 intc: interrupt-controller@17800000 { 694 compatible = "qcom,msm-qgic2"; 695 interrupt-controller; 696 interrupt-parent = <&intc>; 697 #interrupt-cells = <3>; 698 reg = <0x17800000 0x1000>, 699 <0x17802000 0x1000>; 700 }; 701 702 a7pll: clock@17808000 { 703 compatible = "qcom,sdx55-a7pll"; 704 reg = <0x17808000 0x1000>; 705 clocks = <&rpmhcc RPMH_CXO_CLK>; 706 clock-names = "bi_tcxo"; 707 #clock-cells = <0>; 708 }; 709 710 apcs: mailbox@17810000 { 711 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 712 reg = <0x17810000 0x2000>; 713 #mbox-cells = <1>; 714 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 715 clock-names = "ref", "pll", "aux"; 716 #clock-cells = <0>; 717 }; 718 719 watchdog@17817000 { 720 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; 721 reg = <0x17817000 0x1000>; 722 clocks = <&sleep_clk>; 723 }; 724 725 timer@17820000 { 726 #address-cells = <1>; 727 #size-cells = <1>; 728 ranges; 729 compatible = "arm,armv7-timer-mem"; 730 reg = <0x17820000 0x1000>; 731 clock-frequency = <19200000>; 732 733 frame@17821000 { 734 frame-number = <0>; 735 interrupts = <GIC_SPI 7 0x4>, 736 <GIC_SPI 6 0x4>; 737 reg = <0x17821000 0x1000>, 738 <0x17822000 0x1000>; 739 }; 740 741 frame@17823000 { 742 frame-number = <1>; 743 interrupts = <GIC_SPI 8 0x4>; 744 reg = <0x17823000 0x1000>; 745 status = "disabled"; 746 }; 747 748 frame@17824000 { 749 frame-number = <2>; 750 interrupts = <GIC_SPI 9 0x4>; 751 reg = <0x17824000 0x1000>; 752 status = "disabled"; 753 }; 754 755 frame@17825000 { 756 frame-number = <3>; 757 interrupts = <GIC_SPI 10 0x4>; 758 reg = <0x17825000 0x1000>; 759 status = "disabled"; 760 }; 761 762 frame@17826000 { 763 frame-number = <4>; 764 interrupts = <GIC_SPI 11 0x4>; 765 reg = <0x17826000 0x1000>; 766 status = "disabled"; 767 }; 768 769 frame@17827000 { 770 frame-number = <5>; 771 interrupts = <GIC_SPI 12 0x4>; 772 reg = <0x17827000 0x1000>; 773 status = "disabled"; 774 }; 775 776 frame@17828000 { 777 frame-number = <6>; 778 interrupts = <GIC_SPI 13 0x4>; 779 reg = <0x17828000 0x1000>; 780 status = "disabled"; 781 }; 782 783 frame@17829000 { 784 frame-number = <7>; 785 interrupts = <GIC_SPI 14 0x4>; 786 reg = <0x17829000 0x1000>; 787 status = "disabled"; 788 }; 789 }; 790 791 apps_rsc: rsc@17830000 { 792 compatible = "qcom,rpmh-rsc"; 793 reg = <0x17830000 0x10000>, <0x17840000 0x10000>; 794 reg-names = "drv-0", "drv-1"; 795 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 797 qcom,tcs-offset = <0xd00>; 798 qcom,drv-id = <1>; 799 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>, 800 <WAKE_TCS 2>, <CONTROL_TCS 1>; 801 802 rpmhcc: clock-controller { 803 compatible = "qcom,sdx55-rpmh-clk"; 804 #clock-cells = <1>; 805 clock-names = "xo"; 806 clocks = <&xo_board>; 807 }; 808 809 rpmhpd: power-controller { 810 compatible = "qcom,sdx55-rpmhpd"; 811 #power-domain-cells = <1>; 812 operating-points-v2 = <&rpmhpd_opp_table>; 813 814 rpmhpd_opp_table: opp-table { 815 compatible = "operating-points-v2"; 816 817 rpmhpd_opp_ret: opp1 { 818 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 819 }; 820 821 rpmhpd_opp_min_svs: opp2 { 822 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 823 }; 824 825 rpmhpd_opp_low_svs: opp3 { 826 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 827 }; 828 829 rpmhpd_opp_svs: opp4 { 830 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 831 }; 832 833 rpmhpd_opp_svs_l1: opp5 { 834 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 835 }; 836 837 rpmhpd_opp_nom: opp6 { 838 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 839 }; 840 841 rpmhpd_opp_nom_l1: opp7 { 842 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 843 }; 844 845 rpmhpd_opp_nom_l2: opp8 { 846 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 847 }; 848 849 rpmhpd_opp_turbo: opp9 { 850 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 851 }; 852 853 rpmhpd_opp_turbo_l1: opp10 { 854 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 855 }; 856 }; 857 }; 858 859 apps_bcm_voter: bcm-voter { 860 compatible = "qcom,bcm-voter"; 861 }; 862 }; 863 }; 864 865 timer { 866 compatible = "arm,armv7-timer"; 867 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 868 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 869 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 870 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 871 clock-frequency = <19200000>; 872 }; 873}; 874