1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interconnect/qcom,msm8974.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8974.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/reset/qcom,gcc-msm8974.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 interrupt-parent = <&intc>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo_board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 }; 25 26 sleep_clk: sleep_clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 37 38 CPU0: cpu@0 { 39 compatible = "qcom,krait"; 40 enable-method = "qcom,kpss-acc-v2"; 41 device_type = "cpu"; 42 reg = <0>; 43 next-level-cache = <&L2>; 44 qcom,acc = <&acc0>; 45 qcom,saw = <&saw0>; 46 cpu-idle-states = <&CPU_SPC>; 47 }; 48 49 CPU1: cpu@1 { 50 compatible = "qcom,krait"; 51 enable-method = "qcom,kpss-acc-v2"; 52 device_type = "cpu"; 53 reg = <1>; 54 next-level-cache = <&L2>; 55 qcom,acc = <&acc1>; 56 qcom,saw = <&saw1>; 57 cpu-idle-states = <&CPU_SPC>; 58 }; 59 60 CPU2: cpu@2 { 61 compatible = "qcom,krait"; 62 enable-method = "qcom,kpss-acc-v2"; 63 device_type = "cpu"; 64 reg = <2>; 65 next-level-cache = <&L2>; 66 qcom,acc = <&acc2>; 67 qcom,saw = <&saw2>; 68 cpu-idle-states = <&CPU_SPC>; 69 }; 70 71 CPU3: cpu@3 { 72 compatible = "qcom,krait"; 73 enable-method = "qcom,kpss-acc-v2"; 74 device_type = "cpu"; 75 reg = <3>; 76 next-level-cache = <&L2>; 77 qcom,acc = <&acc3>; 78 qcom,saw = <&saw3>; 79 cpu-idle-states = <&CPU_SPC>; 80 }; 81 82 L2: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 qcom,saw = <&saw_l2>; 87 }; 88 89 idle-states { 90 CPU_SPC: cpu-spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <150>; 94 exit-latency-us = <200>; 95 min-residency-us = <2000>; 96 }; 97 }; 98 }; 99 100 firmware { 101 scm { 102 compatible = "qcom,scm-msm8974", "qcom,scm"; 103 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 104 clock-names = "core", "bus", "iface"; 105 }; 106 }; 107 108 memory@0 { 109 device_type = "memory"; 110 reg = <0x0 0x0>; 111 }; 112 113 pmu { 114 compatible = "qcom,krait-pmu"; 115 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 }; 117 118 rpm: remoteproc { 119 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; 120 121 master-stats { 122 compatible = "qcom,rpm-master-stats"; 123 qcom,rpm-msg-ram = <&apss_master_stats>, 124 <&mpss_master_stats>, 125 <&lpss_master_stats>, 126 <&pronto_master_stats>; 127 qcom,master-names = "APSS", 128 "MPSS", 129 "LPSS", 130 "PRONTO"; 131 }; 132 133 smd-edge { 134 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 135 mboxes = <&apcs 0>; 136 qcom,smd-edge = <15>; 137 138 rpm_requests: rpm-requests { 139 compatible = "qcom,rpm-msm8974"; 140 qcom,smd-channels = "rpm_requests"; 141 142 rpmcc: clock-controller { 143 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 144 #clock-cells = <1>; 145 clocks = <&xo_board>; 146 clock-names = "xo"; 147 }; 148 }; 149 }; 150 }; 151 152 reserved-memory { 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges; 156 157 mpss_region: mpss@8000000 { 158 reg = <0x08000000 0x5100000>; 159 no-map; 160 }; 161 162 mba_region: mba@d100000 { 163 reg = <0x0d100000 0x100000>; 164 no-map; 165 }; 166 167 wcnss_region: wcnss@d200000 { 168 reg = <0x0d200000 0xa00000>; 169 no-map; 170 }; 171 172 adsp_region: adsp@dc00000 { 173 reg = <0x0dc00000 0x1900000>; 174 no-map; 175 }; 176 177 venus_region: memory@f500000 { 178 reg = <0x0f500000 0x500000>; 179 no-map; 180 }; 181 182 smem_region: smem@fa00000 { 183 reg = <0xfa00000 0x200000>; 184 no-map; 185 }; 186 187 tz_region: memory@fc00000 { 188 reg = <0x0fc00000 0x160000>; 189 no-map; 190 }; 191 192 rfsa_mem: memory@fd60000 { 193 reg = <0x0fd60000 0x20000>; 194 no-map; 195 }; 196 197 rmtfs@fd80000 { 198 compatible = "qcom,rmtfs-mem"; 199 reg = <0x0fd80000 0x180000>; 200 no-map; 201 202 qcom,client-id = <1>; 203 }; 204 }; 205 206 smem { 207 compatible = "qcom,smem"; 208 209 memory-region = <&smem_region>; 210 qcom,rpm-msg-ram = <&rpm_msg_ram>; 211 212 hwlocks = <&tcsr_mutex 3>; 213 }; 214 215 smp2p-adsp { 216 compatible = "qcom,smp2p"; 217 qcom,smem = <443>, <429>; 218 219 interrupt-parent = <&intc>; 220 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 221 222 mboxes = <&apcs 10>; 223 224 qcom,local-pid = <0>; 225 qcom,remote-pid = <2>; 226 227 adsp_smp2p_out: master-kernel { 228 qcom,entry-name = "master-kernel"; 229 #qcom,smem-state-cells = <1>; 230 }; 231 232 adsp_smp2p_in: slave-kernel { 233 qcom,entry-name = "slave-kernel"; 234 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 }; 238 }; 239 240 smp2p-modem { 241 compatible = "qcom,smp2p"; 242 qcom,smem = <435>, <428>; 243 244 interrupt-parent = <&intc>; 245 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 246 247 mboxes = <&apcs 14>; 248 249 qcom,local-pid = <0>; 250 qcom,remote-pid = <1>; 251 252 modem_smp2p_out: master-kernel { 253 qcom,entry-name = "master-kernel"; 254 #qcom,smem-state-cells = <1>; 255 }; 256 257 modem_smp2p_in: slave-kernel { 258 qcom,entry-name = "slave-kernel"; 259 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 }; 263 }; 264 265 smp2p-wcnss { 266 compatible = "qcom,smp2p"; 267 qcom,smem = <451>, <431>; 268 269 interrupt-parent = <&intc>; 270 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 271 272 mboxes = <&apcs 18>; 273 274 qcom,local-pid = <0>; 275 qcom,remote-pid = <4>; 276 277 wcnss_smp2p_out: master-kernel { 278 qcom,entry-name = "master-kernel"; 279 280 #qcom,smem-state-cells = <1>; 281 }; 282 283 wcnss_smp2p_in: slave-kernel { 284 qcom,entry-name = "slave-kernel"; 285 286 interrupt-controller; 287 #interrupt-cells = <2>; 288 }; 289 }; 290 291 smsm { 292 compatible = "qcom,smsm"; 293 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 qcom,ipc-1 = <&apcs 8 13>; 298 qcom,ipc-2 = <&apcs 8 9>; 299 qcom,ipc-3 = <&apcs 8 19>; 300 301 apps_smsm: apps@0 { 302 reg = <0>; 303 304 #qcom,smem-state-cells = <1>; 305 }; 306 307 modem_smsm: modem@1 { 308 reg = <1>; 309 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 310 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 }; 314 315 adsp_smsm: adsp@2 { 316 reg = <2>; 317 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 318 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 }; 322 323 wcnss_smsm: wcnss@7 { 324 reg = <7>; 325 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 326 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 }; 330 }; 331 332 soc: soc { 333 #address-cells = <1>; 334 #size-cells = <1>; 335 ranges; 336 compatible = "simple-bus"; 337 338 intc: interrupt-controller@f9000000 { 339 compatible = "qcom,msm-qgic2"; 340 interrupt-controller; 341 #interrupt-cells = <3>; 342 reg = <0xf9000000 0x1000>, 343 <0xf9002000 0x1000>; 344 }; 345 346 apcs: mailbox@f9011000 { 347 compatible = "qcom,msm8974-apcs-kpss-global", 348 "qcom,msm8994-apcs-kpss-global", "syscon"; 349 reg = <0xf9011000 0x1000>; 350 #mbox-cells = <1>; 351 }; 352 353 saw_l2: power-manager@f9012000 { 354 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; 355 reg = <0xf9012000 0x1000>; 356 }; 357 358 watchdog@f9017000 { 359 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt"; 360 reg = <0xf9017000 0x1000>; 361 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 362 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 363 clocks = <&sleep_clk>; 364 }; 365 366 timer@f9020000 { 367 #address-cells = <1>; 368 #size-cells = <1>; 369 ranges; 370 compatible = "arm,armv7-timer-mem"; 371 reg = <0xf9020000 0x1000>; 372 clock-frequency = <19200000>; 373 374 frame@f9021000 { 375 frame-number = <0>; 376 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 378 reg = <0xf9021000 0x1000>, 379 <0xf9022000 0x1000>; 380 }; 381 382 frame@f9023000 { 383 frame-number = <1>; 384 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 385 reg = <0xf9023000 0x1000>; 386 status = "disabled"; 387 }; 388 389 frame@f9024000 { 390 frame-number = <2>; 391 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 392 reg = <0xf9024000 0x1000>; 393 status = "disabled"; 394 }; 395 396 frame@f9025000 { 397 frame-number = <3>; 398 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 399 reg = <0xf9025000 0x1000>; 400 status = "disabled"; 401 }; 402 403 frame@f9026000 { 404 frame-number = <4>; 405 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 406 reg = <0xf9026000 0x1000>; 407 status = "disabled"; 408 }; 409 410 frame@f9027000 { 411 frame-number = <5>; 412 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 413 reg = <0xf9027000 0x1000>; 414 status = "disabled"; 415 }; 416 417 frame@f9028000 { 418 frame-number = <6>; 419 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 420 reg = <0xf9028000 0x1000>; 421 status = "disabled"; 422 }; 423 }; 424 425 acc0: power-manager@f9088000 { 426 compatible = "qcom,kpss-acc-v2"; 427 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 428 }; 429 430 saw0: power-manager@f9089000 { 431 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 432 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 433 }; 434 435 acc1: power-manager@f9098000 { 436 compatible = "qcom,kpss-acc-v2"; 437 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 438 }; 439 440 saw1: power-manager@f9099000 { 441 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 442 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 443 }; 444 445 acc2: power-manager@f90a8000 { 446 compatible = "qcom,kpss-acc-v2"; 447 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 448 }; 449 450 saw2: power-manager@f90a9000 { 451 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 452 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 453 }; 454 455 acc3: power-manager@f90b8000 { 456 compatible = "qcom,kpss-acc-v2"; 457 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 458 }; 459 460 saw3: power-manager@f90b9000 { 461 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 462 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 463 }; 464 465 sdhc_1: mmc@f9824900 { 466 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 467 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 468 reg-names = "hc", "core"; 469 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 471 interrupt-names = "hc_irq", "pwr_irq"; 472 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 473 <&gcc GCC_SDCC1_APPS_CLK>, 474 <&xo_board>; 475 clock-names = "iface", "core", "xo"; 476 bus-width = <8>; 477 non-removable; 478 479 status = "disabled"; 480 }; 481 482 sdhc_3: mmc@f9864900 { 483 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 484 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 485 reg-names = "hc", "core"; 486 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 488 interrupt-names = "hc_irq", "pwr_irq"; 489 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 490 <&gcc GCC_SDCC3_APPS_CLK>, 491 <&xo_board>; 492 clock-names = "iface", "core", "xo"; 493 bus-width = <4>; 494 495 #address-cells = <1>; 496 #size-cells = <0>; 497 498 status = "disabled"; 499 }; 500 501 sdhc_2: mmc@f98a4900 { 502 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 503 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 504 reg-names = "hc", "core"; 505 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 507 interrupt-names = "hc_irq", "pwr_irq"; 508 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 509 <&gcc GCC_SDCC2_APPS_CLK>, 510 <&xo_board>; 511 clock-names = "iface", "core", "xo"; 512 bus-width = <4>; 513 514 #address-cells = <1>; 515 #size-cells = <0>; 516 517 status = "disabled"; 518 }; 519 520 blsp1_uart1: serial@f991d000 { 521 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 522 reg = <0xf991d000 0x1000>; 523 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 525 clock-names = "core", "iface"; 526 status = "disabled"; 527 }; 528 529 blsp1_uart2: serial@f991e000 { 530 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 531 reg = <0xf991e000 0x1000>; 532 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 534 clock-names = "core", "iface"; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&blsp1_uart2_default>; 537 status = "disabled"; 538 }; 539 540 blsp1_i2c1: i2c@f9923000 { 541 status = "disabled"; 542 compatible = "qcom,i2c-qup-v2.1.1"; 543 reg = <0xf9923000 0x1000>; 544 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 546 clock-names = "core", "iface"; 547 pinctrl-names = "default", "sleep"; 548 pinctrl-0 = <&blsp1_i2c1_default>; 549 pinctrl-1 = <&blsp1_i2c1_sleep>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 }; 553 554 blsp1_i2c2: i2c@f9924000 { 555 status = "disabled"; 556 compatible = "qcom,i2c-qup-v2.1.1"; 557 reg = <0xf9924000 0x1000>; 558 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 560 clock-names = "core", "iface"; 561 pinctrl-names = "default", "sleep"; 562 pinctrl-0 = <&blsp1_i2c2_default>; 563 pinctrl-1 = <&blsp1_i2c2_sleep>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 }; 567 568 blsp1_i2c3: i2c@f9925000 { 569 status = "disabled"; 570 compatible = "qcom,i2c-qup-v2.1.1"; 571 reg = <0xf9925000 0x1000>; 572 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 574 clock-names = "core", "iface"; 575 pinctrl-names = "default", "sleep"; 576 pinctrl-0 = <&blsp1_i2c3_default>; 577 pinctrl-1 = <&blsp1_i2c3_sleep>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 }; 581 582 blsp1_i2c6: i2c@f9928000 { 583 status = "disabled"; 584 compatible = "qcom,i2c-qup-v2.1.1"; 585 reg = <0xf9928000 0x1000>; 586 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 588 clock-names = "core", "iface"; 589 pinctrl-names = "default", "sleep"; 590 pinctrl-0 = <&blsp1_i2c6_default>; 591 pinctrl-1 = <&blsp1_i2c6_sleep>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 }; 595 596 blsp2_dma: dma-controller@f9944000 { 597 compatible = "qcom,bam-v1.4.0"; 598 reg = <0xf9944000 0x19000>; 599 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 601 clock-names = "bam_clk"; 602 #dma-cells = <1>; 603 qcom,ee = <0>; 604 }; 605 606 blsp2_uart1: serial@f995d000 { 607 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 608 reg = <0xf995d000 0x1000>; 609 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 611 clock-names = "core", "iface"; 612 pinctrl-names = "default", "sleep"; 613 pinctrl-0 = <&blsp2_uart1_default>; 614 pinctrl-1 = <&blsp2_uart1_sleep>; 615 status = "disabled"; 616 }; 617 618 blsp2_uart2: serial@f995e000 { 619 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 620 reg = <0xf995e000 0x1000>; 621 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 623 clock-names = "core", "iface"; 624 status = "disabled"; 625 }; 626 627 blsp2_uart4: serial@f9960000 { 628 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 629 reg = <0xf9960000 0x1000>; 630 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 632 clock-names = "core", "iface"; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&blsp2_uart4_default>; 635 status = "disabled"; 636 }; 637 638 blsp2_i2c2: i2c@f9964000 { 639 status = "disabled"; 640 compatible = "qcom,i2c-qup-v2.1.1"; 641 reg = <0xf9964000 0x1000>; 642 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 644 clock-names = "core", "iface"; 645 pinctrl-names = "default", "sleep"; 646 pinctrl-0 = <&blsp2_i2c2_default>; 647 pinctrl-1 = <&blsp2_i2c2_sleep>; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 }; 651 652 blsp2_i2c5: i2c@f9967000 { 653 status = "disabled"; 654 compatible = "qcom,i2c-qup-v2.1.1"; 655 reg = <0xf9967000 0x1000>; 656 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 658 clock-names = "core", "iface"; 659 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 660 dma-names = "tx", "rx"; 661 pinctrl-names = "default", "sleep"; 662 pinctrl-0 = <&blsp2_i2c5_default>; 663 pinctrl-1 = <&blsp2_i2c5_sleep>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 }; 667 668 blsp2_i2c6: i2c@f9968000 { 669 status = "disabled"; 670 compatible = "qcom,i2c-qup-v2.1.1"; 671 reg = <0xf9968000 0x1000>; 672 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 674 clock-names = "core", "iface"; 675 pinctrl-names = "default", "sleep"; 676 pinctrl-0 = <&blsp2_i2c6_default>; 677 pinctrl-1 = <&blsp2_i2c6_sleep>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 }; 681 682 usb: usb@f9a55000 { 683 compatible = "qcom,ci-hdrc"; 684 reg = <0xf9a55000 0x200>, 685 <0xf9a55200 0x200>; 686 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 688 <&gcc GCC_USB_HS_SYSTEM_CLK>; 689 clock-names = "iface", "core"; 690 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 691 assigned-clock-rates = <75000000>; 692 resets = <&gcc GCC_USB_HS_BCR>; 693 reset-names = "core"; 694 phy_type = "ulpi"; 695 dr_mode = "otg"; 696 ahb-burst-config = <0>; 697 phy-names = "usb-phy"; 698 status = "disabled"; 699 #reset-cells = <1>; 700 701 ulpi { 702 usb_hs1_phy: phy-0 { 703 compatible = "qcom,usb-hs-phy-msm8974", 704 "qcom,usb-hs-phy"; 705 #phy-cells = <0>; 706 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 707 clock-names = "ref", "sleep"; 708 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 709 reset-names = "phy", "por"; 710 status = "disabled"; 711 }; 712 713 usb_hs2_phy: phy-1 { 714 compatible = "qcom,usb-hs-phy-msm8974", 715 "qcom,usb-hs-phy"; 716 #phy-cells = <0>; 717 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 718 clock-names = "ref", "sleep"; 719 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; 720 reset-names = "phy", "por"; 721 status = "disabled"; 722 }; 723 }; 724 }; 725 726 rng@f9bff000 { 727 compatible = "qcom,prng"; 728 reg = <0xf9bff000 0x200>; 729 clocks = <&gcc GCC_PRNG_AHB_CLK>; 730 clock-names = "core"; 731 }; 732 733 pronto: remoteproc@fb204000 { 734 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 735 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 736 reg-names = "ccu", "dxe", "pmu"; 737 738 memory-region = <&wcnss_region>; 739 740 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 741 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 742 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 743 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 744 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 745 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 746 747 qcom,smem-states = <&wcnss_smp2p_out 0>; 748 qcom,smem-state-names = "stop"; 749 750 status = "disabled"; 751 752 iris { 753 compatible = "qcom,wcn3680"; 754 755 clocks = <&rpmcc RPM_SMD_CXO_A2>; 756 clock-names = "xo"; 757 }; 758 759 smd-edge { 760 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 761 762 mboxes = <&apcs 17>; 763 qcom,smd-edge = <6>; 764 765 wcnss { 766 compatible = "qcom,wcnss"; 767 qcom,smd-channels = "WCNSS_CTRL"; 768 status = "disabled"; 769 770 qcom,mmio = <&pronto>; 771 772 bluetooth { 773 compatible = "qcom,wcnss-bt"; 774 }; 775 776 wifi { 777 compatible = "qcom,wcnss-wlan"; 778 779 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 780 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 781 interrupt-names = "tx", "rx"; 782 783 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 784 qcom,smem-state-names = "tx-enable", 785 "tx-rings-empty"; 786 }; 787 }; 788 }; 789 }; 790 791 sram@fc190000 { 792 compatible = "qcom,msm8974-rpm-stats"; 793 reg = <0xfc190000 0x10000>; 794 }; 795 796 etf@fc307000 { 797 compatible = "arm,coresight-tmc", "arm,primecell"; 798 reg = <0xfc307000 0x1000>; 799 800 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 801 clock-names = "apb_pclk", "atclk"; 802 803 out-ports { 804 port { 805 etf_out: endpoint { 806 remote-endpoint = <&replicator_in>; 807 }; 808 }; 809 }; 810 811 in-ports { 812 port { 813 etf_in: endpoint { 814 remote-endpoint = <&merger_out>; 815 }; 816 }; 817 }; 818 }; 819 820 tpiu@fc318000 { 821 compatible = "arm,coresight-tpiu", "arm,primecell"; 822 reg = <0xfc318000 0x1000>; 823 824 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 825 clock-names = "apb_pclk", "atclk"; 826 827 in-ports { 828 port { 829 tpiu_in: endpoint { 830 remote-endpoint = <&replicator_out1>; 831 }; 832 }; 833 }; 834 }; 835 836 funnel@fc31a000 { 837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 838 reg = <0xfc31a000 0x1000>; 839 840 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 841 clock-names = "apb_pclk", "atclk"; 842 843 in-ports { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 847 /* 848 * Not described input ports: 849 * 0 - not-connected 850 * 1 - connected trought funnel to Multimedia CPU 851 * 2 - connected to Wireless CPU 852 * 3 - not-connected 853 * 4 - not-connected 854 * 6 - not-connected 855 * 7 - connected to STM 856 */ 857 port@5 { 858 reg = <5>; 859 funnel1_in5: endpoint { 860 remote-endpoint = <&kpss_out>; 861 }; 862 }; 863 }; 864 865 out-ports { 866 port { 867 funnel1_out: endpoint { 868 remote-endpoint = <&merger_in1>; 869 }; 870 }; 871 }; 872 }; 873 874 funnel@fc31b000 { 875 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 876 reg = <0xfc31b000 0x1000>; 877 878 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 879 clock-names = "apb_pclk", "atclk"; 880 881 in-ports { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 885 /* 886 * Not described input ports: 887 * 0 - connected trought funnel to Audio, Modem and 888 * Resource and Power Manager CPU's 889 * 2...7 - not-connected 890 */ 891 port@1 { 892 reg = <1>; 893 merger_in1: endpoint { 894 remote-endpoint = <&funnel1_out>; 895 }; 896 }; 897 }; 898 899 out-ports { 900 port { 901 merger_out: endpoint { 902 remote-endpoint = <&etf_in>; 903 }; 904 }; 905 }; 906 }; 907 908 replicator@fc31c000 { 909 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 910 reg = <0xfc31c000 0x1000>; 911 912 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 913 clock-names = "apb_pclk", "atclk"; 914 915 out-ports { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 919 port@0 { 920 reg = <0>; 921 replicator_out0: endpoint { 922 remote-endpoint = <&etr_in>; 923 }; 924 }; 925 port@1 { 926 reg = <1>; 927 replicator_out1: endpoint { 928 remote-endpoint = <&tpiu_in>; 929 }; 930 }; 931 }; 932 933 in-ports { 934 port { 935 replicator_in: endpoint { 936 remote-endpoint = <&etf_out>; 937 }; 938 }; 939 }; 940 }; 941 942 etr@fc322000 { 943 compatible = "arm,coresight-tmc", "arm,primecell"; 944 reg = <0xfc322000 0x1000>; 945 946 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 947 clock-names = "apb_pclk", "atclk"; 948 949 in-ports { 950 port { 951 etr_in: endpoint { 952 remote-endpoint = <&replicator_out0>; 953 }; 954 }; 955 }; 956 }; 957 958 etm@fc33c000 { 959 compatible = "arm,coresight-etm4x", "arm,primecell"; 960 reg = <0xfc33c000 0x1000>; 961 962 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 963 clock-names = "apb_pclk", "atclk"; 964 965 cpu = <&CPU0>; 966 967 out-ports { 968 port { 969 etm0_out: endpoint { 970 remote-endpoint = <&kpss_in0>; 971 }; 972 }; 973 }; 974 }; 975 976 etm@fc33d000 { 977 compatible = "arm,coresight-etm4x", "arm,primecell"; 978 reg = <0xfc33d000 0x1000>; 979 980 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 981 clock-names = "apb_pclk", "atclk"; 982 983 cpu = <&CPU1>; 984 985 out-ports { 986 port { 987 etm1_out: endpoint { 988 remote-endpoint = <&kpss_in1>; 989 }; 990 }; 991 }; 992 }; 993 994 etm@fc33e000 { 995 compatible = "arm,coresight-etm4x", "arm,primecell"; 996 reg = <0xfc33e000 0x1000>; 997 998 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 999 clock-names = "apb_pclk", "atclk"; 1000 1001 cpu = <&CPU2>; 1002 1003 out-ports { 1004 port { 1005 etm2_out: endpoint { 1006 remote-endpoint = <&kpss_in2>; 1007 }; 1008 }; 1009 }; 1010 }; 1011 1012 etm@fc33f000 { 1013 compatible = "arm,coresight-etm4x", "arm,primecell"; 1014 reg = <0xfc33f000 0x1000>; 1015 1016 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1017 clock-names = "apb_pclk", "atclk"; 1018 1019 cpu = <&CPU3>; 1020 1021 out-ports { 1022 port { 1023 etm3_out: endpoint { 1024 remote-endpoint = <&kpss_in3>; 1025 }; 1026 }; 1027 }; 1028 }; 1029 1030 /* KPSS funnel, only 4 inputs are used */ 1031 funnel@fc345000 { 1032 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1033 reg = <0xfc345000 0x1000>; 1034 1035 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1036 clock-names = "apb_pclk", "atclk"; 1037 1038 in-ports { 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 1042 port@0 { 1043 reg = <0>; 1044 kpss_in0: endpoint { 1045 remote-endpoint = <&etm0_out>; 1046 }; 1047 }; 1048 port@1 { 1049 reg = <1>; 1050 kpss_in1: endpoint { 1051 remote-endpoint = <&etm1_out>; 1052 }; 1053 }; 1054 port@2 { 1055 reg = <2>; 1056 kpss_in2: endpoint { 1057 remote-endpoint = <&etm2_out>; 1058 }; 1059 }; 1060 port@3 { 1061 reg = <3>; 1062 kpss_in3: endpoint { 1063 remote-endpoint = <&etm3_out>; 1064 }; 1065 }; 1066 }; 1067 1068 out-ports { 1069 port { 1070 kpss_out: endpoint { 1071 remote-endpoint = <&funnel1_in5>; 1072 }; 1073 }; 1074 }; 1075 }; 1076 1077 bimc: interconnect@fc380000 { 1078 reg = <0xfc380000 0x6a000>; 1079 compatible = "qcom,msm8974-bimc"; 1080 #interconnect-cells = <1>; 1081 clock-names = "bus", "bus_a"; 1082 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1083 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1084 }; 1085 1086 gcc: clock-controller@fc400000 { 1087 compatible = "qcom,gcc-msm8974"; 1088 #clock-cells = <1>; 1089 #reset-cells = <1>; 1090 #power-domain-cells = <1>; 1091 reg = <0xfc400000 0x4000>; 1092 1093 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1094 <&sleep_clk>; 1095 clock-names = "xo", 1096 "sleep_clk"; 1097 }; 1098 1099 rpm_msg_ram: sram@fc428000 { 1100 compatible = "qcom,rpm-msg-ram"; 1101 reg = <0xfc428000 0x4000>; 1102 1103 #address-cells = <1>; 1104 #size-cells = <1>; 1105 ranges = <0 0xfc428000 0x4000>; 1106 1107 apss_master_stats: sram@150 { 1108 reg = <0x150 0x14>; 1109 }; 1110 1111 mpss_master_stats: sram@b50 { 1112 reg = <0xb50 0x14>; 1113 }; 1114 1115 lpss_master_stats: sram@1550 { 1116 reg = <0x1550 0x14>; 1117 }; 1118 1119 pronto_master_stats: sram@1f50 { 1120 reg = <0x1f50 0x14>; 1121 }; 1122 }; 1123 1124 snoc: interconnect@fc460000 { 1125 reg = <0xfc460000 0x4000>; 1126 compatible = "qcom,msm8974-snoc"; 1127 #interconnect-cells = <1>; 1128 clock-names = "bus", "bus_a"; 1129 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1130 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1131 }; 1132 1133 pnoc: interconnect@fc468000 { 1134 reg = <0xfc468000 0x4000>; 1135 compatible = "qcom,msm8974-pnoc"; 1136 #interconnect-cells = <1>; 1137 clock-names = "bus", "bus_a"; 1138 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1139 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1140 }; 1141 1142 ocmemnoc: interconnect@fc470000 { 1143 reg = <0xfc470000 0x4000>; 1144 compatible = "qcom,msm8974-ocmemnoc"; 1145 #interconnect-cells = <1>; 1146 clock-names = "bus", "bus_a"; 1147 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1148 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1149 }; 1150 1151 mmssnoc: interconnect@fc478000 { 1152 reg = <0xfc478000 0x4000>; 1153 compatible = "qcom,msm8974-mmssnoc"; 1154 #interconnect-cells = <1>; 1155 clock-names = "bus", "bus_a"; 1156 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1157 <&mmcc MMSS_S0_AXI_CLK>; 1158 }; 1159 1160 cnoc: interconnect@fc480000 { 1161 reg = <0xfc480000 0x4000>; 1162 compatible = "qcom,msm8974-cnoc"; 1163 #interconnect-cells = <1>; 1164 clock-names = "bus", "bus_a"; 1165 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1166 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1167 }; 1168 1169 tsens: thermal-sensor@fc4a9000 { 1170 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 1171 reg = <0xfc4a9000 0x1000>, /* TM */ 1172 <0xfc4a8000 0x1000>; /* SROT */ 1173 nvmem-cells = <&tsens_mode>, 1174 <&tsens_base1>, <&tsens_base2>, 1175 <&tsens_use_backup>, 1176 <&tsens_mode_backup>, 1177 <&tsens_base1_backup>, <&tsens_base2_backup>, 1178 <&tsens_s0_p1>, <&tsens_s0_p2>, 1179 <&tsens_s1_p1>, <&tsens_s1_p2>, 1180 <&tsens_s2_p1>, <&tsens_s2_p2>, 1181 <&tsens_s3_p1>, <&tsens_s3_p2>, 1182 <&tsens_s4_p1>, <&tsens_s4_p2>, 1183 <&tsens_s5_p1>, <&tsens_s5_p2>, 1184 <&tsens_s6_p1>, <&tsens_s6_p2>, 1185 <&tsens_s7_p1>, <&tsens_s7_p2>, 1186 <&tsens_s8_p1>, <&tsens_s8_p2>, 1187 <&tsens_s9_p1>, <&tsens_s9_p2>, 1188 <&tsens_s10_p1>, <&tsens_s10_p2>, 1189 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 1190 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 1191 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 1192 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 1193 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 1194 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 1195 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 1196 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 1197 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 1198 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 1199 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 1200 nvmem-cell-names = "mode", 1201 "base1", "base2", 1202 "use_backup", 1203 "mode_backup", 1204 "base1_backup", "base2_backup", 1205 "s0_p1", "s0_p2", 1206 "s1_p1", "s1_p2", 1207 "s2_p1", "s2_p2", 1208 "s3_p1", "s3_p2", 1209 "s4_p1", "s4_p2", 1210 "s5_p1", "s5_p2", 1211 "s6_p1", "s6_p2", 1212 "s7_p1", "s7_p2", 1213 "s8_p1", "s8_p2", 1214 "s9_p1", "s9_p2", 1215 "s10_p1", "s10_p2", 1216 "s0_p1_backup", "s0_p2_backup", 1217 "s1_p1_backup", "s1_p2_backup", 1218 "s2_p1_backup", "s2_p2_backup", 1219 "s3_p1_backup", "s3_p2_backup", 1220 "s4_p1_backup", "s4_p2_backup", 1221 "s5_p1_backup", "s5_p2_backup", 1222 "s6_p1_backup", "s6_p2_backup", 1223 "s7_p1_backup", "s7_p2_backup", 1224 "s8_p1_backup", "s8_p2_backup", 1225 "s9_p1_backup", "s9_p2_backup", 1226 "s10_p1_backup", "s10_p2_backup"; 1227 #qcom,sensors = <11>; 1228 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1229 interrupt-names = "uplow"; 1230 #thermal-sensor-cells = <1>; 1231 }; 1232 1233 restart@fc4ab000 { 1234 compatible = "qcom,pshold"; 1235 reg = <0xfc4ab000 0x4>; 1236 }; 1237 1238 qfprom: efuse@fc4bc000 { 1239 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1240 reg = <0xfc4bc000 0x2100>; 1241 #address-cells = <1>; 1242 #size-cells = <1>; 1243 1244 tsens_base1: base1@d0 { 1245 reg = <0xd0 0x1>; 1246 bits = <0 8>; 1247 }; 1248 1249 tsens_s0_p1: s0-p1@d1 { 1250 reg = <0xd1 0x1>; 1251 bits = <0 6>; 1252 }; 1253 1254 tsens_s1_p1: s1-p1@d2 { 1255 reg = <0xd1 0x2>; 1256 bits = <6 6>; 1257 }; 1258 1259 tsens_s2_p1: s2-p1@d2 { 1260 reg = <0xd2 0x2>; 1261 bits = <4 6>; 1262 }; 1263 1264 tsens_s3_p1: s3-p1@d3 { 1265 reg = <0xd3 0x1>; 1266 bits = <2 6>; 1267 }; 1268 1269 tsens_s4_p1: s4-p1@d4 { 1270 reg = <0xd4 0x1>; 1271 bits = <0 6>; 1272 }; 1273 1274 tsens_s5_p1: s5-p1@d4 { 1275 reg = <0xd4 0x2>; 1276 bits = <6 6>; 1277 }; 1278 1279 tsens_s6_p1: s6-p1@d5 { 1280 reg = <0xd5 0x2>; 1281 bits = <4 6>; 1282 }; 1283 1284 tsens_s7_p1: s7-p1@d6 { 1285 reg = <0xd6 0x1>; 1286 bits = <2 6>; 1287 }; 1288 1289 tsens_s8_p1: s8-p1@d7 { 1290 reg = <0xd7 0x1>; 1291 bits = <0 6>; 1292 }; 1293 1294 tsens_mode: mode@d7 { 1295 reg = <0xd7 0x1>; 1296 bits = <6 2>; 1297 }; 1298 1299 tsens_s9_p1: s9-p1@d8 { 1300 reg = <0xd8 0x1>; 1301 bits = <0 6>; 1302 }; 1303 1304 tsens_s10_p1: s10_p1@d8 { 1305 reg = <0xd8 0x2>; 1306 bits = <6 6>; 1307 }; 1308 1309 tsens_base2: base2@d9 { 1310 reg = <0xd9 0x2>; 1311 bits = <4 8>; 1312 }; 1313 1314 tsens_s0_p2: s0-p2@da { 1315 reg = <0xda 0x2>; 1316 bits = <4 6>; 1317 }; 1318 1319 tsens_s1_p2: s1-p2@db { 1320 reg = <0xdb 0x1>; 1321 bits = <2 6>; 1322 }; 1323 1324 tsens_s2_p2: s2-p2@dc { 1325 reg = <0xdc 0x1>; 1326 bits = <0 6>; 1327 }; 1328 1329 tsens_s3_p2: s3-p2@dc { 1330 reg = <0xdc 0x2>; 1331 bits = <6 6>; 1332 }; 1333 1334 tsens_s4_p2: s4-p2@dd { 1335 reg = <0xdd 0x2>; 1336 bits = <4 6>; 1337 }; 1338 1339 tsens_s5_p2: s5-p2@de { 1340 reg = <0xde 0x2>; 1341 bits = <2 6>; 1342 }; 1343 1344 tsens_s6_p2: s6-p2@df { 1345 reg = <0xdf 0x1>; 1346 bits = <0 6>; 1347 }; 1348 1349 tsens_s7_p2: s7-p2@e0 { 1350 reg = <0xe0 0x1>; 1351 bits = <0 6>; 1352 }; 1353 1354 tsens_s8_p2: s8-p2@e0 { 1355 reg = <0xe0 0x2>; 1356 bits = <6 6>; 1357 }; 1358 1359 tsens_s9_p2: s9-p2@e1 { 1360 reg = <0xe1 0x2>; 1361 bits = <4 6>; 1362 }; 1363 1364 tsens_s10_p2: s10_p2@e2 { 1365 reg = <0xe2 0x2>; 1366 bits = <2 6>; 1367 }; 1368 1369 tsens_s5_p2_backup: s5-p2_backup@e3 { 1370 reg = <0xe3 0x2>; 1371 bits = <0 6>; 1372 }; 1373 1374 tsens_mode_backup: mode_backup@e3 { 1375 reg = <0xe3 0x1>; 1376 bits = <6 2>; 1377 }; 1378 1379 tsens_s6_p2_backup: s6-p2_backup@e4 { 1380 reg = <0xe4 0x1>; 1381 bits = <0 6>; 1382 }; 1383 1384 tsens_s7_p2_backup: s7-p2_backup@e4 { 1385 reg = <0xe4 0x2>; 1386 bits = <6 6>; 1387 }; 1388 1389 tsens_s8_p2_backup: s8-p2_backup@e5 { 1390 reg = <0xe5 0x2>; 1391 bits = <4 6>; 1392 }; 1393 1394 tsens_s9_p2_backup: s9-p2_backup@e6 { 1395 reg = <0xe6 0x2>; 1396 bits = <2 6>; 1397 }; 1398 1399 tsens_s10_p2_backup: s10_p2_backup@e7 { 1400 reg = <0xe7 0x1>; 1401 bits = <0 6>; 1402 }; 1403 1404 tsens_base1_backup: base1_backup@440 { 1405 reg = <0x440 0x1>; 1406 bits = <0 8>; 1407 }; 1408 1409 tsens_s0_p1_backup: s0-p1_backup@441 { 1410 reg = <0x441 0x1>; 1411 bits = <0 6>; 1412 }; 1413 1414 tsens_s1_p1_backup: s1-p1_backup@442 { 1415 reg = <0x441 0x2>; 1416 bits = <6 6>; 1417 }; 1418 1419 tsens_s2_p1_backup: s2-p1_backup@442 { 1420 reg = <0x442 0x2>; 1421 bits = <4 6>; 1422 }; 1423 1424 tsens_s3_p1_backup: s3-p1_backup@443 { 1425 reg = <0x443 0x1>; 1426 bits = <2 6>; 1427 }; 1428 1429 tsens_s4_p1_backup: s4-p1_backup@444 { 1430 reg = <0x444 0x1>; 1431 bits = <0 6>; 1432 }; 1433 1434 tsens_s5_p1_backup: s5-p1_backup@444 { 1435 reg = <0x444 0x2>; 1436 bits = <6 6>; 1437 }; 1438 1439 tsens_s6_p1_backup: s6-p1_backup@445 { 1440 reg = <0x445 0x2>; 1441 bits = <4 6>; 1442 }; 1443 1444 tsens_s7_p1_backup: s7-p1_backup@446 { 1445 reg = <0x446 0x1>; 1446 bits = <2 6>; 1447 }; 1448 1449 tsens_use_backup: use_backup@447 { 1450 reg = <0x447 0x1>; 1451 bits = <5 3>; 1452 }; 1453 1454 tsens_s8_p1_backup: s8-p1_backup@448 { 1455 reg = <0x448 0x1>; 1456 bits = <0 6>; 1457 }; 1458 1459 tsens_s9_p1_backup: s9-p1_backup@448 { 1460 reg = <0x448 0x2>; 1461 bits = <6 6>; 1462 }; 1463 1464 tsens_s10_p1_backup: s10_p1_backup@449 { 1465 reg = <0x449 0x2>; 1466 bits = <4 6>; 1467 }; 1468 1469 tsens_base2_backup: base2_backup@44a { 1470 reg = <0x44a 0x2>; 1471 bits = <2 8>; 1472 }; 1473 1474 tsens_s0_p2_backup: s0-p2_backup@44b { 1475 reg = <0x44b 0x3>; 1476 bits = <2 6>; 1477 }; 1478 1479 tsens_s1_p2_backup: s1-p2_backup@44c { 1480 reg = <0x44c 0x1>; 1481 bits = <0 6>; 1482 }; 1483 1484 tsens_s2_p2_backup: s2-p2_backup@44c { 1485 reg = <0x44c 0x2>; 1486 bits = <6 6>; 1487 }; 1488 1489 tsens_s3_p2_backup: s3-p2_backup@44d { 1490 reg = <0x44d 0x2>; 1491 bits = <4 6>; 1492 }; 1493 1494 tsens_s4_p2_backup: s4-p2_backup@44e { 1495 reg = <0x44e 0x1>; 1496 bits = <2 6>; 1497 }; 1498 }; 1499 1500 spmi_bus: spmi@fc4cf000 { 1501 compatible = "qcom,spmi-pmic-arb"; 1502 reg-names = "core", "intr", "cnfg"; 1503 reg = <0xfc4cf000 0x1000>, 1504 <0xfc4cb000 0x1000>, 1505 <0xfc4ca000 0x1000>; 1506 interrupt-names = "periph_irq"; 1507 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1508 qcom,ee = <0>; 1509 qcom,channel = <0>; 1510 #address-cells = <2>; 1511 #size-cells = <0>; 1512 interrupt-controller; 1513 #interrupt-cells = <4>; 1514 }; 1515 1516 bam_dmux_dma: dma-controller@fc834000 { 1517 compatible = "qcom,bam-v1.4.0"; 1518 reg = <0xfc834000 0x7000>; 1519 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1520 #dma-cells = <1>; 1521 qcom,ee = <0>; 1522 1523 num-channels = <6>; 1524 qcom,num-ees = <1>; 1525 qcom,powered-remotely; 1526 }; 1527 1528 remoteproc_mss: remoteproc@fc880000 { 1529 compatible = "qcom,msm8974-mss-pil"; 1530 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1531 reg-names = "qdsp6", "rmb"; 1532 1533 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1534 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1535 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1536 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1537 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1538 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1539 1540 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1541 <&gcc GCC_MSS_CFG_AHB_CLK>, 1542 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1543 <&xo_board>; 1544 clock-names = "iface", "bus", "mem", "xo"; 1545 1546 resets = <&gcc GCC_MSS_RESTART>; 1547 reset-names = "mss_restart"; 1548 1549 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; 1550 1551 qcom,smem-states = <&modem_smp2p_out 0>; 1552 qcom,smem-state-names = "stop"; 1553 1554 status = "disabled"; 1555 1556 mba { 1557 memory-region = <&mba_region>; 1558 }; 1559 1560 mpss { 1561 memory-region = <&mpss_region>; 1562 }; 1563 1564 bam_dmux: bam-dmux { 1565 compatible = "qcom,bam-dmux"; 1566 1567 interrupt-parent = <&modem_smsm>; 1568 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1569 interrupt-names = "pc", "pc-ack"; 1570 1571 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1572 qcom,smem-state-names = "pc", "pc-ack"; 1573 1574 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1575 dma-names = "tx", "rx"; 1576 }; 1577 1578 smd-edge { 1579 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1580 1581 mboxes = <&apcs 12>; 1582 qcom,smd-edge = <0>; 1583 1584 label = "modem"; 1585 }; 1586 }; 1587 1588 tcsr_mutex: hwlock@fd484000 { 1589 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; 1590 reg = <0xfd484000 0x2000>; 1591 #hwlock-cells = <1>; 1592 }; 1593 1594 tcsr: syscon@fd4a0000 { 1595 compatible = "qcom,tcsr-msm8974", "syscon"; 1596 reg = <0xfd4a0000 0x10000>; 1597 }; 1598 1599 tlmm: pinctrl@fd510000 { 1600 compatible = "qcom,msm8974-pinctrl"; 1601 reg = <0xfd510000 0x4000>; 1602 gpio-controller; 1603 gpio-ranges = <&tlmm 0 0 146>; 1604 #gpio-cells = <2>; 1605 interrupt-controller; 1606 #interrupt-cells = <2>; 1607 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1608 1609 sdc1_off: sdc1-off-state { 1610 clk-pins { 1611 pins = "sdc1_clk"; 1612 bias-disable; 1613 drive-strength = <2>; 1614 }; 1615 1616 cmd-pins { 1617 pins = "sdc1_cmd"; 1618 bias-pull-up; 1619 drive-strength = <2>; 1620 }; 1621 1622 data-pins { 1623 pins = "sdc1_data"; 1624 bias-pull-up; 1625 drive-strength = <2>; 1626 }; 1627 }; 1628 1629 sdc2_off: sdc2-off-state { 1630 clk-pins { 1631 pins = "sdc2_clk"; 1632 bias-disable; 1633 drive-strength = <2>; 1634 }; 1635 1636 cmd-pins { 1637 pins = "sdc2_cmd"; 1638 bias-pull-up; 1639 drive-strength = <2>; 1640 }; 1641 1642 data-pins { 1643 pins = "sdc2_data"; 1644 bias-pull-up; 1645 drive-strength = <2>; 1646 }; 1647 }; 1648 1649 blsp1_uart2_default: blsp1-uart2-default-state { 1650 rx-pins { 1651 pins = "gpio5"; 1652 function = "blsp_uart2"; 1653 drive-strength = <2>; 1654 bias-pull-up; 1655 }; 1656 1657 tx-pins { 1658 pins = "gpio4"; 1659 function = "blsp_uart2"; 1660 drive-strength = <4>; 1661 bias-disable; 1662 }; 1663 }; 1664 1665 blsp2_uart1_default: blsp2-uart1-default-state { 1666 tx-rts-pins { 1667 pins = "gpio41", "gpio44"; 1668 function = "blsp_uart7"; 1669 drive-strength = <2>; 1670 bias-disable; 1671 }; 1672 1673 rx-cts-pins { 1674 pins = "gpio42", "gpio43"; 1675 function = "blsp_uart7"; 1676 drive-strength = <2>; 1677 bias-pull-up; 1678 }; 1679 }; 1680 1681 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 1682 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1683 function = "gpio"; 1684 drive-strength = <2>; 1685 bias-pull-down; 1686 }; 1687 1688 blsp2_uart4_default: blsp2-uart4-default-state { 1689 tx-rts-pins { 1690 pins = "gpio53", "gpio56"; 1691 function = "blsp_uart10"; 1692 drive-strength = <2>; 1693 bias-disable; 1694 }; 1695 1696 rx-cts-pins { 1697 pins = "gpio54", "gpio55"; 1698 function = "blsp_uart10"; 1699 drive-strength = <2>; 1700 bias-pull-up; 1701 }; 1702 }; 1703 1704 blsp1_i2c1_default: blsp1-i2c1-default-state { 1705 pins = "gpio2", "gpio3"; 1706 function = "blsp_i2c1"; 1707 drive-strength = <2>; 1708 bias-disable; 1709 }; 1710 1711 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { 1712 pins = "gpio2", "gpio3"; 1713 function = "blsp_i2c1"; 1714 drive-strength = <2>; 1715 bias-pull-up; 1716 }; 1717 1718 blsp1_i2c2_default: blsp1-i2c2-default-state { 1719 pins = "gpio6", "gpio7"; 1720 function = "blsp_i2c2"; 1721 drive-strength = <2>; 1722 bias-disable; 1723 }; 1724 1725 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 1726 pins = "gpio6", "gpio7"; 1727 function = "blsp_i2c2"; 1728 drive-strength = <2>; 1729 bias-pull-up; 1730 }; 1731 1732 blsp1_i2c3_default: blsp1-i2c3-default-state { 1733 pins = "gpio10", "gpio11"; 1734 function = "blsp_i2c3"; 1735 drive-strength = <2>; 1736 bias-disable; 1737 }; 1738 1739 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1740 pins = "gpio10", "gpio11"; 1741 function = "blsp_i2c3"; 1742 drive-strength = <2>; 1743 bias-pull-up; 1744 }; 1745 1746 /* BLSP1_I2C4 info is missing */ 1747 1748 /* BLSP1_I2C5 info is missing */ 1749 1750 blsp1_i2c6_default: blsp1-i2c6-default-state { 1751 pins = "gpio29", "gpio30"; 1752 function = "blsp_i2c6"; 1753 drive-strength = <2>; 1754 bias-disable; 1755 }; 1756 1757 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1758 pins = "gpio29", "gpio30"; 1759 function = "blsp_i2c6"; 1760 drive-strength = <2>; 1761 bias-pull-up; 1762 }; 1763 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1764 1765 /* BLSP2_I2C1 info is missing */ 1766 1767 blsp2_i2c2_default: blsp2-i2c2-default-state { 1768 pins = "gpio47", "gpio48"; 1769 function = "blsp_i2c8"; 1770 drive-strength = <2>; 1771 bias-disable; 1772 }; 1773 1774 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1775 pins = "gpio47", "gpio48"; 1776 function = "blsp_i2c8"; 1777 drive-strength = <2>; 1778 bias-pull-up; 1779 }; 1780 1781 /* BLSP2_I2C3 info is missing */ 1782 1783 /* BLSP2_I2C4 info is missing */ 1784 1785 blsp2_i2c5_default: blsp2-i2c5-default-state { 1786 pins = "gpio83", "gpio84"; 1787 function = "blsp_i2c11"; 1788 drive-strength = <2>; 1789 bias-disable; 1790 }; 1791 1792 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1793 pins = "gpio83", "gpio84"; 1794 function = "blsp_i2c11"; 1795 drive-strength = <2>; 1796 bias-pull-up; 1797 }; 1798 1799 blsp2_i2c6_default: blsp2-i2c6-default-state { 1800 pins = "gpio87", "gpio88"; 1801 function = "blsp_i2c12"; 1802 drive-strength = <2>; 1803 bias-disable; 1804 }; 1805 1806 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1807 pins = "gpio87", "gpio88"; 1808 function = "blsp_i2c12"; 1809 drive-strength = <2>; 1810 bias-pull-up; 1811 }; 1812 1813 cci_default: cci-default-state { 1814 cci_i2c0_default: cci-i2c0-default-pins { 1815 pins = "gpio19", "gpio20"; 1816 function = "cci_i2c0"; 1817 drive-strength = <2>; 1818 bias-disable; 1819 }; 1820 1821 cci_i2c1_default: cci-i2c1-default-pins { 1822 pins = "gpio21", "gpio22"; 1823 function = "cci_i2c1"; 1824 drive-strength = <2>; 1825 bias-disable; 1826 }; 1827 }; 1828 1829 cci_sleep: cci-sleep-state { 1830 cci_i2c0_sleep: cci-i2c0-sleep-pins { 1831 pins = "gpio19", "gpio20"; 1832 function = "gpio"; 1833 drive-strength = <2>; 1834 bias-disable; 1835 }; 1836 1837 cci_i2c1_sleep: cci-i2c1-sleep-pins { 1838 pins = "gpio21", "gpio22"; 1839 function = "gpio"; 1840 drive-strength = <2>; 1841 bias-disable; 1842 }; 1843 }; 1844 1845 spi8_default: spi8_default-state { 1846 mosi-pins { 1847 pins = "gpio45"; 1848 function = "blsp_spi8"; 1849 }; 1850 miso-pins { 1851 pins = "gpio46"; 1852 function = "blsp_spi8"; 1853 }; 1854 cs-pins { 1855 pins = "gpio47"; 1856 function = "blsp_spi8"; 1857 }; 1858 clk-pins { 1859 pins = "gpio48"; 1860 function = "blsp_spi8"; 1861 }; 1862 }; 1863 }; 1864 1865 mmcc: clock-controller@fd8c0000 { 1866 compatible = "qcom,mmcc-msm8974"; 1867 #clock-cells = <1>; 1868 #reset-cells = <1>; 1869 #power-domain-cells = <1>; 1870 reg = <0xfd8c0000 0x6000>; 1871 clocks = <&xo_board>, 1872 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1873 <&gcc GPLL0_VOTE>, 1874 <&gcc GPLL1_VOTE>, 1875 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1876 <&mdss_dsi0_phy 1>, 1877 <&mdss_dsi0_phy 0>, 1878 <&mdss_dsi1_phy 1>, 1879 <&mdss_dsi1_phy 0>, 1880 <0>, 1881 <0>, 1882 <0>; 1883 clock-names = "xo", 1884 "mmss_gpll0_vote", 1885 "gpll0_vote", 1886 "gpll1_vote", 1887 "gfx3d_clk_src", 1888 "dsi0pll", 1889 "dsi0pllbyte", 1890 "dsi1pll", 1891 "dsi1pllbyte", 1892 "hdmipll", 1893 "edp_link_clk", 1894 "edp_vco_div"; 1895 }; 1896 1897 mdss: display-subsystem@fd900000 { 1898 compatible = "qcom,mdss"; 1899 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1900 reg-names = "mdss_phys", "vbif_phys"; 1901 1902 power-domains = <&mmcc MDSS_GDSC>; 1903 1904 clocks = <&mmcc MDSS_AHB_CLK>, 1905 <&mmcc MDSS_AXI_CLK>, 1906 <&mmcc MDSS_VSYNC_CLK>; 1907 clock-names = "iface", "bus", "vsync"; 1908 1909 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1910 1911 interrupt-controller; 1912 #interrupt-cells = <1>; 1913 1914 status = "disabled"; 1915 1916 #address-cells = <1>; 1917 #size-cells = <1>; 1918 ranges; 1919 1920 mdp: display-controller@fd900000 { 1921 compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; 1922 reg = <0xfd900100 0x22000>; 1923 reg-names = "mdp_phys"; 1924 1925 interrupt-parent = <&mdss>; 1926 interrupts = <0>; 1927 1928 clocks = <&mmcc MDSS_AHB_CLK>, 1929 <&mmcc MDSS_AXI_CLK>, 1930 <&mmcc MDSS_MDP_CLK>, 1931 <&mmcc MDSS_VSYNC_CLK>; 1932 clock-names = "iface", "bus", "core", "vsync"; 1933 1934 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1935 interconnect-names = "mdp0-mem"; 1936 1937 ports { 1938 #address-cells = <1>; 1939 #size-cells = <0>; 1940 1941 port@0 { 1942 reg = <0>; 1943 mdp5_intf1_out: endpoint { 1944 remote-endpoint = <&mdss_dsi0_in>; 1945 }; 1946 }; 1947 1948 port@1 { 1949 reg = <1>; 1950 mdp5_intf2_out: endpoint { 1951 remote-endpoint = <&mdss_dsi1_in>; 1952 }; 1953 }; 1954 }; 1955 }; 1956 1957 mdss_dsi0: dsi@fd922800 { 1958 compatible = "qcom,msm8974-dsi-ctrl", 1959 "qcom,mdss-dsi-ctrl"; 1960 reg = <0xfd922800 0x1f8>; 1961 reg-names = "dsi_ctrl"; 1962 1963 interrupt-parent = <&mdss>; 1964 interrupts = <4>; 1965 1966 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1967 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1968 1969 clocks = <&mmcc MDSS_MDP_CLK>, 1970 <&mmcc MDSS_AHB_CLK>, 1971 <&mmcc MDSS_AXI_CLK>, 1972 <&mmcc MDSS_BYTE0_CLK>, 1973 <&mmcc MDSS_PCLK0_CLK>, 1974 <&mmcc MDSS_ESC0_CLK>, 1975 <&mmcc MMSS_MISC_AHB_CLK>; 1976 clock-names = "mdp_core", 1977 "iface", 1978 "bus", 1979 "byte", 1980 "pixel", 1981 "core", 1982 "core_mmss"; 1983 1984 phys = <&mdss_dsi0_phy>; 1985 1986 status = "disabled"; 1987 1988 #address-cells = <1>; 1989 #size-cells = <0>; 1990 1991 ports { 1992 #address-cells = <1>; 1993 #size-cells = <0>; 1994 1995 port@0 { 1996 reg = <0>; 1997 mdss_dsi0_in: endpoint { 1998 remote-endpoint = <&mdp5_intf1_out>; 1999 }; 2000 }; 2001 2002 port@1 { 2003 reg = <1>; 2004 mdss_dsi0_out: endpoint { 2005 }; 2006 }; 2007 }; 2008 }; 2009 2010 mdss_dsi0_phy: phy@fd922a00 { 2011 compatible = "qcom,dsi-phy-28nm-hpm"; 2012 reg = <0xfd922a00 0xd4>, 2013 <0xfd922b00 0x280>, 2014 <0xfd922d80 0x30>; 2015 reg-names = "dsi_pll", 2016 "dsi_phy", 2017 "dsi_phy_regulator"; 2018 2019 #clock-cells = <1>; 2020 #phy-cells = <0>; 2021 2022 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2023 clock-names = "iface", "ref"; 2024 2025 status = "disabled"; 2026 }; 2027 2028 mdss_dsi1: dsi@fd922e00 { 2029 compatible = "qcom,msm8974-dsi-ctrl", 2030 "qcom,mdss-dsi-ctrl"; 2031 reg = <0xfd922e00 0x1f8>; 2032 reg-names = "dsi_ctrl"; 2033 2034 interrupt-parent = <&mdss>; 2035 interrupts = <4>; 2036 2037 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 2038 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2039 2040 clocks = <&mmcc MDSS_MDP_CLK>, 2041 <&mmcc MDSS_AHB_CLK>, 2042 <&mmcc MDSS_AXI_CLK>, 2043 <&mmcc MDSS_BYTE1_CLK>, 2044 <&mmcc MDSS_PCLK1_CLK>, 2045 <&mmcc MDSS_ESC1_CLK>, 2046 <&mmcc MMSS_MISC_AHB_CLK>; 2047 clock-names = "mdp_core", 2048 "iface", 2049 "bus", 2050 "byte", 2051 "pixel", 2052 "core", 2053 "core_mmss"; 2054 2055 phys = <&mdss_dsi1_phy>; 2056 2057 status = "disabled"; 2058 2059 #address-cells = <1>; 2060 #size-cells = <0>; 2061 2062 ports { 2063 #address-cells = <1>; 2064 #size-cells = <0>; 2065 2066 port@0 { 2067 reg = <0>; 2068 mdss_dsi1_in: endpoint { 2069 remote-endpoint = <&mdp5_intf2_out>; 2070 }; 2071 }; 2072 2073 port@1 { 2074 reg = <1>; 2075 mdss_dsi1_out: endpoint { 2076 }; 2077 }; 2078 }; 2079 }; 2080 2081 mdss_dsi1_phy: phy@fd923000 { 2082 compatible = "qcom,dsi-phy-28nm-hpm"; 2083 reg = <0xfd923000 0xd4>, 2084 <0xfd923100 0x280>, 2085 <0xfd923380 0x30>; 2086 reg-names = "dsi_pll", 2087 "dsi_phy", 2088 "dsi_phy_regulator"; 2089 2090 #clock-cells = <1>; 2091 #phy-cells = <0>; 2092 2093 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2094 clock-names = "iface", "ref"; 2095 2096 status = "disabled"; 2097 }; 2098 }; 2099 2100 cci: cci@fda0c000 { 2101 compatible = "qcom,msm8974-cci"; 2102 #address-cells = <1>; 2103 #size-cells = <0>; 2104 reg = <0xfda0c000 0x1000>; 2105 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 2106 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2107 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 2108 <&mmcc CAMSS_CCI_CCI_CLK>; 2109 clock-names = "camss_top_ahb", 2110 "cci_ahb", 2111 "cci"; 2112 2113 pinctrl-names = "default", "sleep"; 2114 pinctrl-0 = <&cci_default>; 2115 pinctrl-1 = <&cci_sleep>; 2116 2117 status = "disabled"; 2118 2119 cci_i2c0: i2c-bus@0 { 2120 reg = <0>; 2121 clock-frequency = <100000>; 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 }; 2125 2126 cci_i2c1: i2c-bus@1 { 2127 reg = <1>; 2128 clock-frequency = <100000>; 2129 #address-cells = <1>; 2130 #size-cells = <0>; 2131 }; 2132 }; 2133 2134 gpu: gpu@fdb00000 { 2135 compatible = "qcom,adreno-330.1", "qcom,adreno"; 2136 reg = <0xfdb00000 0x10000>; 2137 reg-names = "kgsl_3d0_reg_memory"; 2138 2139 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2140 interrupt-names = "kgsl_3d0_irq"; 2141 2142 clocks = <&mmcc OXILI_GFX3D_CLK>, 2143 <&mmcc OXILICX_AHB_CLK>, 2144 <&mmcc OXILICX_AXI_CLK>; 2145 clock-names = "core", "iface", "mem_iface"; 2146 2147 sram = <&gmu_sram>; 2148 power-domains = <&mmcc OXILICX_GDSC>; 2149 operating-points-v2 = <&gpu_opp_table>; 2150 2151 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 2152 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 2153 interconnect-names = "gfx-mem", "ocmem"; 2154 2155 // iommus = <&gpu_iommu 0>; 2156 2157 status = "disabled"; 2158 2159 gpu_opp_table: opp-table { 2160 compatible = "operating-points-v2"; 2161 2162 opp-320000000 { 2163 opp-hz = /bits/ 64 <320000000>; 2164 }; 2165 2166 opp-200000000 { 2167 opp-hz = /bits/ 64 <200000000>; 2168 }; 2169 2170 opp-27000000 { 2171 opp-hz = /bits/ 64 <27000000>; 2172 }; 2173 }; 2174 }; 2175 2176 sram@fdd00000 { 2177 compatible = "qcom,msm8974-ocmem"; 2178 reg = <0xfdd00000 0x2000>, 2179 <0xfec00000 0x180000>; 2180 reg-names = "ctrl", "mem"; 2181 ranges = <0 0xfec00000 0x180000>; 2182 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 2183 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 2184 clock-names = "core", "iface"; 2185 2186 #address-cells = <1>; 2187 #size-cells = <1>; 2188 2189 gmu_sram: gmu-sram@0 { 2190 reg = <0x0 0x100000>; 2191 }; 2192 }; 2193 2194 remoteproc_adsp: remoteproc@fe200000 { 2195 compatible = "qcom,msm8974-adsp-pil"; 2196 reg = <0xfe200000 0x100>; 2197 2198 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2199 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2200 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2201 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2202 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2203 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2204 2205 clocks = <&xo_board>; 2206 clock-names = "xo"; 2207 2208 memory-region = <&adsp_region>; 2209 2210 qcom,smem-states = <&adsp_smp2p_out 0>; 2211 qcom,smem-state-names = "stop"; 2212 2213 status = "disabled"; 2214 2215 smd-edge { 2216 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2217 2218 mboxes = <&apcs 8>; 2219 qcom,smd-edge = <1>; 2220 label = "lpass"; 2221 }; 2222 }; 2223 2224 imem: sram@fe805000 { 2225 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 2226 reg = <0xfe805000 0x1000>; 2227 2228 reboot-mode { 2229 compatible = "syscon-reboot-mode"; 2230 offset = <0x65c>; 2231 }; 2232 }; 2233 }; 2234 2235 thermal-zones { 2236 cpu0-thermal { 2237 polling-delay-passive = <250>; 2238 polling-delay = <1000>; 2239 2240 thermal-sensors = <&tsens 5>; 2241 2242 trips { 2243 cpu_alert0: trip0 { 2244 temperature = <75000>; 2245 hysteresis = <2000>; 2246 type = "passive"; 2247 }; 2248 cpu_crit0: trip1 { 2249 temperature = <110000>; 2250 hysteresis = <2000>; 2251 type = "critical"; 2252 }; 2253 }; 2254 }; 2255 2256 cpu1-thermal { 2257 polling-delay-passive = <250>; 2258 polling-delay = <1000>; 2259 2260 thermal-sensors = <&tsens 6>; 2261 2262 trips { 2263 cpu_alert1: trip0 { 2264 temperature = <75000>; 2265 hysteresis = <2000>; 2266 type = "passive"; 2267 }; 2268 cpu_crit1: trip1 { 2269 temperature = <110000>; 2270 hysteresis = <2000>; 2271 type = "critical"; 2272 }; 2273 }; 2274 }; 2275 2276 cpu2-thermal { 2277 polling-delay-passive = <250>; 2278 polling-delay = <1000>; 2279 2280 thermal-sensors = <&tsens 7>; 2281 2282 trips { 2283 cpu_alert2: trip0 { 2284 temperature = <75000>; 2285 hysteresis = <2000>; 2286 type = "passive"; 2287 }; 2288 cpu_crit2: trip1 { 2289 temperature = <110000>; 2290 hysteresis = <2000>; 2291 type = "critical"; 2292 }; 2293 }; 2294 }; 2295 2296 cpu3-thermal { 2297 polling-delay-passive = <250>; 2298 polling-delay = <1000>; 2299 2300 thermal-sensors = <&tsens 8>; 2301 2302 trips { 2303 cpu_alert3: trip0 { 2304 temperature = <75000>; 2305 hysteresis = <2000>; 2306 type = "passive"; 2307 }; 2308 cpu_crit3: trip1 { 2309 temperature = <110000>; 2310 hysteresis = <2000>; 2311 type = "critical"; 2312 }; 2313 }; 2314 }; 2315 2316 q6-dsp-thermal { 2317 polling-delay-passive = <250>; 2318 polling-delay = <1000>; 2319 2320 thermal-sensors = <&tsens 1>; 2321 2322 trips { 2323 q6_dsp_alert0: trip-point0 { 2324 temperature = <90000>; 2325 hysteresis = <2000>; 2326 type = "hot"; 2327 }; 2328 }; 2329 }; 2330 2331 modemtx-thermal { 2332 polling-delay-passive = <250>; 2333 polling-delay = <1000>; 2334 2335 thermal-sensors = <&tsens 2>; 2336 2337 trips { 2338 modemtx_alert0: trip-point0 { 2339 temperature = <90000>; 2340 hysteresis = <2000>; 2341 type = "hot"; 2342 }; 2343 }; 2344 }; 2345 2346 video-thermal { 2347 polling-delay-passive = <250>; 2348 polling-delay = <1000>; 2349 2350 thermal-sensors = <&tsens 3>; 2351 2352 trips { 2353 video_alert0: trip-point0 { 2354 temperature = <95000>; 2355 hysteresis = <2000>; 2356 type = "hot"; 2357 }; 2358 }; 2359 }; 2360 2361 wlan-thermal { 2362 polling-delay-passive = <250>; 2363 polling-delay = <1000>; 2364 2365 thermal-sensors = <&tsens 4>; 2366 2367 trips { 2368 wlan_alert0: trip-point0 { 2369 temperature = <105000>; 2370 hysteresis = <2000>; 2371 type = "hot"; 2372 }; 2373 }; 2374 }; 2375 2376 gpu-top-thermal { 2377 polling-delay-passive = <250>; 2378 polling-delay = <1000>; 2379 2380 thermal-sensors = <&tsens 9>; 2381 2382 trips { 2383 gpu1_alert0: trip-point0 { 2384 temperature = <90000>; 2385 hysteresis = <2000>; 2386 type = "hot"; 2387 }; 2388 }; 2389 }; 2390 2391 gpu-bottom-thermal { 2392 polling-delay-passive = <250>; 2393 polling-delay = <1000>; 2394 2395 thermal-sensors = <&tsens 10>; 2396 2397 trips { 2398 gpu2_alert0: trip-point0 { 2399 temperature = <90000>; 2400 hysteresis = <2000>; 2401 type = "hot"; 2402 }; 2403 }; 2404 }; 2405 }; 2406 2407 timer { 2408 compatible = "arm,armv7-timer"; 2409 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2410 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2411 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2412 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2413 clock-frequency = <19200000>; 2414 }; 2415}; 2416