1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/dts-v1/; 3*724ba675SRob Herring 4*724ba675SRob Herring#include <dt-bindings/interconnect/qcom,msm8974.h> 5*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 6*724ba675SRob Herring#include <dt-bindings/clock/qcom,gcc-msm8974.h> 7*724ba675SRob Herring#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8*724ba675SRob Herring#include <dt-bindings/clock/qcom,rpmcc.h> 9*724ba675SRob Herring#include <dt-bindings/reset/qcom,gcc-msm8974.h> 10*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring #address-cells = <1>; 14*724ba675SRob Herring #size-cells = <1>; 15*724ba675SRob Herring interrupt-parent = <&intc>; 16*724ba675SRob Herring 17*724ba675SRob Herring clocks { 18*724ba675SRob Herring xo_board: xo_board { 19*724ba675SRob Herring compatible = "fixed-clock"; 20*724ba675SRob Herring #clock-cells = <0>; 21*724ba675SRob Herring clock-frequency = <19200000>; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring sleep_clk: sleep_clk { 25*724ba675SRob Herring compatible = "fixed-clock"; 26*724ba675SRob Herring #clock-cells = <0>; 27*724ba675SRob Herring clock-frequency = <32768>; 28*724ba675SRob Herring }; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring cpus { 32*724ba675SRob Herring #address-cells = <1>; 33*724ba675SRob Herring #size-cells = <0>; 34*724ba675SRob Herring interrupts = <GIC_PPI 9 0xf04>; 35*724ba675SRob Herring 36*724ba675SRob Herring CPU0: cpu@0 { 37*724ba675SRob Herring compatible = "qcom,krait"; 38*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 39*724ba675SRob Herring device_type = "cpu"; 40*724ba675SRob Herring reg = <0>; 41*724ba675SRob Herring next-level-cache = <&L2>; 42*724ba675SRob Herring qcom,acc = <&acc0>; 43*724ba675SRob Herring qcom,saw = <&saw0>; 44*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring CPU1: cpu@1 { 48*724ba675SRob Herring compatible = "qcom,krait"; 49*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 50*724ba675SRob Herring device_type = "cpu"; 51*724ba675SRob Herring reg = <1>; 52*724ba675SRob Herring next-level-cache = <&L2>; 53*724ba675SRob Herring qcom,acc = <&acc1>; 54*724ba675SRob Herring qcom,saw = <&saw1>; 55*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring 58*724ba675SRob Herring CPU2: cpu@2 { 59*724ba675SRob Herring compatible = "qcom,krait"; 60*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 61*724ba675SRob Herring device_type = "cpu"; 62*724ba675SRob Herring reg = <2>; 63*724ba675SRob Herring next-level-cache = <&L2>; 64*724ba675SRob Herring qcom,acc = <&acc2>; 65*724ba675SRob Herring qcom,saw = <&saw2>; 66*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring 69*724ba675SRob Herring CPU3: cpu@3 { 70*724ba675SRob Herring compatible = "qcom,krait"; 71*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 72*724ba675SRob Herring device_type = "cpu"; 73*724ba675SRob Herring reg = <3>; 74*724ba675SRob Herring next-level-cache = <&L2>; 75*724ba675SRob Herring qcom,acc = <&acc3>; 76*724ba675SRob Herring qcom,saw = <&saw3>; 77*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring L2: l2-cache { 81*724ba675SRob Herring compatible = "cache"; 82*724ba675SRob Herring cache-level = <2>; 83*724ba675SRob Herring qcom,saw = <&saw_l2>; 84*724ba675SRob Herring }; 85*724ba675SRob Herring 86*724ba675SRob Herring idle-states { 87*724ba675SRob Herring CPU_SPC: spc { 88*724ba675SRob Herring compatible = "qcom,idle-state-spc", 89*724ba675SRob Herring "arm,idle-state"; 90*724ba675SRob Herring entry-latency-us = <150>; 91*724ba675SRob Herring exit-latency-us = <200>; 92*724ba675SRob Herring min-residency-us = <2000>; 93*724ba675SRob Herring }; 94*724ba675SRob Herring }; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring firmware { 98*724ba675SRob Herring scm { 99*724ba675SRob Herring compatible = "qcom,scm-msm8974", "qcom,scm"; 100*724ba675SRob Herring clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 101*724ba675SRob Herring clock-names = "core", "bus", "iface"; 102*724ba675SRob Herring }; 103*724ba675SRob Herring }; 104*724ba675SRob Herring 105*724ba675SRob Herring memory { 106*724ba675SRob Herring device_type = "memory"; 107*724ba675SRob Herring reg = <0x0 0x0>; 108*724ba675SRob Herring }; 109*724ba675SRob Herring 110*724ba675SRob Herring pmu { 111*724ba675SRob Herring compatible = "qcom,krait-pmu"; 112*724ba675SRob Herring interrupts = <GIC_PPI 7 0xf04>; 113*724ba675SRob Herring }; 114*724ba675SRob Herring 115*724ba675SRob Herring reserved-memory { 116*724ba675SRob Herring #address-cells = <1>; 117*724ba675SRob Herring #size-cells = <1>; 118*724ba675SRob Herring ranges; 119*724ba675SRob Herring 120*724ba675SRob Herring mpss_region: mpss@8000000 { 121*724ba675SRob Herring reg = <0x08000000 0x5100000>; 122*724ba675SRob Herring no-map; 123*724ba675SRob Herring }; 124*724ba675SRob Herring 125*724ba675SRob Herring mba_region: mba@d100000 { 126*724ba675SRob Herring reg = <0x0d100000 0x100000>; 127*724ba675SRob Herring no-map; 128*724ba675SRob Herring }; 129*724ba675SRob Herring 130*724ba675SRob Herring wcnss_region: wcnss@d200000 { 131*724ba675SRob Herring reg = <0x0d200000 0xa00000>; 132*724ba675SRob Herring no-map; 133*724ba675SRob Herring }; 134*724ba675SRob Herring 135*724ba675SRob Herring adsp_region: adsp@dc00000 { 136*724ba675SRob Herring reg = <0x0dc00000 0x1900000>; 137*724ba675SRob Herring no-map; 138*724ba675SRob Herring }; 139*724ba675SRob Herring 140*724ba675SRob Herring venus_region: memory@f500000 { 141*724ba675SRob Herring reg = <0x0f500000 0x500000>; 142*724ba675SRob Herring no-map; 143*724ba675SRob Herring }; 144*724ba675SRob Herring 145*724ba675SRob Herring smem_region: smem@fa00000 { 146*724ba675SRob Herring reg = <0xfa00000 0x200000>; 147*724ba675SRob Herring no-map; 148*724ba675SRob Herring }; 149*724ba675SRob Herring 150*724ba675SRob Herring tz_region: memory@fc00000 { 151*724ba675SRob Herring reg = <0x0fc00000 0x160000>; 152*724ba675SRob Herring no-map; 153*724ba675SRob Herring }; 154*724ba675SRob Herring 155*724ba675SRob Herring rfsa_mem: memory@fd60000 { 156*724ba675SRob Herring reg = <0x0fd60000 0x20000>; 157*724ba675SRob Herring no-map; 158*724ba675SRob Herring }; 159*724ba675SRob Herring 160*724ba675SRob Herring rmtfs@fd80000 { 161*724ba675SRob Herring compatible = "qcom,rmtfs-mem"; 162*724ba675SRob Herring reg = <0x0fd80000 0x180000>; 163*724ba675SRob Herring no-map; 164*724ba675SRob Herring 165*724ba675SRob Herring qcom,client-id = <1>; 166*724ba675SRob Herring }; 167*724ba675SRob Herring }; 168*724ba675SRob Herring 169*724ba675SRob Herring smem { 170*724ba675SRob Herring compatible = "qcom,smem"; 171*724ba675SRob Herring 172*724ba675SRob Herring memory-region = <&smem_region>; 173*724ba675SRob Herring qcom,rpm-msg-ram = <&rpm_msg_ram>; 174*724ba675SRob Herring 175*724ba675SRob Herring hwlocks = <&tcsr_mutex 3>; 176*724ba675SRob Herring }; 177*724ba675SRob Herring 178*724ba675SRob Herring smp2p-adsp { 179*724ba675SRob Herring compatible = "qcom,smp2p"; 180*724ba675SRob Herring qcom,smem = <443>, <429>; 181*724ba675SRob Herring 182*724ba675SRob Herring interrupt-parent = <&intc>; 183*724ba675SRob Herring interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 184*724ba675SRob Herring 185*724ba675SRob Herring qcom,ipc = <&apcs 8 10>; 186*724ba675SRob Herring 187*724ba675SRob Herring qcom,local-pid = <0>; 188*724ba675SRob Herring qcom,remote-pid = <2>; 189*724ba675SRob Herring 190*724ba675SRob Herring adsp_smp2p_out: master-kernel { 191*724ba675SRob Herring qcom,entry-name = "master-kernel"; 192*724ba675SRob Herring #qcom,smem-state-cells = <1>; 193*724ba675SRob Herring }; 194*724ba675SRob Herring 195*724ba675SRob Herring adsp_smp2p_in: slave-kernel { 196*724ba675SRob Herring qcom,entry-name = "slave-kernel"; 197*724ba675SRob Herring 198*724ba675SRob Herring interrupt-controller; 199*724ba675SRob Herring #interrupt-cells = <2>; 200*724ba675SRob Herring }; 201*724ba675SRob Herring }; 202*724ba675SRob Herring 203*724ba675SRob Herring smp2p-modem { 204*724ba675SRob Herring compatible = "qcom,smp2p"; 205*724ba675SRob Herring qcom,smem = <435>, <428>; 206*724ba675SRob Herring 207*724ba675SRob Herring interrupt-parent = <&intc>; 208*724ba675SRob Herring interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 209*724ba675SRob Herring 210*724ba675SRob Herring qcom,ipc = <&apcs 8 14>; 211*724ba675SRob Herring 212*724ba675SRob Herring qcom,local-pid = <0>; 213*724ba675SRob Herring qcom,remote-pid = <1>; 214*724ba675SRob Herring 215*724ba675SRob Herring modem_smp2p_out: master-kernel { 216*724ba675SRob Herring qcom,entry-name = "master-kernel"; 217*724ba675SRob Herring #qcom,smem-state-cells = <1>; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring modem_smp2p_in: slave-kernel { 221*724ba675SRob Herring qcom,entry-name = "slave-kernel"; 222*724ba675SRob Herring 223*724ba675SRob Herring interrupt-controller; 224*724ba675SRob Herring #interrupt-cells = <2>; 225*724ba675SRob Herring }; 226*724ba675SRob Herring }; 227*724ba675SRob Herring 228*724ba675SRob Herring smp2p-wcnss { 229*724ba675SRob Herring compatible = "qcom,smp2p"; 230*724ba675SRob Herring qcom,smem = <451>, <431>; 231*724ba675SRob Herring 232*724ba675SRob Herring interrupt-parent = <&intc>; 233*724ba675SRob Herring interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 234*724ba675SRob Herring 235*724ba675SRob Herring qcom,ipc = <&apcs 8 18>; 236*724ba675SRob Herring 237*724ba675SRob Herring qcom,local-pid = <0>; 238*724ba675SRob Herring qcom,remote-pid = <4>; 239*724ba675SRob Herring 240*724ba675SRob Herring wcnss_smp2p_out: master-kernel { 241*724ba675SRob Herring qcom,entry-name = "master-kernel"; 242*724ba675SRob Herring 243*724ba675SRob Herring #qcom,smem-state-cells = <1>; 244*724ba675SRob Herring }; 245*724ba675SRob Herring 246*724ba675SRob Herring wcnss_smp2p_in: slave-kernel { 247*724ba675SRob Herring qcom,entry-name = "slave-kernel"; 248*724ba675SRob Herring 249*724ba675SRob Herring interrupt-controller; 250*724ba675SRob Herring #interrupt-cells = <2>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring }; 253*724ba675SRob Herring 254*724ba675SRob Herring smsm { 255*724ba675SRob Herring compatible = "qcom,smsm"; 256*724ba675SRob Herring 257*724ba675SRob Herring #address-cells = <1>; 258*724ba675SRob Herring #size-cells = <0>; 259*724ba675SRob Herring 260*724ba675SRob Herring qcom,ipc-1 = <&apcs 8 13>; 261*724ba675SRob Herring qcom,ipc-2 = <&apcs 8 9>; 262*724ba675SRob Herring qcom,ipc-3 = <&apcs 8 19>; 263*724ba675SRob Herring 264*724ba675SRob Herring apps_smsm: apps@0 { 265*724ba675SRob Herring reg = <0>; 266*724ba675SRob Herring 267*724ba675SRob Herring #qcom,smem-state-cells = <1>; 268*724ba675SRob Herring }; 269*724ba675SRob Herring 270*724ba675SRob Herring modem_smsm: modem@1 { 271*724ba675SRob Herring reg = <1>; 272*724ba675SRob Herring interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 273*724ba675SRob Herring 274*724ba675SRob Herring interrupt-controller; 275*724ba675SRob Herring #interrupt-cells = <2>; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring adsp_smsm: adsp@2 { 279*724ba675SRob Herring reg = <2>; 280*724ba675SRob Herring interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 281*724ba675SRob Herring 282*724ba675SRob Herring interrupt-controller; 283*724ba675SRob Herring #interrupt-cells = <2>; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring wcnss_smsm: wcnss@7 { 287*724ba675SRob Herring reg = <7>; 288*724ba675SRob Herring interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 289*724ba675SRob Herring 290*724ba675SRob Herring interrupt-controller; 291*724ba675SRob Herring #interrupt-cells = <2>; 292*724ba675SRob Herring }; 293*724ba675SRob Herring }; 294*724ba675SRob Herring 295*724ba675SRob Herring smd { 296*724ba675SRob Herring compatible = "qcom,smd"; 297*724ba675SRob Herring 298*724ba675SRob Herring rpm { 299*724ba675SRob Herring interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 300*724ba675SRob Herring qcom,ipc = <&apcs 8 0>; 301*724ba675SRob Herring qcom,smd-edge = <15>; 302*724ba675SRob Herring 303*724ba675SRob Herring rpm_requests: rpm-requests { 304*724ba675SRob Herring compatible = "qcom,rpm-msm8974"; 305*724ba675SRob Herring qcom,smd-channels = "rpm_requests"; 306*724ba675SRob Herring 307*724ba675SRob Herring rpmcc: clock-controller { 308*724ba675SRob Herring compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 309*724ba675SRob Herring #clock-cells = <1>; 310*724ba675SRob Herring clocks = <&xo_board>; 311*724ba675SRob Herring clock-names = "xo"; 312*724ba675SRob Herring }; 313*724ba675SRob Herring }; 314*724ba675SRob Herring }; 315*724ba675SRob Herring }; 316*724ba675SRob Herring 317*724ba675SRob Herring soc: soc { 318*724ba675SRob Herring #address-cells = <1>; 319*724ba675SRob Herring #size-cells = <1>; 320*724ba675SRob Herring ranges; 321*724ba675SRob Herring compatible = "simple-bus"; 322*724ba675SRob Herring 323*724ba675SRob Herring intc: interrupt-controller@f9000000 { 324*724ba675SRob Herring compatible = "qcom,msm-qgic2"; 325*724ba675SRob Herring interrupt-controller; 326*724ba675SRob Herring #interrupt-cells = <3>; 327*724ba675SRob Herring reg = <0xf9000000 0x1000>, 328*724ba675SRob Herring <0xf9002000 0x1000>; 329*724ba675SRob Herring }; 330*724ba675SRob Herring 331*724ba675SRob Herring apcs: syscon@f9011000 { 332*724ba675SRob Herring compatible = "syscon"; 333*724ba675SRob Herring reg = <0xf9011000 0x1000>; 334*724ba675SRob Herring }; 335*724ba675SRob Herring 336*724ba675SRob Herring timer@f9020000 { 337*724ba675SRob Herring #address-cells = <1>; 338*724ba675SRob Herring #size-cells = <1>; 339*724ba675SRob Herring ranges; 340*724ba675SRob Herring compatible = "arm,armv7-timer-mem"; 341*724ba675SRob Herring reg = <0xf9020000 0x1000>; 342*724ba675SRob Herring clock-frequency = <19200000>; 343*724ba675SRob Herring 344*724ba675SRob Herring frame@f9021000 { 345*724ba675SRob Herring frame-number = <0>; 346*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 347*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 348*724ba675SRob Herring reg = <0xf9021000 0x1000>, 349*724ba675SRob Herring <0xf9022000 0x1000>; 350*724ba675SRob Herring }; 351*724ba675SRob Herring 352*724ba675SRob Herring frame@f9023000 { 353*724ba675SRob Herring frame-number = <1>; 354*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 355*724ba675SRob Herring reg = <0xf9023000 0x1000>; 356*724ba675SRob Herring status = "disabled"; 357*724ba675SRob Herring }; 358*724ba675SRob Herring 359*724ba675SRob Herring frame@f9024000 { 360*724ba675SRob Herring frame-number = <2>; 361*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 362*724ba675SRob Herring reg = <0xf9024000 0x1000>; 363*724ba675SRob Herring status = "disabled"; 364*724ba675SRob Herring }; 365*724ba675SRob Herring 366*724ba675SRob Herring frame@f9025000 { 367*724ba675SRob Herring frame-number = <3>; 368*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 369*724ba675SRob Herring reg = <0xf9025000 0x1000>; 370*724ba675SRob Herring status = "disabled"; 371*724ba675SRob Herring }; 372*724ba675SRob Herring 373*724ba675SRob Herring frame@f9026000 { 374*724ba675SRob Herring frame-number = <4>; 375*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 376*724ba675SRob Herring reg = <0xf9026000 0x1000>; 377*724ba675SRob Herring status = "disabled"; 378*724ba675SRob Herring }; 379*724ba675SRob Herring 380*724ba675SRob Herring frame@f9027000 { 381*724ba675SRob Herring frame-number = <5>; 382*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 383*724ba675SRob Herring reg = <0xf9027000 0x1000>; 384*724ba675SRob Herring status = "disabled"; 385*724ba675SRob Herring }; 386*724ba675SRob Herring 387*724ba675SRob Herring frame@f9028000 { 388*724ba675SRob Herring frame-number = <6>; 389*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 390*724ba675SRob Herring reg = <0xf9028000 0x1000>; 391*724ba675SRob Herring status = "disabled"; 392*724ba675SRob Herring }; 393*724ba675SRob Herring }; 394*724ba675SRob Herring 395*724ba675SRob Herring saw0: power-controller@f9089000 { 396*724ba675SRob Herring compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 397*724ba675SRob Herring reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 398*724ba675SRob Herring }; 399*724ba675SRob Herring 400*724ba675SRob Herring saw1: power-controller@f9099000 { 401*724ba675SRob Herring compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 402*724ba675SRob Herring reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 403*724ba675SRob Herring }; 404*724ba675SRob Herring 405*724ba675SRob Herring saw2: power-controller@f90a9000 { 406*724ba675SRob Herring compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 407*724ba675SRob Herring reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 408*724ba675SRob Herring }; 409*724ba675SRob Herring 410*724ba675SRob Herring saw3: power-controller@f90b9000 { 411*724ba675SRob Herring compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 412*724ba675SRob Herring reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 413*724ba675SRob Herring }; 414*724ba675SRob Herring 415*724ba675SRob Herring saw_l2: power-controller@f9012000 { 416*724ba675SRob Herring compatible = "qcom,saw2"; 417*724ba675SRob Herring reg = <0xf9012000 0x1000>; 418*724ba675SRob Herring regulator; 419*724ba675SRob Herring }; 420*724ba675SRob Herring 421*724ba675SRob Herring acc0: power-manager@f9088000 { 422*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 423*724ba675SRob Herring reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 424*724ba675SRob Herring }; 425*724ba675SRob Herring 426*724ba675SRob Herring acc1: power-manager@f9098000 { 427*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 428*724ba675SRob Herring reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 429*724ba675SRob Herring }; 430*724ba675SRob Herring 431*724ba675SRob Herring acc2: power-manager@f90a8000 { 432*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 433*724ba675SRob Herring reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 434*724ba675SRob Herring }; 435*724ba675SRob Herring 436*724ba675SRob Herring acc3: power-manager@f90b8000 { 437*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 438*724ba675SRob Herring reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 439*724ba675SRob Herring }; 440*724ba675SRob Herring 441*724ba675SRob Herring sdhc_1: mmc@f9824900 { 442*724ba675SRob Herring compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 443*724ba675SRob Herring reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 444*724ba675SRob Herring reg-names = "hc", "core"; 445*724ba675SRob Herring interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 446*724ba675SRob Herring <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 447*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 448*724ba675SRob Herring clocks = <&gcc GCC_SDCC1_AHB_CLK>, 449*724ba675SRob Herring <&gcc GCC_SDCC1_APPS_CLK>, 450*724ba675SRob Herring <&xo_board>; 451*724ba675SRob Herring clock-names = "iface", "core", "xo"; 452*724ba675SRob Herring bus-width = <8>; 453*724ba675SRob Herring non-removable; 454*724ba675SRob Herring 455*724ba675SRob Herring status = "disabled"; 456*724ba675SRob Herring }; 457*724ba675SRob Herring 458*724ba675SRob Herring sdhc_3: mmc@f9864900 { 459*724ba675SRob Herring compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 460*724ba675SRob Herring reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 461*724ba675SRob Herring reg-names = "hc", "core"; 462*724ba675SRob Herring interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 463*724ba675SRob Herring <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 464*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 465*724ba675SRob Herring clocks = <&gcc GCC_SDCC3_AHB_CLK>, 466*724ba675SRob Herring <&gcc GCC_SDCC3_APPS_CLK>, 467*724ba675SRob Herring <&xo_board>; 468*724ba675SRob Herring clock-names = "iface", "core", "xo"; 469*724ba675SRob Herring bus-width = <4>; 470*724ba675SRob Herring 471*724ba675SRob Herring #address-cells = <1>; 472*724ba675SRob Herring #size-cells = <0>; 473*724ba675SRob Herring 474*724ba675SRob Herring status = "disabled"; 475*724ba675SRob Herring }; 476*724ba675SRob Herring 477*724ba675SRob Herring sdhc_2: mmc@f98a4900 { 478*724ba675SRob Herring compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 479*724ba675SRob Herring reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 480*724ba675SRob Herring reg-names = "hc", "core"; 481*724ba675SRob Herring interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 482*724ba675SRob Herring <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 483*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 484*724ba675SRob Herring clocks = <&gcc GCC_SDCC2_AHB_CLK>, 485*724ba675SRob Herring <&gcc GCC_SDCC2_APPS_CLK>, 486*724ba675SRob Herring <&xo_board>; 487*724ba675SRob Herring clock-names = "iface", "core", "xo"; 488*724ba675SRob Herring bus-width = <4>; 489*724ba675SRob Herring 490*724ba675SRob Herring #address-cells = <1>; 491*724ba675SRob Herring #size-cells = <0>; 492*724ba675SRob Herring 493*724ba675SRob Herring status = "disabled"; 494*724ba675SRob Herring }; 495*724ba675SRob Herring 496*724ba675SRob Herring blsp1_uart1: serial@f991d000 { 497*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 498*724ba675SRob Herring reg = <0xf991d000 0x1000>; 499*724ba675SRob Herring interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 500*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 501*724ba675SRob Herring clock-names = "core", "iface"; 502*724ba675SRob Herring status = "disabled"; 503*724ba675SRob Herring }; 504*724ba675SRob Herring 505*724ba675SRob Herring blsp1_uart2: serial@f991e000 { 506*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 507*724ba675SRob Herring reg = <0xf991e000 0x1000>; 508*724ba675SRob Herring interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 509*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 510*724ba675SRob Herring clock-names = "core", "iface"; 511*724ba675SRob Herring pinctrl-names = "default"; 512*724ba675SRob Herring pinctrl-0 = <&blsp1_uart2_default>; 513*724ba675SRob Herring status = "disabled"; 514*724ba675SRob Herring }; 515*724ba675SRob Herring 516*724ba675SRob Herring blsp1_i2c1: i2c@f9923000 { 517*724ba675SRob Herring status = "disabled"; 518*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 519*724ba675SRob Herring reg = <0xf9923000 0x1000>; 520*724ba675SRob Herring interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 521*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 522*724ba675SRob Herring clock-names = "core", "iface"; 523*724ba675SRob Herring pinctrl-names = "default", "sleep"; 524*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c1_default>; 525*724ba675SRob Herring pinctrl-1 = <&blsp1_i2c1_sleep>; 526*724ba675SRob Herring #address-cells = <1>; 527*724ba675SRob Herring #size-cells = <0>; 528*724ba675SRob Herring }; 529*724ba675SRob Herring 530*724ba675SRob Herring blsp1_i2c2: i2c@f9924000 { 531*724ba675SRob Herring status = "disabled"; 532*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 533*724ba675SRob Herring reg = <0xf9924000 0x1000>; 534*724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 535*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 536*724ba675SRob Herring clock-names = "core", "iface"; 537*724ba675SRob Herring pinctrl-names = "default", "sleep"; 538*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c2_default>; 539*724ba675SRob Herring pinctrl-1 = <&blsp1_i2c2_sleep>; 540*724ba675SRob Herring #address-cells = <1>; 541*724ba675SRob Herring #size-cells = <0>; 542*724ba675SRob Herring }; 543*724ba675SRob Herring 544*724ba675SRob Herring blsp1_i2c3: i2c@f9925000 { 545*724ba675SRob Herring status = "disabled"; 546*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 547*724ba675SRob Herring reg = <0xf9925000 0x1000>; 548*724ba675SRob Herring interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 549*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 550*724ba675SRob Herring clock-names = "core", "iface"; 551*724ba675SRob Herring pinctrl-names = "default", "sleep"; 552*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c3_default>; 553*724ba675SRob Herring pinctrl-1 = <&blsp1_i2c3_sleep>; 554*724ba675SRob Herring #address-cells = <1>; 555*724ba675SRob Herring #size-cells = <0>; 556*724ba675SRob Herring }; 557*724ba675SRob Herring 558*724ba675SRob Herring blsp1_i2c6: i2c@f9928000 { 559*724ba675SRob Herring status = "disabled"; 560*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 561*724ba675SRob Herring reg = <0xf9928000 0x1000>; 562*724ba675SRob Herring interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 563*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 564*724ba675SRob Herring clock-names = "core", "iface"; 565*724ba675SRob Herring pinctrl-names = "default", "sleep"; 566*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c6_default>; 567*724ba675SRob Herring pinctrl-1 = <&blsp1_i2c6_sleep>; 568*724ba675SRob Herring #address-cells = <1>; 569*724ba675SRob Herring #size-cells = <0>; 570*724ba675SRob Herring }; 571*724ba675SRob Herring 572*724ba675SRob Herring blsp2_dma: dma-controller@f9944000 { 573*724ba675SRob Herring compatible = "qcom,bam-v1.4.0"; 574*724ba675SRob Herring reg = <0xf9944000 0x19000>; 575*724ba675SRob Herring interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 576*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_AHB_CLK>; 577*724ba675SRob Herring clock-names = "bam_clk"; 578*724ba675SRob Herring #dma-cells = <1>; 579*724ba675SRob Herring qcom,ee = <0>; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring blsp2_uart1: serial@f995d000 { 583*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 584*724ba675SRob Herring reg = <0xf995d000 0x1000>; 585*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 586*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 587*724ba675SRob Herring clock-names = "core", "iface"; 588*724ba675SRob Herring pinctrl-names = "default", "sleep"; 589*724ba675SRob Herring pinctrl-0 = <&blsp2_uart1_default>; 590*724ba675SRob Herring pinctrl-1 = <&blsp2_uart1_sleep>; 591*724ba675SRob Herring status = "disabled"; 592*724ba675SRob Herring }; 593*724ba675SRob Herring 594*724ba675SRob Herring blsp2_uart2: serial@f995e000 { 595*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 596*724ba675SRob Herring reg = <0xf995e000 0x1000>; 597*724ba675SRob Herring interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 598*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 599*724ba675SRob Herring clock-names = "core", "iface"; 600*724ba675SRob Herring status = "disabled"; 601*724ba675SRob Herring }; 602*724ba675SRob Herring 603*724ba675SRob Herring blsp2_uart4: serial@f9960000 { 604*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 605*724ba675SRob Herring reg = <0xf9960000 0x1000>; 606*724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 607*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 608*724ba675SRob Herring clock-names = "core", "iface"; 609*724ba675SRob Herring pinctrl-names = "default"; 610*724ba675SRob Herring pinctrl-0 = <&blsp2_uart4_default>; 611*724ba675SRob Herring status = "disabled"; 612*724ba675SRob Herring }; 613*724ba675SRob Herring 614*724ba675SRob Herring blsp2_i2c2: i2c@f9964000 { 615*724ba675SRob Herring status = "disabled"; 616*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 617*724ba675SRob Herring reg = <0xf9964000 0x1000>; 618*724ba675SRob Herring interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 619*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 620*724ba675SRob Herring clock-names = "core", "iface"; 621*724ba675SRob Herring pinctrl-names = "default", "sleep"; 622*724ba675SRob Herring pinctrl-0 = <&blsp2_i2c2_default>; 623*724ba675SRob Herring pinctrl-1 = <&blsp2_i2c2_sleep>; 624*724ba675SRob Herring #address-cells = <1>; 625*724ba675SRob Herring #size-cells = <0>; 626*724ba675SRob Herring }; 627*724ba675SRob Herring 628*724ba675SRob Herring blsp2_i2c5: i2c@f9967000 { 629*724ba675SRob Herring status = "disabled"; 630*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 631*724ba675SRob Herring reg = <0xf9967000 0x1000>; 632*724ba675SRob Herring interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 633*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 634*724ba675SRob Herring clock-names = "core", "iface"; 635*724ba675SRob Herring dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 636*724ba675SRob Herring dma-names = "tx", "rx"; 637*724ba675SRob Herring pinctrl-names = "default", "sleep"; 638*724ba675SRob Herring pinctrl-0 = <&blsp2_i2c5_default>; 639*724ba675SRob Herring pinctrl-1 = <&blsp2_i2c5_sleep>; 640*724ba675SRob Herring #address-cells = <1>; 641*724ba675SRob Herring #size-cells = <0>; 642*724ba675SRob Herring }; 643*724ba675SRob Herring 644*724ba675SRob Herring blsp2_i2c6: i2c@f9968000 { 645*724ba675SRob Herring status = "disabled"; 646*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 647*724ba675SRob Herring reg = <0xf9968000 0x1000>; 648*724ba675SRob Herring interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 649*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 650*724ba675SRob Herring clock-names = "core", "iface"; 651*724ba675SRob Herring pinctrl-names = "default", "sleep"; 652*724ba675SRob Herring pinctrl-0 = <&blsp2_i2c6_default>; 653*724ba675SRob Herring pinctrl-1 = <&blsp2_i2c6_sleep>; 654*724ba675SRob Herring #address-cells = <1>; 655*724ba675SRob Herring #size-cells = <0>; 656*724ba675SRob Herring }; 657*724ba675SRob Herring 658*724ba675SRob Herring usb: usb@f9a55000 { 659*724ba675SRob Herring compatible = "qcom,ci-hdrc"; 660*724ba675SRob Herring reg = <0xf9a55000 0x200>, 661*724ba675SRob Herring <0xf9a55200 0x200>; 662*724ba675SRob Herring interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 663*724ba675SRob Herring clocks = <&gcc GCC_USB_HS_AHB_CLK>, 664*724ba675SRob Herring <&gcc GCC_USB_HS_SYSTEM_CLK>; 665*724ba675SRob Herring clock-names = "iface", "core"; 666*724ba675SRob Herring assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 667*724ba675SRob Herring assigned-clock-rates = <75000000>; 668*724ba675SRob Herring resets = <&gcc GCC_USB_HS_BCR>; 669*724ba675SRob Herring reset-names = "core"; 670*724ba675SRob Herring phy_type = "ulpi"; 671*724ba675SRob Herring dr_mode = "otg"; 672*724ba675SRob Herring ahb-burst-config = <0>; 673*724ba675SRob Herring phy-names = "usb-phy"; 674*724ba675SRob Herring status = "disabled"; 675*724ba675SRob Herring #reset-cells = <1>; 676*724ba675SRob Herring 677*724ba675SRob Herring ulpi { 678*724ba675SRob Herring usb_hs1_phy: phy-0 { 679*724ba675SRob Herring compatible = "qcom,usb-hs-phy-msm8974", 680*724ba675SRob Herring "qcom,usb-hs-phy"; 681*724ba675SRob Herring #phy-cells = <0>; 682*724ba675SRob Herring clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 683*724ba675SRob Herring clock-names = "ref", "sleep"; 684*724ba675SRob Herring resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 685*724ba675SRob Herring reset-names = "phy", "por"; 686*724ba675SRob Herring status = "disabled"; 687*724ba675SRob Herring }; 688*724ba675SRob Herring 689*724ba675SRob Herring usb_hs2_phy: phy-1 { 690*724ba675SRob Herring compatible = "qcom,usb-hs-phy-msm8974", 691*724ba675SRob Herring "qcom,usb-hs-phy"; 692*724ba675SRob Herring #phy-cells = <0>; 693*724ba675SRob Herring clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 694*724ba675SRob Herring clock-names = "ref", "sleep"; 695*724ba675SRob Herring resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; 696*724ba675SRob Herring reset-names = "phy", "por"; 697*724ba675SRob Herring status = "disabled"; 698*724ba675SRob Herring }; 699*724ba675SRob Herring }; 700*724ba675SRob Herring }; 701*724ba675SRob Herring 702*724ba675SRob Herring rng@f9bff000 { 703*724ba675SRob Herring compatible = "qcom,prng"; 704*724ba675SRob Herring reg = <0xf9bff000 0x200>; 705*724ba675SRob Herring clocks = <&gcc GCC_PRNG_AHB_CLK>; 706*724ba675SRob Herring clock-names = "core"; 707*724ba675SRob Herring }; 708*724ba675SRob Herring 709*724ba675SRob Herring pronto: remoteproc@fb204000 { 710*724ba675SRob Herring compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 711*724ba675SRob Herring reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 712*724ba675SRob Herring reg-names = "ccu", "dxe", "pmu"; 713*724ba675SRob Herring 714*724ba675SRob Herring memory-region = <&wcnss_region>; 715*724ba675SRob Herring 716*724ba675SRob Herring interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 717*724ba675SRob Herring <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 718*724ba675SRob Herring <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 719*724ba675SRob Herring <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 720*724ba675SRob Herring <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 721*724ba675SRob Herring interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 722*724ba675SRob Herring 723*724ba675SRob Herring qcom,smem-states = <&wcnss_smp2p_out 0>; 724*724ba675SRob Herring qcom,smem-state-names = "stop"; 725*724ba675SRob Herring 726*724ba675SRob Herring status = "disabled"; 727*724ba675SRob Herring 728*724ba675SRob Herring iris { 729*724ba675SRob Herring compatible = "qcom,wcn3680"; 730*724ba675SRob Herring 731*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_CXO_A2>; 732*724ba675SRob Herring clock-names = "xo"; 733*724ba675SRob Herring }; 734*724ba675SRob Herring 735*724ba675SRob Herring smd-edge { 736*724ba675SRob Herring interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 737*724ba675SRob Herring 738*724ba675SRob Herring qcom,ipc = <&apcs 8 17>; 739*724ba675SRob Herring qcom,smd-edge = <6>; 740*724ba675SRob Herring 741*724ba675SRob Herring wcnss { 742*724ba675SRob Herring compatible = "qcom,wcnss"; 743*724ba675SRob Herring qcom,smd-channels = "WCNSS_CTRL"; 744*724ba675SRob Herring status = "disabled"; 745*724ba675SRob Herring 746*724ba675SRob Herring qcom,mmio = <&pronto>; 747*724ba675SRob Herring 748*724ba675SRob Herring bluetooth { 749*724ba675SRob Herring compatible = "qcom,wcnss-bt"; 750*724ba675SRob Herring }; 751*724ba675SRob Herring 752*724ba675SRob Herring wifi { 753*724ba675SRob Herring compatible = "qcom,wcnss-wlan"; 754*724ba675SRob Herring 755*724ba675SRob Herring interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 756*724ba675SRob Herring <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 757*724ba675SRob Herring interrupt-names = "tx", "rx"; 758*724ba675SRob Herring 759*724ba675SRob Herring qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 760*724ba675SRob Herring qcom,smem-state-names = "tx-enable", 761*724ba675SRob Herring "tx-rings-empty"; 762*724ba675SRob Herring }; 763*724ba675SRob Herring }; 764*724ba675SRob Herring }; 765*724ba675SRob Herring }; 766*724ba675SRob Herring 767*724ba675SRob Herring sram@fc190000 { 768*724ba675SRob Herring compatible = "qcom,msm8974-rpm-stats"; 769*724ba675SRob Herring reg = <0xfc190000 0x10000>; 770*724ba675SRob Herring }; 771*724ba675SRob Herring 772*724ba675SRob Herring etf@fc307000 { 773*724ba675SRob Herring compatible = "arm,coresight-tmc", "arm,primecell"; 774*724ba675SRob Herring reg = <0xfc307000 0x1000>; 775*724ba675SRob Herring 776*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 777*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 778*724ba675SRob Herring 779*724ba675SRob Herring out-ports { 780*724ba675SRob Herring port { 781*724ba675SRob Herring etf_out: endpoint { 782*724ba675SRob Herring remote-endpoint = <&replicator_in>; 783*724ba675SRob Herring }; 784*724ba675SRob Herring }; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring in-ports { 788*724ba675SRob Herring port { 789*724ba675SRob Herring etf_in: endpoint { 790*724ba675SRob Herring remote-endpoint = <&merger_out>; 791*724ba675SRob Herring }; 792*724ba675SRob Herring }; 793*724ba675SRob Herring }; 794*724ba675SRob Herring }; 795*724ba675SRob Herring 796*724ba675SRob Herring tpiu@fc318000 { 797*724ba675SRob Herring compatible = "arm,coresight-tpiu", "arm,primecell"; 798*724ba675SRob Herring reg = <0xfc318000 0x1000>; 799*724ba675SRob Herring 800*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 801*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 802*724ba675SRob Herring 803*724ba675SRob Herring in-ports { 804*724ba675SRob Herring port { 805*724ba675SRob Herring tpiu_in: endpoint { 806*724ba675SRob Herring remote-endpoint = <&replicator_out1>; 807*724ba675SRob Herring }; 808*724ba675SRob Herring }; 809*724ba675SRob Herring }; 810*724ba675SRob Herring }; 811*724ba675SRob Herring 812*724ba675SRob Herring funnel@fc31a000 { 813*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 814*724ba675SRob Herring reg = <0xfc31a000 0x1000>; 815*724ba675SRob Herring 816*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 817*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 818*724ba675SRob Herring 819*724ba675SRob Herring in-ports { 820*724ba675SRob Herring #address-cells = <1>; 821*724ba675SRob Herring #size-cells = <0>; 822*724ba675SRob Herring 823*724ba675SRob Herring /* 824*724ba675SRob Herring * Not described input ports: 825*724ba675SRob Herring * 0 - not-connected 826*724ba675SRob Herring * 1 - connected trought funnel to Multimedia CPU 827*724ba675SRob Herring * 2 - connected to Wireless CPU 828*724ba675SRob Herring * 3 - not-connected 829*724ba675SRob Herring * 4 - not-connected 830*724ba675SRob Herring * 6 - not-connected 831*724ba675SRob Herring * 7 - connected to STM 832*724ba675SRob Herring */ 833*724ba675SRob Herring port@5 { 834*724ba675SRob Herring reg = <5>; 835*724ba675SRob Herring funnel1_in5: endpoint { 836*724ba675SRob Herring remote-endpoint = <&kpss_out>; 837*724ba675SRob Herring }; 838*724ba675SRob Herring }; 839*724ba675SRob Herring }; 840*724ba675SRob Herring 841*724ba675SRob Herring out-ports { 842*724ba675SRob Herring port { 843*724ba675SRob Herring funnel1_out: endpoint { 844*724ba675SRob Herring remote-endpoint = <&merger_in1>; 845*724ba675SRob Herring }; 846*724ba675SRob Herring }; 847*724ba675SRob Herring }; 848*724ba675SRob Herring }; 849*724ba675SRob Herring 850*724ba675SRob Herring funnel@fc31b000 { 851*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 852*724ba675SRob Herring reg = <0xfc31b000 0x1000>; 853*724ba675SRob Herring 854*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 855*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 856*724ba675SRob Herring 857*724ba675SRob Herring in-ports { 858*724ba675SRob Herring #address-cells = <1>; 859*724ba675SRob Herring #size-cells = <0>; 860*724ba675SRob Herring 861*724ba675SRob Herring /* 862*724ba675SRob Herring * Not described input ports: 863*724ba675SRob Herring * 0 - connected trought funnel to Audio, Modem and 864*724ba675SRob Herring * Resource and Power Manager CPU's 865*724ba675SRob Herring * 2...7 - not-connected 866*724ba675SRob Herring */ 867*724ba675SRob Herring port@1 { 868*724ba675SRob Herring reg = <1>; 869*724ba675SRob Herring merger_in1: endpoint { 870*724ba675SRob Herring remote-endpoint = <&funnel1_out>; 871*724ba675SRob Herring }; 872*724ba675SRob Herring }; 873*724ba675SRob Herring }; 874*724ba675SRob Herring 875*724ba675SRob Herring out-ports { 876*724ba675SRob Herring port { 877*724ba675SRob Herring merger_out: endpoint { 878*724ba675SRob Herring remote-endpoint = <&etf_in>; 879*724ba675SRob Herring }; 880*724ba675SRob Herring }; 881*724ba675SRob Herring }; 882*724ba675SRob Herring }; 883*724ba675SRob Herring 884*724ba675SRob Herring replicator@fc31c000 { 885*724ba675SRob Herring compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 886*724ba675SRob Herring reg = <0xfc31c000 0x1000>; 887*724ba675SRob Herring 888*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 889*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 890*724ba675SRob Herring 891*724ba675SRob Herring out-ports { 892*724ba675SRob Herring #address-cells = <1>; 893*724ba675SRob Herring #size-cells = <0>; 894*724ba675SRob Herring 895*724ba675SRob Herring port@0 { 896*724ba675SRob Herring reg = <0>; 897*724ba675SRob Herring replicator_out0: endpoint { 898*724ba675SRob Herring remote-endpoint = <&etr_in>; 899*724ba675SRob Herring }; 900*724ba675SRob Herring }; 901*724ba675SRob Herring port@1 { 902*724ba675SRob Herring reg = <1>; 903*724ba675SRob Herring replicator_out1: endpoint { 904*724ba675SRob Herring remote-endpoint = <&tpiu_in>; 905*724ba675SRob Herring }; 906*724ba675SRob Herring }; 907*724ba675SRob Herring }; 908*724ba675SRob Herring 909*724ba675SRob Herring in-ports { 910*724ba675SRob Herring port { 911*724ba675SRob Herring replicator_in: endpoint { 912*724ba675SRob Herring remote-endpoint = <&etf_out>; 913*724ba675SRob Herring }; 914*724ba675SRob Herring }; 915*724ba675SRob Herring }; 916*724ba675SRob Herring }; 917*724ba675SRob Herring 918*724ba675SRob Herring etr@fc322000 { 919*724ba675SRob Herring compatible = "arm,coresight-tmc", "arm,primecell"; 920*724ba675SRob Herring reg = <0xfc322000 0x1000>; 921*724ba675SRob Herring 922*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 923*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 924*724ba675SRob Herring 925*724ba675SRob Herring in-ports { 926*724ba675SRob Herring port { 927*724ba675SRob Herring etr_in: endpoint { 928*724ba675SRob Herring remote-endpoint = <&replicator_out0>; 929*724ba675SRob Herring }; 930*724ba675SRob Herring }; 931*724ba675SRob Herring }; 932*724ba675SRob Herring }; 933*724ba675SRob Herring 934*724ba675SRob Herring etm@fc33c000 { 935*724ba675SRob Herring compatible = "arm,coresight-etm4x", "arm,primecell"; 936*724ba675SRob Herring reg = <0xfc33c000 0x1000>; 937*724ba675SRob Herring 938*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 939*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 940*724ba675SRob Herring 941*724ba675SRob Herring cpu = <&CPU0>; 942*724ba675SRob Herring 943*724ba675SRob Herring out-ports { 944*724ba675SRob Herring port { 945*724ba675SRob Herring etm0_out: endpoint { 946*724ba675SRob Herring remote-endpoint = <&kpss_in0>; 947*724ba675SRob Herring }; 948*724ba675SRob Herring }; 949*724ba675SRob Herring }; 950*724ba675SRob Herring }; 951*724ba675SRob Herring 952*724ba675SRob Herring etm@fc33d000 { 953*724ba675SRob Herring compatible = "arm,coresight-etm4x", "arm,primecell"; 954*724ba675SRob Herring reg = <0xfc33d000 0x1000>; 955*724ba675SRob Herring 956*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 957*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 958*724ba675SRob Herring 959*724ba675SRob Herring cpu = <&CPU1>; 960*724ba675SRob Herring 961*724ba675SRob Herring out-ports { 962*724ba675SRob Herring port { 963*724ba675SRob Herring etm1_out: endpoint { 964*724ba675SRob Herring remote-endpoint = <&kpss_in1>; 965*724ba675SRob Herring }; 966*724ba675SRob Herring }; 967*724ba675SRob Herring }; 968*724ba675SRob Herring }; 969*724ba675SRob Herring 970*724ba675SRob Herring etm@fc33e000 { 971*724ba675SRob Herring compatible = "arm,coresight-etm4x", "arm,primecell"; 972*724ba675SRob Herring reg = <0xfc33e000 0x1000>; 973*724ba675SRob Herring 974*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 975*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 976*724ba675SRob Herring 977*724ba675SRob Herring cpu = <&CPU2>; 978*724ba675SRob Herring 979*724ba675SRob Herring out-ports { 980*724ba675SRob Herring port { 981*724ba675SRob Herring etm2_out: endpoint { 982*724ba675SRob Herring remote-endpoint = <&kpss_in2>; 983*724ba675SRob Herring }; 984*724ba675SRob Herring }; 985*724ba675SRob Herring }; 986*724ba675SRob Herring }; 987*724ba675SRob Herring 988*724ba675SRob Herring etm@fc33f000 { 989*724ba675SRob Herring compatible = "arm,coresight-etm4x", "arm,primecell"; 990*724ba675SRob Herring reg = <0xfc33f000 0x1000>; 991*724ba675SRob Herring 992*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 993*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 994*724ba675SRob Herring 995*724ba675SRob Herring cpu = <&CPU3>; 996*724ba675SRob Herring 997*724ba675SRob Herring out-ports { 998*724ba675SRob Herring port { 999*724ba675SRob Herring etm3_out: endpoint { 1000*724ba675SRob Herring remote-endpoint = <&kpss_in3>; 1001*724ba675SRob Herring }; 1002*724ba675SRob Herring }; 1003*724ba675SRob Herring }; 1004*724ba675SRob Herring }; 1005*724ba675SRob Herring 1006*724ba675SRob Herring /* KPSS funnel, only 4 inputs are used */ 1007*724ba675SRob Herring funnel@fc345000 { 1008*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1009*724ba675SRob Herring reg = <0xfc345000 0x1000>; 1010*724ba675SRob Herring 1011*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1012*724ba675SRob Herring clock-names = "apb_pclk", "atclk"; 1013*724ba675SRob Herring 1014*724ba675SRob Herring in-ports { 1015*724ba675SRob Herring #address-cells = <1>; 1016*724ba675SRob Herring #size-cells = <0>; 1017*724ba675SRob Herring 1018*724ba675SRob Herring port@0 { 1019*724ba675SRob Herring reg = <0>; 1020*724ba675SRob Herring kpss_in0: endpoint { 1021*724ba675SRob Herring remote-endpoint = <&etm0_out>; 1022*724ba675SRob Herring }; 1023*724ba675SRob Herring }; 1024*724ba675SRob Herring port@1 { 1025*724ba675SRob Herring reg = <1>; 1026*724ba675SRob Herring kpss_in1: endpoint { 1027*724ba675SRob Herring remote-endpoint = <&etm1_out>; 1028*724ba675SRob Herring }; 1029*724ba675SRob Herring }; 1030*724ba675SRob Herring port@2 { 1031*724ba675SRob Herring reg = <2>; 1032*724ba675SRob Herring kpss_in2: endpoint { 1033*724ba675SRob Herring remote-endpoint = <&etm2_out>; 1034*724ba675SRob Herring }; 1035*724ba675SRob Herring }; 1036*724ba675SRob Herring port@3 { 1037*724ba675SRob Herring reg = <3>; 1038*724ba675SRob Herring kpss_in3: endpoint { 1039*724ba675SRob Herring remote-endpoint = <&etm3_out>; 1040*724ba675SRob Herring }; 1041*724ba675SRob Herring }; 1042*724ba675SRob Herring }; 1043*724ba675SRob Herring 1044*724ba675SRob Herring out-ports { 1045*724ba675SRob Herring port { 1046*724ba675SRob Herring kpss_out: endpoint { 1047*724ba675SRob Herring remote-endpoint = <&funnel1_in5>; 1048*724ba675SRob Herring }; 1049*724ba675SRob Herring }; 1050*724ba675SRob Herring }; 1051*724ba675SRob Herring }; 1052*724ba675SRob Herring 1053*724ba675SRob Herring gcc: clock-controller@fc400000 { 1054*724ba675SRob Herring compatible = "qcom,gcc-msm8974"; 1055*724ba675SRob Herring #clock-cells = <1>; 1056*724ba675SRob Herring #reset-cells = <1>; 1057*724ba675SRob Herring #power-domain-cells = <1>; 1058*724ba675SRob Herring reg = <0xfc400000 0x4000>; 1059*724ba675SRob Herring 1060*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1061*724ba675SRob Herring <&sleep_clk>; 1062*724ba675SRob Herring clock-names = "xo", 1063*724ba675SRob Herring "sleep_clk"; 1064*724ba675SRob Herring }; 1065*724ba675SRob Herring 1066*724ba675SRob Herring rpm_msg_ram: sram@fc428000 { 1067*724ba675SRob Herring compatible = "qcom,rpm-msg-ram"; 1068*724ba675SRob Herring reg = <0xfc428000 0x4000>; 1069*724ba675SRob Herring }; 1070*724ba675SRob Herring 1071*724ba675SRob Herring bimc: interconnect@fc380000 { 1072*724ba675SRob Herring reg = <0xfc380000 0x6a000>; 1073*724ba675SRob Herring compatible = "qcom,msm8974-bimc"; 1074*724ba675SRob Herring #interconnect-cells = <1>; 1075*724ba675SRob Herring clock-names = "bus", "bus_a"; 1076*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1077*724ba675SRob Herring <&rpmcc RPM_SMD_BIMC_A_CLK>; 1078*724ba675SRob Herring }; 1079*724ba675SRob Herring 1080*724ba675SRob Herring snoc: interconnect@fc460000 { 1081*724ba675SRob Herring reg = <0xfc460000 0x4000>; 1082*724ba675SRob Herring compatible = "qcom,msm8974-snoc"; 1083*724ba675SRob Herring #interconnect-cells = <1>; 1084*724ba675SRob Herring clock-names = "bus", "bus_a"; 1085*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1086*724ba675SRob Herring <&rpmcc RPM_SMD_SNOC_A_CLK>; 1087*724ba675SRob Herring }; 1088*724ba675SRob Herring 1089*724ba675SRob Herring pnoc: interconnect@fc468000 { 1090*724ba675SRob Herring reg = <0xfc468000 0x4000>; 1091*724ba675SRob Herring compatible = "qcom,msm8974-pnoc"; 1092*724ba675SRob Herring #interconnect-cells = <1>; 1093*724ba675SRob Herring clock-names = "bus", "bus_a"; 1094*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1095*724ba675SRob Herring <&rpmcc RPM_SMD_PNOC_A_CLK>; 1096*724ba675SRob Herring }; 1097*724ba675SRob Herring 1098*724ba675SRob Herring ocmemnoc: interconnect@fc470000 { 1099*724ba675SRob Herring reg = <0xfc470000 0x4000>; 1100*724ba675SRob Herring compatible = "qcom,msm8974-ocmemnoc"; 1101*724ba675SRob Herring #interconnect-cells = <1>; 1102*724ba675SRob Herring clock-names = "bus", "bus_a"; 1103*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1104*724ba675SRob Herring <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1105*724ba675SRob Herring }; 1106*724ba675SRob Herring 1107*724ba675SRob Herring mmssnoc: interconnect@fc478000 { 1108*724ba675SRob Herring reg = <0xfc478000 0x4000>; 1109*724ba675SRob Herring compatible = "qcom,msm8974-mmssnoc"; 1110*724ba675SRob Herring #interconnect-cells = <1>; 1111*724ba675SRob Herring clock-names = "bus", "bus_a"; 1112*724ba675SRob Herring clocks = <&mmcc MMSS_S0_AXI_CLK>, 1113*724ba675SRob Herring <&mmcc MMSS_S0_AXI_CLK>; 1114*724ba675SRob Herring }; 1115*724ba675SRob Herring 1116*724ba675SRob Herring cnoc: interconnect@fc480000 { 1117*724ba675SRob Herring reg = <0xfc480000 0x4000>; 1118*724ba675SRob Herring compatible = "qcom,msm8974-cnoc"; 1119*724ba675SRob Herring #interconnect-cells = <1>; 1120*724ba675SRob Herring clock-names = "bus", "bus_a"; 1121*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1122*724ba675SRob Herring <&rpmcc RPM_SMD_CNOC_A_CLK>; 1123*724ba675SRob Herring }; 1124*724ba675SRob Herring 1125*724ba675SRob Herring tsens: thermal-sensor@fc4a9000 { 1126*724ba675SRob Herring compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 1127*724ba675SRob Herring reg = <0xfc4a9000 0x1000>, /* TM */ 1128*724ba675SRob Herring <0xfc4a8000 0x1000>; /* SROT */ 1129*724ba675SRob Herring nvmem-cells = <&tsens_mode>, 1130*724ba675SRob Herring <&tsens_base1>, <&tsens_base2>, 1131*724ba675SRob Herring <&tsens_use_backup>, 1132*724ba675SRob Herring <&tsens_mode_backup>, 1133*724ba675SRob Herring <&tsens_base1_backup>, <&tsens_base2_backup>, 1134*724ba675SRob Herring <&tsens_s0_p1>, <&tsens_s0_p2>, 1135*724ba675SRob Herring <&tsens_s1_p1>, <&tsens_s1_p2>, 1136*724ba675SRob Herring <&tsens_s2_p1>, <&tsens_s2_p2>, 1137*724ba675SRob Herring <&tsens_s3_p1>, <&tsens_s3_p2>, 1138*724ba675SRob Herring <&tsens_s4_p1>, <&tsens_s4_p2>, 1139*724ba675SRob Herring <&tsens_s5_p1>, <&tsens_s5_p2>, 1140*724ba675SRob Herring <&tsens_s6_p1>, <&tsens_s6_p2>, 1141*724ba675SRob Herring <&tsens_s7_p1>, <&tsens_s7_p2>, 1142*724ba675SRob Herring <&tsens_s8_p1>, <&tsens_s8_p2>, 1143*724ba675SRob Herring <&tsens_s9_p1>, <&tsens_s9_p2>, 1144*724ba675SRob Herring <&tsens_s10_p1>, <&tsens_s10_p2>, 1145*724ba675SRob Herring <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 1146*724ba675SRob Herring <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 1147*724ba675SRob Herring <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 1148*724ba675SRob Herring <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 1149*724ba675SRob Herring <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 1150*724ba675SRob Herring <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 1151*724ba675SRob Herring <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 1152*724ba675SRob Herring <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 1153*724ba675SRob Herring <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 1154*724ba675SRob Herring <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 1155*724ba675SRob Herring <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 1156*724ba675SRob Herring nvmem-cell-names = "mode", 1157*724ba675SRob Herring "base1", "base2", 1158*724ba675SRob Herring "use_backup", 1159*724ba675SRob Herring "mode_backup", 1160*724ba675SRob Herring "base1_backup", "base2_backup", 1161*724ba675SRob Herring "s0_p1", "s0_p2", 1162*724ba675SRob Herring "s1_p1", "s1_p2", 1163*724ba675SRob Herring "s2_p1", "s2_p2", 1164*724ba675SRob Herring "s3_p1", "s3_p2", 1165*724ba675SRob Herring "s4_p1", "s4_p2", 1166*724ba675SRob Herring "s5_p1", "s5_p2", 1167*724ba675SRob Herring "s6_p1", "s6_p2", 1168*724ba675SRob Herring "s7_p1", "s7_p2", 1169*724ba675SRob Herring "s8_p1", "s8_p2", 1170*724ba675SRob Herring "s9_p1", "s9_p2", 1171*724ba675SRob Herring "s10_p1", "s10_p2", 1172*724ba675SRob Herring "s0_p1_backup", "s0_p2_backup", 1173*724ba675SRob Herring "s1_p1_backup", "s1_p2_backup", 1174*724ba675SRob Herring "s2_p1_backup", "s2_p2_backup", 1175*724ba675SRob Herring "s3_p1_backup", "s3_p2_backup", 1176*724ba675SRob Herring "s4_p1_backup", "s4_p2_backup", 1177*724ba675SRob Herring "s5_p1_backup", "s5_p2_backup", 1178*724ba675SRob Herring "s6_p1_backup", "s6_p2_backup", 1179*724ba675SRob Herring "s7_p1_backup", "s7_p2_backup", 1180*724ba675SRob Herring "s8_p1_backup", "s8_p2_backup", 1181*724ba675SRob Herring "s9_p1_backup", "s9_p2_backup", 1182*724ba675SRob Herring "s10_p1_backup", "s10_p2_backup"; 1183*724ba675SRob Herring #qcom,sensors = <11>; 1184*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1185*724ba675SRob Herring interrupt-names = "uplow"; 1186*724ba675SRob Herring #thermal-sensor-cells = <1>; 1187*724ba675SRob Herring }; 1188*724ba675SRob Herring 1189*724ba675SRob Herring restart@fc4ab000 { 1190*724ba675SRob Herring compatible = "qcom,pshold"; 1191*724ba675SRob Herring reg = <0xfc4ab000 0x4>; 1192*724ba675SRob Herring }; 1193*724ba675SRob Herring 1194*724ba675SRob Herring qfprom: qfprom@fc4bc000 { 1195*724ba675SRob Herring compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1196*724ba675SRob Herring reg = <0xfc4bc000 0x1000>; 1197*724ba675SRob Herring #address-cells = <1>; 1198*724ba675SRob Herring #size-cells = <1>; 1199*724ba675SRob Herring 1200*724ba675SRob Herring tsens_base1: base1@d0 { 1201*724ba675SRob Herring reg = <0xd0 0x1>; 1202*724ba675SRob Herring bits = <0 8>; 1203*724ba675SRob Herring }; 1204*724ba675SRob Herring 1205*724ba675SRob Herring tsens_s0_p1: s0-p1@d1 { 1206*724ba675SRob Herring reg = <0xd1 0x1>; 1207*724ba675SRob Herring bits = <0 6>; 1208*724ba675SRob Herring }; 1209*724ba675SRob Herring 1210*724ba675SRob Herring tsens_s1_p1: s1-p1@d2 { 1211*724ba675SRob Herring reg = <0xd1 0x2>; 1212*724ba675SRob Herring bits = <6 6>; 1213*724ba675SRob Herring }; 1214*724ba675SRob Herring 1215*724ba675SRob Herring tsens_s2_p1: s2-p1@d2 { 1216*724ba675SRob Herring reg = <0xd2 0x2>; 1217*724ba675SRob Herring bits = <4 6>; 1218*724ba675SRob Herring }; 1219*724ba675SRob Herring 1220*724ba675SRob Herring tsens_s3_p1: s3-p1@d3 { 1221*724ba675SRob Herring reg = <0xd3 0x1>; 1222*724ba675SRob Herring bits = <2 6>; 1223*724ba675SRob Herring }; 1224*724ba675SRob Herring 1225*724ba675SRob Herring tsens_s4_p1: s4-p1@d4 { 1226*724ba675SRob Herring reg = <0xd4 0x1>; 1227*724ba675SRob Herring bits = <0 6>; 1228*724ba675SRob Herring }; 1229*724ba675SRob Herring 1230*724ba675SRob Herring tsens_s5_p1: s5-p1@d4 { 1231*724ba675SRob Herring reg = <0xd4 0x2>; 1232*724ba675SRob Herring bits = <6 6>; 1233*724ba675SRob Herring }; 1234*724ba675SRob Herring 1235*724ba675SRob Herring tsens_s6_p1: s6-p1@d5 { 1236*724ba675SRob Herring reg = <0xd5 0x2>; 1237*724ba675SRob Herring bits = <4 6>; 1238*724ba675SRob Herring }; 1239*724ba675SRob Herring 1240*724ba675SRob Herring tsens_s7_p1: s7-p1@d6 { 1241*724ba675SRob Herring reg = <0xd6 0x1>; 1242*724ba675SRob Herring bits = <2 6>; 1243*724ba675SRob Herring }; 1244*724ba675SRob Herring 1245*724ba675SRob Herring tsens_s8_p1: s8-p1@d7 { 1246*724ba675SRob Herring reg = <0xd7 0x1>; 1247*724ba675SRob Herring bits = <0 6>; 1248*724ba675SRob Herring }; 1249*724ba675SRob Herring 1250*724ba675SRob Herring tsens_mode: mode@d7 { 1251*724ba675SRob Herring reg = <0xd7 0x1>; 1252*724ba675SRob Herring bits = <6 2>; 1253*724ba675SRob Herring }; 1254*724ba675SRob Herring 1255*724ba675SRob Herring tsens_s9_p1: s9-p1@d8 { 1256*724ba675SRob Herring reg = <0xd8 0x1>; 1257*724ba675SRob Herring bits = <0 6>; 1258*724ba675SRob Herring }; 1259*724ba675SRob Herring 1260*724ba675SRob Herring tsens_s10_p1: s10_p1@d8 { 1261*724ba675SRob Herring reg = <0xd8 0x2>; 1262*724ba675SRob Herring bits = <6 6>; 1263*724ba675SRob Herring }; 1264*724ba675SRob Herring 1265*724ba675SRob Herring tsens_base2: base2@d9 { 1266*724ba675SRob Herring reg = <0xd9 0x2>; 1267*724ba675SRob Herring bits = <4 8>; 1268*724ba675SRob Herring }; 1269*724ba675SRob Herring 1270*724ba675SRob Herring tsens_s0_p2: s0-p2@da { 1271*724ba675SRob Herring reg = <0xda 0x2>; 1272*724ba675SRob Herring bits = <4 6>; 1273*724ba675SRob Herring }; 1274*724ba675SRob Herring 1275*724ba675SRob Herring tsens_s1_p2: s1-p2@db { 1276*724ba675SRob Herring reg = <0xdb 0x1>; 1277*724ba675SRob Herring bits = <2 6>; 1278*724ba675SRob Herring }; 1279*724ba675SRob Herring 1280*724ba675SRob Herring tsens_s2_p2: s2-p2@dc { 1281*724ba675SRob Herring reg = <0xdc 0x1>; 1282*724ba675SRob Herring bits = <0 6>; 1283*724ba675SRob Herring }; 1284*724ba675SRob Herring 1285*724ba675SRob Herring tsens_s3_p2: s3-p2@dc { 1286*724ba675SRob Herring reg = <0xdc 0x2>; 1287*724ba675SRob Herring bits = <6 6>; 1288*724ba675SRob Herring }; 1289*724ba675SRob Herring 1290*724ba675SRob Herring tsens_s4_p2: s4-p2@dd { 1291*724ba675SRob Herring reg = <0xdd 0x2>; 1292*724ba675SRob Herring bits = <4 6>; 1293*724ba675SRob Herring }; 1294*724ba675SRob Herring 1295*724ba675SRob Herring tsens_s5_p2: s5-p2@de { 1296*724ba675SRob Herring reg = <0xde 0x2>; 1297*724ba675SRob Herring bits = <2 6>; 1298*724ba675SRob Herring }; 1299*724ba675SRob Herring 1300*724ba675SRob Herring tsens_s6_p2: s6-p2@df { 1301*724ba675SRob Herring reg = <0xdf 0x1>; 1302*724ba675SRob Herring bits = <0 6>; 1303*724ba675SRob Herring }; 1304*724ba675SRob Herring 1305*724ba675SRob Herring tsens_s7_p2: s7-p2@e0 { 1306*724ba675SRob Herring reg = <0xe0 0x1>; 1307*724ba675SRob Herring bits = <0 6>; 1308*724ba675SRob Herring }; 1309*724ba675SRob Herring 1310*724ba675SRob Herring tsens_s8_p2: s8-p2@e0 { 1311*724ba675SRob Herring reg = <0xe0 0x2>; 1312*724ba675SRob Herring bits = <6 6>; 1313*724ba675SRob Herring }; 1314*724ba675SRob Herring 1315*724ba675SRob Herring tsens_s9_p2: s9-p2@e1 { 1316*724ba675SRob Herring reg = <0xe1 0x2>; 1317*724ba675SRob Herring bits = <4 6>; 1318*724ba675SRob Herring }; 1319*724ba675SRob Herring 1320*724ba675SRob Herring tsens_s10_p2: s10_p2@e2 { 1321*724ba675SRob Herring reg = <0xe2 0x2>; 1322*724ba675SRob Herring bits = <2 6>; 1323*724ba675SRob Herring }; 1324*724ba675SRob Herring 1325*724ba675SRob Herring tsens_s5_p2_backup: s5-p2_backup@e3 { 1326*724ba675SRob Herring reg = <0xe3 0x2>; 1327*724ba675SRob Herring bits = <0 6>; 1328*724ba675SRob Herring }; 1329*724ba675SRob Herring 1330*724ba675SRob Herring tsens_mode_backup: mode_backup@e3 { 1331*724ba675SRob Herring reg = <0xe3 0x1>; 1332*724ba675SRob Herring bits = <6 2>; 1333*724ba675SRob Herring }; 1334*724ba675SRob Herring 1335*724ba675SRob Herring tsens_s6_p2_backup: s6-p2_backup@e4 { 1336*724ba675SRob Herring reg = <0xe4 0x1>; 1337*724ba675SRob Herring bits = <0 6>; 1338*724ba675SRob Herring }; 1339*724ba675SRob Herring 1340*724ba675SRob Herring tsens_s7_p2_backup: s7-p2_backup@e4 { 1341*724ba675SRob Herring reg = <0xe4 0x2>; 1342*724ba675SRob Herring bits = <6 6>; 1343*724ba675SRob Herring }; 1344*724ba675SRob Herring 1345*724ba675SRob Herring tsens_s8_p2_backup: s8-p2_backup@e5 { 1346*724ba675SRob Herring reg = <0xe5 0x2>; 1347*724ba675SRob Herring bits = <4 6>; 1348*724ba675SRob Herring }; 1349*724ba675SRob Herring 1350*724ba675SRob Herring tsens_s9_p2_backup: s9-p2_backup@e6 { 1351*724ba675SRob Herring reg = <0xe6 0x2>; 1352*724ba675SRob Herring bits = <2 6>; 1353*724ba675SRob Herring }; 1354*724ba675SRob Herring 1355*724ba675SRob Herring tsens_s10_p2_backup: s10_p2_backup@e7 { 1356*724ba675SRob Herring reg = <0xe7 0x1>; 1357*724ba675SRob Herring bits = <0 6>; 1358*724ba675SRob Herring }; 1359*724ba675SRob Herring 1360*724ba675SRob Herring tsens_base1_backup: base1_backup@440 { 1361*724ba675SRob Herring reg = <0x440 0x1>; 1362*724ba675SRob Herring bits = <0 8>; 1363*724ba675SRob Herring }; 1364*724ba675SRob Herring 1365*724ba675SRob Herring tsens_s0_p1_backup: s0-p1_backup@441 { 1366*724ba675SRob Herring reg = <0x441 0x1>; 1367*724ba675SRob Herring bits = <0 6>; 1368*724ba675SRob Herring }; 1369*724ba675SRob Herring 1370*724ba675SRob Herring tsens_s1_p1_backup: s1-p1_backup@442 { 1371*724ba675SRob Herring reg = <0x441 0x2>; 1372*724ba675SRob Herring bits = <6 6>; 1373*724ba675SRob Herring }; 1374*724ba675SRob Herring 1375*724ba675SRob Herring tsens_s2_p1_backup: s2-p1_backup@442 { 1376*724ba675SRob Herring reg = <0x442 0x2>; 1377*724ba675SRob Herring bits = <4 6>; 1378*724ba675SRob Herring }; 1379*724ba675SRob Herring 1380*724ba675SRob Herring tsens_s3_p1_backup: s3-p1_backup@443 { 1381*724ba675SRob Herring reg = <0x443 0x1>; 1382*724ba675SRob Herring bits = <2 6>; 1383*724ba675SRob Herring }; 1384*724ba675SRob Herring 1385*724ba675SRob Herring tsens_s4_p1_backup: s4-p1_backup@444 { 1386*724ba675SRob Herring reg = <0x444 0x1>; 1387*724ba675SRob Herring bits = <0 6>; 1388*724ba675SRob Herring }; 1389*724ba675SRob Herring 1390*724ba675SRob Herring tsens_s5_p1_backup: s5-p1_backup@444 { 1391*724ba675SRob Herring reg = <0x444 0x2>; 1392*724ba675SRob Herring bits = <6 6>; 1393*724ba675SRob Herring }; 1394*724ba675SRob Herring 1395*724ba675SRob Herring tsens_s6_p1_backup: s6-p1_backup@445 { 1396*724ba675SRob Herring reg = <0x445 0x2>; 1397*724ba675SRob Herring bits = <4 6>; 1398*724ba675SRob Herring }; 1399*724ba675SRob Herring 1400*724ba675SRob Herring tsens_s7_p1_backup: s7-p1_backup@446 { 1401*724ba675SRob Herring reg = <0x446 0x1>; 1402*724ba675SRob Herring bits = <2 6>; 1403*724ba675SRob Herring }; 1404*724ba675SRob Herring 1405*724ba675SRob Herring tsens_use_backup: use_backup@447 { 1406*724ba675SRob Herring reg = <0x447 0x1>; 1407*724ba675SRob Herring bits = <5 3>; 1408*724ba675SRob Herring }; 1409*724ba675SRob Herring 1410*724ba675SRob Herring tsens_s8_p1_backup: s8-p1_backup@448 { 1411*724ba675SRob Herring reg = <0x448 0x1>; 1412*724ba675SRob Herring bits = <0 6>; 1413*724ba675SRob Herring }; 1414*724ba675SRob Herring 1415*724ba675SRob Herring tsens_s9_p1_backup: s9-p1_backup@448 { 1416*724ba675SRob Herring reg = <0x448 0x2>; 1417*724ba675SRob Herring bits = <6 6>; 1418*724ba675SRob Herring }; 1419*724ba675SRob Herring 1420*724ba675SRob Herring tsens_s10_p1_backup: s10_p1_backup@449 { 1421*724ba675SRob Herring reg = <0x449 0x2>; 1422*724ba675SRob Herring bits = <4 6>; 1423*724ba675SRob Herring }; 1424*724ba675SRob Herring 1425*724ba675SRob Herring tsens_base2_backup: base2_backup@44a { 1426*724ba675SRob Herring reg = <0x44a 0x2>; 1427*724ba675SRob Herring bits = <2 8>; 1428*724ba675SRob Herring }; 1429*724ba675SRob Herring 1430*724ba675SRob Herring tsens_s0_p2_backup: s0-p2_backup@44b { 1431*724ba675SRob Herring reg = <0x44b 0x3>; 1432*724ba675SRob Herring bits = <2 6>; 1433*724ba675SRob Herring }; 1434*724ba675SRob Herring 1435*724ba675SRob Herring tsens_s1_p2_backup: s1-p2_backup@44c { 1436*724ba675SRob Herring reg = <0x44c 0x1>; 1437*724ba675SRob Herring bits = <0 6>; 1438*724ba675SRob Herring }; 1439*724ba675SRob Herring 1440*724ba675SRob Herring tsens_s2_p2_backup: s2-p2_backup@44c { 1441*724ba675SRob Herring reg = <0x44c 0x2>; 1442*724ba675SRob Herring bits = <6 6>; 1443*724ba675SRob Herring }; 1444*724ba675SRob Herring 1445*724ba675SRob Herring tsens_s3_p2_backup: s3-p2_backup@44d { 1446*724ba675SRob Herring reg = <0x44d 0x2>; 1447*724ba675SRob Herring bits = <4 6>; 1448*724ba675SRob Herring }; 1449*724ba675SRob Herring 1450*724ba675SRob Herring tsens_s4_p2_backup: s4-p2_backup@44e { 1451*724ba675SRob Herring reg = <0x44e 0x1>; 1452*724ba675SRob Herring bits = <2 6>; 1453*724ba675SRob Herring }; 1454*724ba675SRob Herring }; 1455*724ba675SRob Herring 1456*724ba675SRob Herring spmi_bus: spmi@fc4cf000 { 1457*724ba675SRob Herring compatible = "qcom,spmi-pmic-arb"; 1458*724ba675SRob Herring reg-names = "core", "intr", "cnfg"; 1459*724ba675SRob Herring reg = <0xfc4cf000 0x1000>, 1460*724ba675SRob Herring <0xfc4cb000 0x1000>, 1461*724ba675SRob Herring <0xfc4ca000 0x1000>; 1462*724ba675SRob Herring interrupt-names = "periph_irq"; 1463*724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1464*724ba675SRob Herring qcom,ee = <0>; 1465*724ba675SRob Herring qcom,channel = <0>; 1466*724ba675SRob Herring #address-cells = <2>; 1467*724ba675SRob Herring #size-cells = <0>; 1468*724ba675SRob Herring interrupt-controller; 1469*724ba675SRob Herring #interrupt-cells = <4>; 1470*724ba675SRob Herring }; 1471*724ba675SRob Herring 1472*724ba675SRob Herring bam_dmux_dma: dma-controller@fc834000 { 1473*724ba675SRob Herring compatible = "qcom,bam-v1.4.0"; 1474*724ba675SRob Herring reg = <0xfc834000 0x7000>; 1475*724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1476*724ba675SRob Herring #dma-cells = <1>; 1477*724ba675SRob Herring qcom,ee = <0>; 1478*724ba675SRob Herring 1479*724ba675SRob Herring num-channels = <6>; 1480*724ba675SRob Herring qcom,num-ees = <1>; 1481*724ba675SRob Herring qcom,powered-remotely; 1482*724ba675SRob Herring }; 1483*724ba675SRob Herring 1484*724ba675SRob Herring remoteproc_mss: remoteproc@fc880000 { 1485*724ba675SRob Herring compatible = "qcom,msm8974-mss-pil"; 1486*724ba675SRob Herring reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1487*724ba675SRob Herring reg-names = "qdsp6", "rmb"; 1488*724ba675SRob Herring 1489*724ba675SRob Herring interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1490*724ba675SRob Herring <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1491*724ba675SRob Herring <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1492*724ba675SRob Herring <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1493*724ba675SRob Herring <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1494*724ba675SRob Herring interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1495*724ba675SRob Herring 1496*724ba675SRob Herring clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1497*724ba675SRob Herring <&gcc GCC_MSS_CFG_AHB_CLK>, 1498*724ba675SRob Herring <&gcc GCC_BOOT_ROM_AHB_CLK>, 1499*724ba675SRob Herring <&xo_board>; 1500*724ba675SRob Herring clock-names = "iface", "bus", "mem", "xo"; 1501*724ba675SRob Herring 1502*724ba675SRob Herring resets = <&gcc GCC_MSS_RESTART>; 1503*724ba675SRob Herring reset-names = "mss_restart"; 1504*724ba675SRob Herring 1505*724ba675SRob Herring qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; 1506*724ba675SRob Herring 1507*724ba675SRob Herring qcom,smem-states = <&modem_smp2p_out 0>; 1508*724ba675SRob Herring qcom,smem-state-names = "stop"; 1509*724ba675SRob Herring 1510*724ba675SRob Herring status = "disabled"; 1511*724ba675SRob Herring 1512*724ba675SRob Herring mba { 1513*724ba675SRob Herring memory-region = <&mba_region>; 1514*724ba675SRob Herring }; 1515*724ba675SRob Herring 1516*724ba675SRob Herring mpss { 1517*724ba675SRob Herring memory-region = <&mpss_region>; 1518*724ba675SRob Herring }; 1519*724ba675SRob Herring 1520*724ba675SRob Herring bam_dmux: bam-dmux { 1521*724ba675SRob Herring compatible = "qcom,bam-dmux"; 1522*724ba675SRob Herring 1523*724ba675SRob Herring interrupt-parent = <&modem_smsm>; 1524*724ba675SRob Herring interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1525*724ba675SRob Herring interrupt-names = "pc", "pc-ack"; 1526*724ba675SRob Herring 1527*724ba675SRob Herring qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1528*724ba675SRob Herring qcom,smem-state-names = "pc", "pc-ack"; 1529*724ba675SRob Herring 1530*724ba675SRob Herring dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1531*724ba675SRob Herring dma-names = "tx", "rx"; 1532*724ba675SRob Herring }; 1533*724ba675SRob Herring 1534*724ba675SRob Herring smd-edge { 1535*724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1536*724ba675SRob Herring 1537*724ba675SRob Herring qcom,ipc = <&apcs 8 12>; 1538*724ba675SRob Herring qcom,smd-edge = <0>; 1539*724ba675SRob Herring 1540*724ba675SRob Herring label = "modem"; 1541*724ba675SRob Herring }; 1542*724ba675SRob Herring }; 1543*724ba675SRob Herring 1544*724ba675SRob Herring tcsr_mutex: hwlock@fd484000 { 1545*724ba675SRob Herring compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; 1546*724ba675SRob Herring reg = <0xfd484000 0x2000>; 1547*724ba675SRob Herring #hwlock-cells = <1>; 1548*724ba675SRob Herring }; 1549*724ba675SRob Herring 1550*724ba675SRob Herring tcsr: syscon@fd4a0000 { 1551*724ba675SRob Herring compatible = "qcom,tcsr-msm8974", "syscon"; 1552*724ba675SRob Herring reg = <0xfd4a0000 0x10000>; 1553*724ba675SRob Herring }; 1554*724ba675SRob Herring 1555*724ba675SRob Herring tlmm: pinctrl@fd510000 { 1556*724ba675SRob Herring compatible = "qcom,msm8974-pinctrl"; 1557*724ba675SRob Herring reg = <0xfd510000 0x4000>; 1558*724ba675SRob Herring gpio-controller; 1559*724ba675SRob Herring gpio-ranges = <&tlmm 0 0 146>; 1560*724ba675SRob Herring #gpio-cells = <2>; 1561*724ba675SRob Herring interrupt-controller; 1562*724ba675SRob Herring #interrupt-cells = <2>; 1563*724ba675SRob Herring interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1564*724ba675SRob Herring 1565*724ba675SRob Herring sdc1_off: sdc1-off-state { 1566*724ba675SRob Herring clk-pins { 1567*724ba675SRob Herring pins = "sdc1_clk"; 1568*724ba675SRob Herring bias-disable; 1569*724ba675SRob Herring drive-strength = <2>; 1570*724ba675SRob Herring }; 1571*724ba675SRob Herring 1572*724ba675SRob Herring cmd-pins { 1573*724ba675SRob Herring pins = "sdc1_cmd"; 1574*724ba675SRob Herring bias-pull-up; 1575*724ba675SRob Herring drive-strength = <2>; 1576*724ba675SRob Herring }; 1577*724ba675SRob Herring 1578*724ba675SRob Herring data-pins { 1579*724ba675SRob Herring pins = "sdc1_data"; 1580*724ba675SRob Herring bias-pull-up; 1581*724ba675SRob Herring drive-strength = <2>; 1582*724ba675SRob Herring }; 1583*724ba675SRob Herring }; 1584*724ba675SRob Herring 1585*724ba675SRob Herring sdc2_off: sdc2-off-state { 1586*724ba675SRob Herring clk-pins { 1587*724ba675SRob Herring pins = "sdc2_clk"; 1588*724ba675SRob Herring bias-disable; 1589*724ba675SRob Herring drive-strength = <2>; 1590*724ba675SRob Herring }; 1591*724ba675SRob Herring 1592*724ba675SRob Herring cmd-pins { 1593*724ba675SRob Herring pins = "sdc2_cmd"; 1594*724ba675SRob Herring bias-pull-up; 1595*724ba675SRob Herring drive-strength = <2>; 1596*724ba675SRob Herring }; 1597*724ba675SRob Herring 1598*724ba675SRob Herring data-pins { 1599*724ba675SRob Herring pins = "sdc2_data"; 1600*724ba675SRob Herring bias-pull-up; 1601*724ba675SRob Herring drive-strength = <2>; 1602*724ba675SRob Herring }; 1603*724ba675SRob Herring 1604*724ba675SRob Herring cd-pins { 1605*724ba675SRob Herring pins = "gpio54"; 1606*724ba675SRob Herring function = "gpio"; 1607*724ba675SRob Herring bias-disable; 1608*724ba675SRob Herring drive-strength = <2>; 1609*724ba675SRob Herring }; 1610*724ba675SRob Herring }; 1611*724ba675SRob Herring 1612*724ba675SRob Herring blsp1_uart2_default: blsp1-uart2-default-state { 1613*724ba675SRob Herring rx-pins { 1614*724ba675SRob Herring pins = "gpio5"; 1615*724ba675SRob Herring function = "blsp_uart2"; 1616*724ba675SRob Herring drive-strength = <2>; 1617*724ba675SRob Herring bias-pull-up; 1618*724ba675SRob Herring }; 1619*724ba675SRob Herring 1620*724ba675SRob Herring tx-pins { 1621*724ba675SRob Herring pins = "gpio4"; 1622*724ba675SRob Herring function = "blsp_uart2"; 1623*724ba675SRob Herring drive-strength = <4>; 1624*724ba675SRob Herring bias-disable; 1625*724ba675SRob Herring }; 1626*724ba675SRob Herring }; 1627*724ba675SRob Herring 1628*724ba675SRob Herring blsp2_uart1_default: blsp2-uart1-default-state { 1629*724ba675SRob Herring tx-rts-pins { 1630*724ba675SRob Herring pins = "gpio41", "gpio44"; 1631*724ba675SRob Herring function = "blsp_uart7"; 1632*724ba675SRob Herring drive-strength = <2>; 1633*724ba675SRob Herring bias-disable; 1634*724ba675SRob Herring }; 1635*724ba675SRob Herring 1636*724ba675SRob Herring rx-cts-pins { 1637*724ba675SRob Herring pins = "gpio42", "gpio43"; 1638*724ba675SRob Herring function = "blsp_uart7"; 1639*724ba675SRob Herring drive-strength = <2>; 1640*724ba675SRob Herring bias-pull-up; 1641*724ba675SRob Herring }; 1642*724ba675SRob Herring }; 1643*724ba675SRob Herring 1644*724ba675SRob Herring blsp2_uart1_sleep: blsp2-uart1-sleep-state { 1645*724ba675SRob Herring pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1646*724ba675SRob Herring function = "gpio"; 1647*724ba675SRob Herring drive-strength = <2>; 1648*724ba675SRob Herring bias-pull-down; 1649*724ba675SRob Herring }; 1650*724ba675SRob Herring 1651*724ba675SRob Herring blsp2_uart4_default: blsp2-uart4-default-state { 1652*724ba675SRob Herring tx-rts-pins { 1653*724ba675SRob Herring pins = "gpio53", "gpio56"; 1654*724ba675SRob Herring function = "blsp_uart10"; 1655*724ba675SRob Herring drive-strength = <2>; 1656*724ba675SRob Herring bias-disable; 1657*724ba675SRob Herring }; 1658*724ba675SRob Herring 1659*724ba675SRob Herring rx-cts-pins { 1660*724ba675SRob Herring pins = "gpio54", "gpio55"; 1661*724ba675SRob Herring function = "blsp_uart10"; 1662*724ba675SRob Herring drive-strength = <2>; 1663*724ba675SRob Herring bias-pull-up; 1664*724ba675SRob Herring }; 1665*724ba675SRob Herring }; 1666*724ba675SRob Herring 1667*724ba675SRob Herring blsp1_i2c1_default: blsp1-i2c1-default-state { 1668*724ba675SRob Herring pins = "gpio2", "gpio3"; 1669*724ba675SRob Herring function = "blsp_i2c1"; 1670*724ba675SRob Herring drive-strength = <2>; 1671*724ba675SRob Herring bias-disable; 1672*724ba675SRob Herring }; 1673*724ba675SRob Herring 1674*724ba675SRob Herring blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { 1675*724ba675SRob Herring pins = "gpio2", "gpio3"; 1676*724ba675SRob Herring function = "blsp_i2c1"; 1677*724ba675SRob Herring drive-strength = <2>; 1678*724ba675SRob Herring bias-pull-up; 1679*724ba675SRob Herring }; 1680*724ba675SRob Herring 1681*724ba675SRob Herring blsp1_i2c2_default: blsp1-i2c2-default-state { 1682*724ba675SRob Herring pins = "gpio6", "gpio7"; 1683*724ba675SRob Herring function = "blsp_i2c2"; 1684*724ba675SRob Herring drive-strength = <2>; 1685*724ba675SRob Herring bias-disable; 1686*724ba675SRob Herring }; 1687*724ba675SRob Herring 1688*724ba675SRob Herring blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 1689*724ba675SRob Herring pins = "gpio6", "gpio7"; 1690*724ba675SRob Herring function = "blsp_i2c2"; 1691*724ba675SRob Herring drive-strength = <2>; 1692*724ba675SRob Herring bias-pull-up; 1693*724ba675SRob Herring }; 1694*724ba675SRob Herring 1695*724ba675SRob Herring blsp1_i2c3_default: blsp1-i2c3-default-state { 1696*724ba675SRob Herring pins = "gpio10", "gpio11"; 1697*724ba675SRob Herring function = "blsp_i2c3"; 1698*724ba675SRob Herring drive-strength = <2>; 1699*724ba675SRob Herring bias-disable; 1700*724ba675SRob Herring }; 1701*724ba675SRob Herring 1702*724ba675SRob Herring blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1703*724ba675SRob Herring pins = "gpio10", "gpio11"; 1704*724ba675SRob Herring function = "blsp_i2c3"; 1705*724ba675SRob Herring drive-strength = <2>; 1706*724ba675SRob Herring bias-pull-up; 1707*724ba675SRob Herring }; 1708*724ba675SRob Herring 1709*724ba675SRob Herring /* BLSP1_I2C4 info is missing */ 1710*724ba675SRob Herring 1711*724ba675SRob Herring /* BLSP1_I2C5 info is missing */ 1712*724ba675SRob Herring 1713*724ba675SRob Herring blsp1_i2c6_default: blsp1-i2c6-default-state { 1714*724ba675SRob Herring pins = "gpio29", "gpio30"; 1715*724ba675SRob Herring function = "blsp_i2c6"; 1716*724ba675SRob Herring drive-strength = <2>; 1717*724ba675SRob Herring bias-disable; 1718*724ba675SRob Herring }; 1719*724ba675SRob Herring 1720*724ba675SRob Herring blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1721*724ba675SRob Herring pins = "gpio29", "gpio30"; 1722*724ba675SRob Herring function = "blsp_i2c6"; 1723*724ba675SRob Herring drive-strength = <2>; 1724*724ba675SRob Herring bias-pull-up; 1725*724ba675SRob Herring }; 1726*724ba675SRob Herring /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1727*724ba675SRob Herring 1728*724ba675SRob Herring /* BLSP2_I2C1 info is missing */ 1729*724ba675SRob Herring 1730*724ba675SRob Herring blsp2_i2c2_default: blsp2-i2c2-default-state { 1731*724ba675SRob Herring pins = "gpio47", "gpio48"; 1732*724ba675SRob Herring function = "blsp_i2c8"; 1733*724ba675SRob Herring drive-strength = <2>; 1734*724ba675SRob Herring bias-disable; 1735*724ba675SRob Herring }; 1736*724ba675SRob Herring 1737*724ba675SRob Herring blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1738*724ba675SRob Herring pins = "gpio47", "gpio48"; 1739*724ba675SRob Herring function = "blsp_i2c8"; 1740*724ba675SRob Herring drive-strength = <2>; 1741*724ba675SRob Herring bias-pull-up; 1742*724ba675SRob Herring }; 1743*724ba675SRob Herring 1744*724ba675SRob Herring /* BLSP2_I2C3 info is missing */ 1745*724ba675SRob Herring 1746*724ba675SRob Herring /* BLSP2_I2C4 info is missing */ 1747*724ba675SRob Herring 1748*724ba675SRob Herring blsp2_i2c5_default: blsp2-i2c5-default-state { 1749*724ba675SRob Herring pins = "gpio83", "gpio84"; 1750*724ba675SRob Herring function = "blsp_i2c11"; 1751*724ba675SRob Herring drive-strength = <2>; 1752*724ba675SRob Herring bias-disable; 1753*724ba675SRob Herring }; 1754*724ba675SRob Herring 1755*724ba675SRob Herring blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1756*724ba675SRob Herring pins = "gpio83", "gpio84"; 1757*724ba675SRob Herring function = "blsp_i2c11"; 1758*724ba675SRob Herring drive-strength = <2>; 1759*724ba675SRob Herring bias-pull-up; 1760*724ba675SRob Herring }; 1761*724ba675SRob Herring 1762*724ba675SRob Herring blsp2_i2c6_default: blsp2-i2c6-default-state { 1763*724ba675SRob Herring pins = "gpio87", "gpio88"; 1764*724ba675SRob Herring function = "blsp_i2c12"; 1765*724ba675SRob Herring drive-strength = <2>; 1766*724ba675SRob Herring bias-disable; 1767*724ba675SRob Herring }; 1768*724ba675SRob Herring 1769*724ba675SRob Herring blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1770*724ba675SRob Herring pins = "gpio87", "gpio88"; 1771*724ba675SRob Herring function = "blsp_i2c12"; 1772*724ba675SRob Herring drive-strength = <2>; 1773*724ba675SRob Herring bias-pull-up; 1774*724ba675SRob Herring }; 1775*724ba675SRob Herring 1776*724ba675SRob Herring cci_default: cci-default-state { 1777*724ba675SRob Herring cci_i2c0_default: cci-i2c0-default-pins { 1778*724ba675SRob Herring pins = "gpio19", "gpio20"; 1779*724ba675SRob Herring function = "cci_i2c0"; 1780*724ba675SRob Herring drive-strength = <2>; 1781*724ba675SRob Herring bias-disable; 1782*724ba675SRob Herring }; 1783*724ba675SRob Herring 1784*724ba675SRob Herring cci_i2c1_default: cci-i2c1-default-pins { 1785*724ba675SRob Herring pins = "gpio21", "gpio22"; 1786*724ba675SRob Herring function = "cci_i2c1"; 1787*724ba675SRob Herring drive-strength = <2>; 1788*724ba675SRob Herring bias-disable; 1789*724ba675SRob Herring }; 1790*724ba675SRob Herring }; 1791*724ba675SRob Herring 1792*724ba675SRob Herring cci_sleep: cci-sleep-state { 1793*724ba675SRob Herring cci_i2c0_sleep: cci-i2c0-sleep-pins { 1794*724ba675SRob Herring pins = "gpio19", "gpio20"; 1795*724ba675SRob Herring function = "gpio"; 1796*724ba675SRob Herring drive-strength = <2>; 1797*724ba675SRob Herring bias-disable; 1798*724ba675SRob Herring }; 1799*724ba675SRob Herring 1800*724ba675SRob Herring cci_i2c1_sleep: cci-i2c1-sleep-pins { 1801*724ba675SRob Herring pins = "gpio21", "gpio22"; 1802*724ba675SRob Herring function = "gpio"; 1803*724ba675SRob Herring drive-strength = <2>; 1804*724ba675SRob Herring bias-disable; 1805*724ba675SRob Herring }; 1806*724ba675SRob Herring }; 1807*724ba675SRob Herring 1808*724ba675SRob Herring spi8_default: spi8_default-state { 1809*724ba675SRob Herring mosi-pins { 1810*724ba675SRob Herring pins = "gpio45"; 1811*724ba675SRob Herring function = "blsp_spi8"; 1812*724ba675SRob Herring }; 1813*724ba675SRob Herring miso-pins { 1814*724ba675SRob Herring pins = "gpio46"; 1815*724ba675SRob Herring function = "blsp_spi8"; 1816*724ba675SRob Herring }; 1817*724ba675SRob Herring cs-pins { 1818*724ba675SRob Herring pins = "gpio47"; 1819*724ba675SRob Herring function = "blsp_spi8"; 1820*724ba675SRob Herring }; 1821*724ba675SRob Herring clk-pins { 1822*724ba675SRob Herring pins = "gpio48"; 1823*724ba675SRob Herring function = "blsp_spi8"; 1824*724ba675SRob Herring }; 1825*724ba675SRob Herring }; 1826*724ba675SRob Herring }; 1827*724ba675SRob Herring 1828*724ba675SRob Herring mmcc: clock-controller@fd8c0000 { 1829*724ba675SRob Herring compatible = "qcom,mmcc-msm8974"; 1830*724ba675SRob Herring #clock-cells = <1>; 1831*724ba675SRob Herring #reset-cells = <1>; 1832*724ba675SRob Herring #power-domain-cells = <1>; 1833*724ba675SRob Herring reg = <0xfd8c0000 0x6000>; 1834*724ba675SRob Herring clocks = <&xo_board>, 1835*724ba675SRob Herring <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1836*724ba675SRob Herring <&gcc GPLL0_VOTE>, 1837*724ba675SRob Herring <&gcc GPLL1_VOTE>, 1838*724ba675SRob Herring <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1839*724ba675SRob Herring <&mdss_dsi0_phy 1>, 1840*724ba675SRob Herring <&mdss_dsi0_phy 0>, 1841*724ba675SRob Herring <&mdss_dsi1_phy 1>, 1842*724ba675SRob Herring <&mdss_dsi1_phy 0>, 1843*724ba675SRob Herring <0>, 1844*724ba675SRob Herring <0>, 1845*724ba675SRob Herring <0>; 1846*724ba675SRob Herring clock-names = "xo", 1847*724ba675SRob Herring "mmss_gpll0_vote", 1848*724ba675SRob Herring "gpll0_vote", 1849*724ba675SRob Herring "gpll1_vote", 1850*724ba675SRob Herring "gfx3d_clk_src", 1851*724ba675SRob Herring "dsi0pll", 1852*724ba675SRob Herring "dsi0pllbyte", 1853*724ba675SRob Herring "dsi1pll", 1854*724ba675SRob Herring "dsi1pllbyte", 1855*724ba675SRob Herring "hdmipll", 1856*724ba675SRob Herring "edp_link_clk", 1857*724ba675SRob Herring "edp_vco_div"; 1858*724ba675SRob Herring }; 1859*724ba675SRob Herring 1860*724ba675SRob Herring mdss: display-subsystem@fd900000 { 1861*724ba675SRob Herring compatible = "qcom,mdss"; 1862*724ba675SRob Herring reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1863*724ba675SRob Herring reg-names = "mdss_phys", "vbif_phys"; 1864*724ba675SRob Herring 1865*724ba675SRob Herring power-domains = <&mmcc MDSS_GDSC>; 1866*724ba675SRob Herring 1867*724ba675SRob Herring clocks = <&mmcc MDSS_AHB_CLK>, 1868*724ba675SRob Herring <&mmcc MDSS_AXI_CLK>, 1869*724ba675SRob Herring <&mmcc MDSS_VSYNC_CLK>; 1870*724ba675SRob Herring clock-names = "iface", "bus", "vsync"; 1871*724ba675SRob Herring 1872*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1873*724ba675SRob Herring 1874*724ba675SRob Herring interrupt-controller; 1875*724ba675SRob Herring #interrupt-cells = <1>; 1876*724ba675SRob Herring 1877*724ba675SRob Herring status = "disabled"; 1878*724ba675SRob Herring 1879*724ba675SRob Herring #address-cells = <1>; 1880*724ba675SRob Herring #size-cells = <1>; 1881*724ba675SRob Herring ranges; 1882*724ba675SRob Herring 1883*724ba675SRob Herring mdp: display-controller@fd900000 { 1884*724ba675SRob Herring compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; 1885*724ba675SRob Herring reg = <0xfd900100 0x22000>; 1886*724ba675SRob Herring reg-names = "mdp_phys"; 1887*724ba675SRob Herring 1888*724ba675SRob Herring interrupt-parent = <&mdss>; 1889*724ba675SRob Herring interrupts = <0>; 1890*724ba675SRob Herring 1891*724ba675SRob Herring clocks = <&mmcc MDSS_AHB_CLK>, 1892*724ba675SRob Herring <&mmcc MDSS_AXI_CLK>, 1893*724ba675SRob Herring <&mmcc MDSS_MDP_CLK>, 1894*724ba675SRob Herring <&mmcc MDSS_VSYNC_CLK>; 1895*724ba675SRob Herring clock-names = "iface", "bus", "core", "vsync"; 1896*724ba675SRob Herring 1897*724ba675SRob Herring interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1898*724ba675SRob Herring interconnect-names = "mdp0-mem"; 1899*724ba675SRob Herring 1900*724ba675SRob Herring ports { 1901*724ba675SRob Herring #address-cells = <1>; 1902*724ba675SRob Herring #size-cells = <0>; 1903*724ba675SRob Herring 1904*724ba675SRob Herring port@0 { 1905*724ba675SRob Herring reg = <0>; 1906*724ba675SRob Herring mdp5_intf1_out: endpoint { 1907*724ba675SRob Herring remote-endpoint = <&mdss_dsi0_in>; 1908*724ba675SRob Herring }; 1909*724ba675SRob Herring }; 1910*724ba675SRob Herring 1911*724ba675SRob Herring port@1 { 1912*724ba675SRob Herring reg = <1>; 1913*724ba675SRob Herring mdp5_intf2_out: endpoint { 1914*724ba675SRob Herring remote-endpoint = <&mdss_dsi1_in>; 1915*724ba675SRob Herring }; 1916*724ba675SRob Herring }; 1917*724ba675SRob Herring }; 1918*724ba675SRob Herring }; 1919*724ba675SRob Herring 1920*724ba675SRob Herring mdss_dsi0: dsi@fd922800 { 1921*724ba675SRob Herring compatible = "qcom,msm8974-dsi-ctrl", 1922*724ba675SRob Herring "qcom,mdss-dsi-ctrl"; 1923*724ba675SRob Herring reg = <0xfd922800 0x1f8>; 1924*724ba675SRob Herring reg-names = "dsi_ctrl"; 1925*724ba675SRob Herring 1926*724ba675SRob Herring interrupt-parent = <&mdss>; 1927*724ba675SRob Herring interrupts = <4>; 1928*724ba675SRob Herring 1929*724ba675SRob Herring assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1930*724ba675SRob Herring assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1931*724ba675SRob Herring 1932*724ba675SRob Herring clocks = <&mmcc MDSS_MDP_CLK>, 1933*724ba675SRob Herring <&mmcc MDSS_AHB_CLK>, 1934*724ba675SRob Herring <&mmcc MDSS_AXI_CLK>, 1935*724ba675SRob Herring <&mmcc MDSS_BYTE0_CLK>, 1936*724ba675SRob Herring <&mmcc MDSS_PCLK0_CLK>, 1937*724ba675SRob Herring <&mmcc MDSS_ESC0_CLK>, 1938*724ba675SRob Herring <&mmcc MMSS_MISC_AHB_CLK>; 1939*724ba675SRob Herring clock-names = "mdp_core", 1940*724ba675SRob Herring "iface", 1941*724ba675SRob Herring "bus", 1942*724ba675SRob Herring "byte", 1943*724ba675SRob Herring "pixel", 1944*724ba675SRob Herring "core", 1945*724ba675SRob Herring "core_mmss"; 1946*724ba675SRob Herring 1947*724ba675SRob Herring phys = <&mdss_dsi0_phy>; 1948*724ba675SRob Herring 1949*724ba675SRob Herring status = "disabled"; 1950*724ba675SRob Herring 1951*724ba675SRob Herring #address-cells = <1>; 1952*724ba675SRob Herring #size-cells = <0>; 1953*724ba675SRob Herring 1954*724ba675SRob Herring ports { 1955*724ba675SRob Herring #address-cells = <1>; 1956*724ba675SRob Herring #size-cells = <0>; 1957*724ba675SRob Herring 1958*724ba675SRob Herring port@0 { 1959*724ba675SRob Herring reg = <0>; 1960*724ba675SRob Herring mdss_dsi0_in: endpoint { 1961*724ba675SRob Herring remote-endpoint = <&mdp5_intf1_out>; 1962*724ba675SRob Herring }; 1963*724ba675SRob Herring }; 1964*724ba675SRob Herring 1965*724ba675SRob Herring port@1 { 1966*724ba675SRob Herring reg = <1>; 1967*724ba675SRob Herring mdss_dsi0_out: endpoint { 1968*724ba675SRob Herring }; 1969*724ba675SRob Herring }; 1970*724ba675SRob Herring }; 1971*724ba675SRob Herring }; 1972*724ba675SRob Herring 1973*724ba675SRob Herring mdss_dsi0_phy: phy@fd922a00 { 1974*724ba675SRob Herring compatible = "qcom,dsi-phy-28nm-hpm"; 1975*724ba675SRob Herring reg = <0xfd922a00 0xd4>, 1976*724ba675SRob Herring <0xfd922b00 0x280>, 1977*724ba675SRob Herring <0xfd922d80 0x30>; 1978*724ba675SRob Herring reg-names = "dsi_pll", 1979*724ba675SRob Herring "dsi_phy", 1980*724ba675SRob Herring "dsi_phy_regulator"; 1981*724ba675SRob Herring 1982*724ba675SRob Herring #clock-cells = <1>; 1983*724ba675SRob Herring #phy-cells = <0>; 1984*724ba675SRob Herring 1985*724ba675SRob Herring clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1986*724ba675SRob Herring clock-names = "iface", "ref"; 1987*724ba675SRob Herring 1988*724ba675SRob Herring status = "disabled"; 1989*724ba675SRob Herring }; 1990*724ba675SRob Herring 1991*724ba675SRob Herring mdss_dsi1: dsi@fd922e00 { 1992*724ba675SRob Herring compatible = "qcom,msm8974-dsi-ctrl", 1993*724ba675SRob Herring "qcom,mdss-dsi-ctrl"; 1994*724ba675SRob Herring reg = <0xfd922e00 0x1f8>; 1995*724ba675SRob Herring reg-names = "dsi_ctrl"; 1996*724ba675SRob Herring 1997*724ba675SRob Herring interrupt-parent = <&mdss>; 1998*724ba675SRob Herring interrupts = <4>; 1999*724ba675SRob Herring 2000*724ba675SRob Herring assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 2001*724ba675SRob Herring assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2002*724ba675SRob Herring 2003*724ba675SRob Herring clocks = <&mmcc MDSS_MDP_CLK>, 2004*724ba675SRob Herring <&mmcc MDSS_AHB_CLK>, 2005*724ba675SRob Herring <&mmcc MDSS_AXI_CLK>, 2006*724ba675SRob Herring <&mmcc MDSS_BYTE1_CLK>, 2007*724ba675SRob Herring <&mmcc MDSS_PCLK1_CLK>, 2008*724ba675SRob Herring <&mmcc MDSS_ESC1_CLK>, 2009*724ba675SRob Herring <&mmcc MMSS_MISC_AHB_CLK>; 2010*724ba675SRob Herring clock-names = "mdp_core", 2011*724ba675SRob Herring "iface", 2012*724ba675SRob Herring "bus", 2013*724ba675SRob Herring "byte", 2014*724ba675SRob Herring "pixel", 2015*724ba675SRob Herring "core", 2016*724ba675SRob Herring "core_mmss"; 2017*724ba675SRob Herring 2018*724ba675SRob Herring phys = <&mdss_dsi1_phy>; 2019*724ba675SRob Herring 2020*724ba675SRob Herring status = "disabled"; 2021*724ba675SRob Herring 2022*724ba675SRob Herring #address-cells = <1>; 2023*724ba675SRob Herring #size-cells = <0>; 2024*724ba675SRob Herring 2025*724ba675SRob Herring ports { 2026*724ba675SRob Herring #address-cells = <1>; 2027*724ba675SRob Herring #size-cells = <0>; 2028*724ba675SRob Herring 2029*724ba675SRob Herring port@0 { 2030*724ba675SRob Herring reg = <0>; 2031*724ba675SRob Herring mdss_dsi1_in: endpoint { 2032*724ba675SRob Herring remote-endpoint = <&mdp5_intf2_out>; 2033*724ba675SRob Herring }; 2034*724ba675SRob Herring }; 2035*724ba675SRob Herring 2036*724ba675SRob Herring port@1 { 2037*724ba675SRob Herring reg = <1>; 2038*724ba675SRob Herring mdss_dsi1_out: endpoint { 2039*724ba675SRob Herring }; 2040*724ba675SRob Herring }; 2041*724ba675SRob Herring }; 2042*724ba675SRob Herring }; 2043*724ba675SRob Herring 2044*724ba675SRob Herring mdss_dsi1_phy: phy@fd923000 { 2045*724ba675SRob Herring compatible = "qcom,dsi-phy-28nm-hpm"; 2046*724ba675SRob Herring reg = <0xfd923000 0xd4>, 2047*724ba675SRob Herring <0xfd923100 0x280>, 2048*724ba675SRob Herring <0xfd923380 0x30>; 2049*724ba675SRob Herring reg-names = "dsi_pll", 2050*724ba675SRob Herring "dsi_phy", 2051*724ba675SRob Herring "dsi_phy_regulator"; 2052*724ba675SRob Herring 2053*724ba675SRob Herring #clock-cells = <1>; 2054*724ba675SRob Herring #phy-cells = <0>; 2055*724ba675SRob Herring 2056*724ba675SRob Herring clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2057*724ba675SRob Herring clock-names = "iface", "ref"; 2058*724ba675SRob Herring 2059*724ba675SRob Herring status = "disabled"; 2060*724ba675SRob Herring }; 2061*724ba675SRob Herring }; 2062*724ba675SRob Herring 2063*724ba675SRob Herring cci: cci@fda0c000 { 2064*724ba675SRob Herring compatible = "qcom,msm8974-cci"; 2065*724ba675SRob Herring #address-cells = <1>; 2066*724ba675SRob Herring #size-cells = <0>; 2067*724ba675SRob Herring reg = <0xfda0c000 0x1000>; 2068*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 2069*724ba675SRob Herring clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2070*724ba675SRob Herring <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 2071*724ba675SRob Herring <&mmcc CAMSS_CCI_CCI_CLK>; 2072*724ba675SRob Herring clock-names = "camss_top_ahb", 2073*724ba675SRob Herring "cci_ahb", 2074*724ba675SRob Herring "cci"; 2075*724ba675SRob Herring 2076*724ba675SRob Herring pinctrl-names = "default", "sleep"; 2077*724ba675SRob Herring pinctrl-0 = <&cci_default>; 2078*724ba675SRob Herring pinctrl-1 = <&cci_sleep>; 2079*724ba675SRob Herring 2080*724ba675SRob Herring status = "disabled"; 2081*724ba675SRob Herring 2082*724ba675SRob Herring cci_i2c0: i2c-bus@0 { 2083*724ba675SRob Herring reg = <0>; 2084*724ba675SRob Herring clock-frequency = <100000>; 2085*724ba675SRob Herring #address-cells = <1>; 2086*724ba675SRob Herring #size-cells = <0>; 2087*724ba675SRob Herring }; 2088*724ba675SRob Herring 2089*724ba675SRob Herring cci_i2c1: i2c-bus@1 { 2090*724ba675SRob Herring reg = <1>; 2091*724ba675SRob Herring clock-frequency = <100000>; 2092*724ba675SRob Herring #address-cells = <1>; 2093*724ba675SRob Herring #size-cells = <0>; 2094*724ba675SRob Herring }; 2095*724ba675SRob Herring }; 2096*724ba675SRob Herring 2097*724ba675SRob Herring gpu: adreno@fdb00000 { 2098*724ba675SRob Herring compatible = "qcom,adreno-330.1", "qcom,adreno"; 2099*724ba675SRob Herring reg = <0xfdb00000 0x10000>; 2100*724ba675SRob Herring reg-names = "kgsl_3d0_reg_memory"; 2101*724ba675SRob Herring 2102*724ba675SRob Herring interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2103*724ba675SRob Herring interrupt-names = "kgsl_3d0_irq"; 2104*724ba675SRob Herring 2105*724ba675SRob Herring clocks = <&mmcc OXILI_GFX3D_CLK>, 2106*724ba675SRob Herring <&mmcc OXILICX_AHB_CLK>, 2107*724ba675SRob Herring <&mmcc OXILICX_AXI_CLK>; 2108*724ba675SRob Herring clock-names = "core", "iface", "mem_iface"; 2109*724ba675SRob Herring 2110*724ba675SRob Herring sram = <&gmu_sram>; 2111*724ba675SRob Herring power-domains = <&mmcc OXILICX_GDSC>; 2112*724ba675SRob Herring operating-points-v2 = <&gpu_opp_table>; 2113*724ba675SRob Herring 2114*724ba675SRob Herring interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 2115*724ba675SRob Herring <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 2116*724ba675SRob Herring interconnect-names = "gfx-mem", "ocmem"; 2117*724ba675SRob Herring 2118*724ba675SRob Herring // iommus = <&gpu_iommu 0>; 2119*724ba675SRob Herring 2120*724ba675SRob Herring status = "disabled"; 2121*724ba675SRob Herring 2122*724ba675SRob Herring gpu_opp_table: opp-table { 2123*724ba675SRob Herring compatible = "operating-points-v2"; 2124*724ba675SRob Herring 2125*724ba675SRob Herring opp-320000000 { 2126*724ba675SRob Herring opp-hz = /bits/ 64 <320000000>; 2127*724ba675SRob Herring }; 2128*724ba675SRob Herring 2129*724ba675SRob Herring opp-200000000 { 2130*724ba675SRob Herring opp-hz = /bits/ 64 <200000000>; 2131*724ba675SRob Herring }; 2132*724ba675SRob Herring 2133*724ba675SRob Herring opp-27000000 { 2134*724ba675SRob Herring opp-hz = /bits/ 64 <27000000>; 2135*724ba675SRob Herring }; 2136*724ba675SRob Herring }; 2137*724ba675SRob Herring }; 2138*724ba675SRob Herring 2139*724ba675SRob Herring sram@fdd00000 { 2140*724ba675SRob Herring compatible = "qcom,msm8974-ocmem"; 2141*724ba675SRob Herring reg = <0xfdd00000 0x2000>, 2142*724ba675SRob Herring <0xfec00000 0x180000>; 2143*724ba675SRob Herring reg-names = "ctrl", "mem"; 2144*724ba675SRob Herring ranges = <0 0xfec00000 0x180000>; 2145*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 2146*724ba675SRob Herring <&mmcc OCMEMCX_OCMEMNOC_CLK>; 2147*724ba675SRob Herring clock-names = "core", "iface"; 2148*724ba675SRob Herring 2149*724ba675SRob Herring #address-cells = <1>; 2150*724ba675SRob Herring #size-cells = <1>; 2151*724ba675SRob Herring 2152*724ba675SRob Herring gmu_sram: gmu-sram@0 { 2153*724ba675SRob Herring reg = <0x0 0x100000>; 2154*724ba675SRob Herring }; 2155*724ba675SRob Herring }; 2156*724ba675SRob Herring 2157*724ba675SRob Herring remoteproc_adsp: remoteproc@fe200000 { 2158*724ba675SRob Herring compatible = "qcom,msm8974-adsp-pil"; 2159*724ba675SRob Herring reg = <0xfe200000 0x100>; 2160*724ba675SRob Herring 2161*724ba675SRob Herring interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2162*724ba675SRob Herring <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2163*724ba675SRob Herring <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2164*724ba675SRob Herring <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2165*724ba675SRob Herring <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2166*724ba675SRob Herring interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2167*724ba675SRob Herring 2168*724ba675SRob Herring clocks = <&xo_board>; 2169*724ba675SRob Herring clock-names = "xo"; 2170*724ba675SRob Herring 2171*724ba675SRob Herring memory-region = <&adsp_region>; 2172*724ba675SRob Herring 2173*724ba675SRob Herring qcom,smem-states = <&adsp_smp2p_out 0>; 2174*724ba675SRob Herring qcom,smem-state-names = "stop"; 2175*724ba675SRob Herring 2176*724ba675SRob Herring status = "disabled"; 2177*724ba675SRob Herring 2178*724ba675SRob Herring smd-edge { 2179*724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2180*724ba675SRob Herring 2181*724ba675SRob Herring qcom,ipc = <&apcs 8 8>; 2182*724ba675SRob Herring qcom,smd-edge = <1>; 2183*724ba675SRob Herring label = "lpass"; 2184*724ba675SRob Herring }; 2185*724ba675SRob Herring }; 2186*724ba675SRob Herring 2187*724ba675SRob Herring imem: sram@fe805000 { 2188*724ba675SRob Herring compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 2189*724ba675SRob Herring reg = <0xfe805000 0x1000>; 2190*724ba675SRob Herring 2191*724ba675SRob Herring reboot-mode { 2192*724ba675SRob Herring compatible = "syscon-reboot-mode"; 2193*724ba675SRob Herring offset = <0x65c>; 2194*724ba675SRob Herring }; 2195*724ba675SRob Herring }; 2196*724ba675SRob Herring }; 2197*724ba675SRob Herring 2198*724ba675SRob Herring thermal-zones { 2199*724ba675SRob Herring cpu0-thermal { 2200*724ba675SRob Herring polling-delay-passive = <250>; 2201*724ba675SRob Herring polling-delay = <1000>; 2202*724ba675SRob Herring 2203*724ba675SRob Herring thermal-sensors = <&tsens 5>; 2204*724ba675SRob Herring 2205*724ba675SRob Herring trips { 2206*724ba675SRob Herring cpu_alert0: trip0 { 2207*724ba675SRob Herring temperature = <75000>; 2208*724ba675SRob Herring hysteresis = <2000>; 2209*724ba675SRob Herring type = "passive"; 2210*724ba675SRob Herring }; 2211*724ba675SRob Herring cpu_crit0: trip1 { 2212*724ba675SRob Herring temperature = <110000>; 2213*724ba675SRob Herring hysteresis = <2000>; 2214*724ba675SRob Herring type = "critical"; 2215*724ba675SRob Herring }; 2216*724ba675SRob Herring }; 2217*724ba675SRob Herring }; 2218*724ba675SRob Herring 2219*724ba675SRob Herring cpu1-thermal { 2220*724ba675SRob Herring polling-delay-passive = <250>; 2221*724ba675SRob Herring polling-delay = <1000>; 2222*724ba675SRob Herring 2223*724ba675SRob Herring thermal-sensors = <&tsens 6>; 2224*724ba675SRob Herring 2225*724ba675SRob Herring trips { 2226*724ba675SRob Herring cpu_alert1: trip0 { 2227*724ba675SRob Herring temperature = <75000>; 2228*724ba675SRob Herring hysteresis = <2000>; 2229*724ba675SRob Herring type = "passive"; 2230*724ba675SRob Herring }; 2231*724ba675SRob Herring cpu_crit1: trip1 { 2232*724ba675SRob Herring temperature = <110000>; 2233*724ba675SRob Herring hysteresis = <2000>; 2234*724ba675SRob Herring type = "critical"; 2235*724ba675SRob Herring }; 2236*724ba675SRob Herring }; 2237*724ba675SRob Herring }; 2238*724ba675SRob Herring 2239*724ba675SRob Herring cpu2-thermal { 2240*724ba675SRob Herring polling-delay-passive = <250>; 2241*724ba675SRob Herring polling-delay = <1000>; 2242*724ba675SRob Herring 2243*724ba675SRob Herring thermal-sensors = <&tsens 7>; 2244*724ba675SRob Herring 2245*724ba675SRob Herring trips { 2246*724ba675SRob Herring cpu_alert2: trip0 { 2247*724ba675SRob Herring temperature = <75000>; 2248*724ba675SRob Herring hysteresis = <2000>; 2249*724ba675SRob Herring type = "passive"; 2250*724ba675SRob Herring }; 2251*724ba675SRob Herring cpu_crit2: trip1 { 2252*724ba675SRob Herring temperature = <110000>; 2253*724ba675SRob Herring hysteresis = <2000>; 2254*724ba675SRob Herring type = "critical"; 2255*724ba675SRob Herring }; 2256*724ba675SRob Herring }; 2257*724ba675SRob Herring }; 2258*724ba675SRob Herring 2259*724ba675SRob Herring cpu3-thermal { 2260*724ba675SRob Herring polling-delay-passive = <250>; 2261*724ba675SRob Herring polling-delay = <1000>; 2262*724ba675SRob Herring 2263*724ba675SRob Herring thermal-sensors = <&tsens 8>; 2264*724ba675SRob Herring 2265*724ba675SRob Herring trips { 2266*724ba675SRob Herring cpu_alert3: trip0 { 2267*724ba675SRob Herring temperature = <75000>; 2268*724ba675SRob Herring hysteresis = <2000>; 2269*724ba675SRob Herring type = "passive"; 2270*724ba675SRob Herring }; 2271*724ba675SRob Herring cpu_crit3: trip1 { 2272*724ba675SRob Herring temperature = <110000>; 2273*724ba675SRob Herring hysteresis = <2000>; 2274*724ba675SRob Herring type = "critical"; 2275*724ba675SRob Herring }; 2276*724ba675SRob Herring }; 2277*724ba675SRob Herring }; 2278*724ba675SRob Herring 2279*724ba675SRob Herring q6-dsp-thermal { 2280*724ba675SRob Herring polling-delay-passive = <250>; 2281*724ba675SRob Herring polling-delay = <1000>; 2282*724ba675SRob Herring 2283*724ba675SRob Herring thermal-sensors = <&tsens 1>; 2284*724ba675SRob Herring 2285*724ba675SRob Herring trips { 2286*724ba675SRob Herring q6_dsp_alert0: trip-point0 { 2287*724ba675SRob Herring temperature = <90000>; 2288*724ba675SRob Herring hysteresis = <2000>; 2289*724ba675SRob Herring type = "hot"; 2290*724ba675SRob Herring }; 2291*724ba675SRob Herring }; 2292*724ba675SRob Herring }; 2293*724ba675SRob Herring 2294*724ba675SRob Herring modemtx-thermal { 2295*724ba675SRob Herring polling-delay-passive = <250>; 2296*724ba675SRob Herring polling-delay = <1000>; 2297*724ba675SRob Herring 2298*724ba675SRob Herring thermal-sensors = <&tsens 2>; 2299*724ba675SRob Herring 2300*724ba675SRob Herring trips { 2301*724ba675SRob Herring modemtx_alert0: trip-point0 { 2302*724ba675SRob Herring temperature = <90000>; 2303*724ba675SRob Herring hysteresis = <2000>; 2304*724ba675SRob Herring type = "hot"; 2305*724ba675SRob Herring }; 2306*724ba675SRob Herring }; 2307*724ba675SRob Herring }; 2308*724ba675SRob Herring 2309*724ba675SRob Herring video-thermal { 2310*724ba675SRob Herring polling-delay-passive = <250>; 2311*724ba675SRob Herring polling-delay = <1000>; 2312*724ba675SRob Herring 2313*724ba675SRob Herring thermal-sensors = <&tsens 3>; 2314*724ba675SRob Herring 2315*724ba675SRob Herring trips { 2316*724ba675SRob Herring video_alert0: trip-point0 { 2317*724ba675SRob Herring temperature = <95000>; 2318*724ba675SRob Herring hysteresis = <2000>; 2319*724ba675SRob Herring type = "hot"; 2320*724ba675SRob Herring }; 2321*724ba675SRob Herring }; 2322*724ba675SRob Herring }; 2323*724ba675SRob Herring 2324*724ba675SRob Herring wlan-thermal { 2325*724ba675SRob Herring polling-delay-passive = <250>; 2326*724ba675SRob Herring polling-delay = <1000>; 2327*724ba675SRob Herring 2328*724ba675SRob Herring thermal-sensors = <&tsens 4>; 2329*724ba675SRob Herring 2330*724ba675SRob Herring trips { 2331*724ba675SRob Herring wlan_alert0: trip-point0 { 2332*724ba675SRob Herring temperature = <105000>; 2333*724ba675SRob Herring hysteresis = <2000>; 2334*724ba675SRob Herring type = "hot"; 2335*724ba675SRob Herring }; 2336*724ba675SRob Herring }; 2337*724ba675SRob Herring }; 2338*724ba675SRob Herring 2339*724ba675SRob Herring gpu-top-thermal { 2340*724ba675SRob Herring polling-delay-passive = <250>; 2341*724ba675SRob Herring polling-delay = <1000>; 2342*724ba675SRob Herring 2343*724ba675SRob Herring thermal-sensors = <&tsens 9>; 2344*724ba675SRob Herring 2345*724ba675SRob Herring trips { 2346*724ba675SRob Herring gpu1_alert0: trip-point0 { 2347*724ba675SRob Herring temperature = <90000>; 2348*724ba675SRob Herring hysteresis = <2000>; 2349*724ba675SRob Herring type = "hot"; 2350*724ba675SRob Herring }; 2351*724ba675SRob Herring }; 2352*724ba675SRob Herring }; 2353*724ba675SRob Herring 2354*724ba675SRob Herring gpu-bottom-thermal { 2355*724ba675SRob Herring polling-delay-passive = <250>; 2356*724ba675SRob Herring polling-delay = <1000>; 2357*724ba675SRob Herring 2358*724ba675SRob Herring thermal-sensors = <&tsens 10>; 2359*724ba675SRob Herring 2360*724ba675SRob Herring trips { 2361*724ba675SRob Herring gpu2_alert0: trip-point0 { 2362*724ba675SRob Herring temperature = <90000>; 2363*724ba675SRob Herring hysteresis = <2000>; 2364*724ba675SRob Herring type = "hot"; 2365*724ba675SRob Herring }; 2366*724ba675SRob Herring }; 2367*724ba675SRob Herring }; 2368*724ba675SRob Herring }; 2369*724ba675SRob Herring 2370*724ba675SRob Herring timer { 2371*724ba675SRob Herring compatible = "arm,armv7-timer"; 2372*724ba675SRob Herring interrupts = <GIC_PPI 2 0xf08>, 2373*724ba675SRob Herring <GIC_PPI 3 0xf08>, 2374*724ba675SRob Herring <GIC_PPI 4 0xf08>, 2375*724ba675SRob Herring <GIC_PPI 1 0xf08>; 2376*724ba675SRob Herring clock-frequency = <19200000>; 2377*724ba675SRob Herring }; 2378*724ba675SRob Herring 2379*724ba675SRob Herring vreg_boost: vreg-boost { 2380*724ba675SRob Herring compatible = "regulator-fixed"; 2381*724ba675SRob Herring 2382*724ba675SRob Herring regulator-name = "vreg-boost"; 2383*724ba675SRob Herring regulator-min-microvolt = <3150000>; 2384*724ba675SRob Herring regulator-max-microvolt = <3150000>; 2385*724ba675SRob Herring 2386*724ba675SRob Herring regulator-always-on; 2387*724ba675SRob Herring regulator-boot-on; 2388*724ba675SRob Herring 2389*724ba675SRob Herring gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; 2390*724ba675SRob Herring enable-active-high; 2391*724ba675SRob Herring 2392*724ba675SRob Herring pinctrl-names = "default"; 2393*724ba675SRob Herring pinctrl-0 = <&boost_bypass_n_pin>; 2394*724ba675SRob Herring }; 2395*724ba675SRob Herring 2396*724ba675SRob Herring vreg_vph_pwr: vreg-vph-pwr { 2397*724ba675SRob Herring compatible = "regulator-fixed"; 2398*724ba675SRob Herring regulator-name = "vph-pwr"; 2399*724ba675SRob Herring 2400*724ba675SRob Herring regulator-min-microvolt = <3600000>; 2401*724ba675SRob Herring regulator-max-microvolt = <3600000>; 2402*724ba675SRob Herring 2403*724ba675SRob Herring regulator-always-on; 2404*724ba675SRob Herring }; 2405*724ba675SRob Herring}; 2406