1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8660.h> 7#include <dt-bindings/soc/qcom,gsbi.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 model = "Qualcomm MSM8660"; 13 compatible = "qcom,msm8660"; 14 interrupt-parent = <&intc>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "qcom,scorpion"; 22 enable-method = "qcom,gcc-msm8660"; 23 device_type = "cpu"; 24 reg = <0>; 25 next-level-cache = <&L2>; 26 }; 27 28 cpu@1 { 29 compatible = "qcom,scorpion"; 30 enable-method = "qcom,gcc-msm8660"; 31 device_type = "cpu"; 32 reg = <1>; 33 next-level-cache = <&L2>; 34 }; 35 36 L2: l2-cache { 37 compatible = "cache"; 38 cache-level = <2>; 39 cache-unified; 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x0 0x0>; 46 }; 47 48 cpu-pmu { 49 compatible = "qcom,scorpion-mp-pmu"; 50 interrupts = <1 9 0x304>; 51 }; 52 53 clocks { 54 cxo_board: cxo-board-clk { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <19200000>; 58 clock-output-names = "cxo_board"; 59 }; 60 61 pxo_board: pxo-board-clk { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <27000000>; 65 clock-output-names = "pxo_board"; 66 }; 67 68 sleep-clk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <32768>; 72 clock-output-names = "sleep_clk"; 73 }; 74 }; 75 76 soc: soc { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges; 80 compatible = "simple-bus"; 81 82 intc: interrupt-controller@2080000 { 83 compatible = "qcom,msm-8660-qgic"; 84 interrupt-controller; 85 #interrupt-cells = <3>; 86 reg = < 0x02080000 0x1000 >, 87 < 0x02081000 0x1000 >; 88 }; 89 90 timer@2000000 { 91 compatible = "qcom,scss-timer", "qcom,msm-timer"; 92 interrupts = <1 0 0x301>, 93 <1 1 0x301>, 94 <1 2 0x301>; 95 reg = <0x02000000 0x100>; 96 clock-frequency = <27000000>, 97 <32768>; 98 cpu-offset = <0x40000>; 99 }; 100 101 tlmm: pinctrl@800000 { 102 compatible = "qcom,msm8660-pinctrl"; 103 reg = <0x800000 0x4000>; 104 105 gpio-controller; 106 gpio-ranges = <&tlmm 0 0 173>; 107 #gpio-cells = <2>; 108 interrupts = <0 16 0x4>; 109 interrupt-controller; 110 #interrupt-cells = <2>; 111 112 }; 113 114 gcc: clock-controller@900000 { 115 compatible = "qcom,gcc-msm8660"; 116 #clock-cells = <1>; 117 #power-domain-cells = <1>; 118 #reset-cells = <1>; 119 reg = <0x900000 0x4000>; 120 clocks = <&pxo_board>, <&cxo_board>; 121 clock-names = "pxo", "cxo"; 122 }; 123 124 gsbi1: gsbi@16000000 { 125 compatible = "qcom,gsbi-v1.0.0"; 126 cell-index = <12>; 127 reg = <0x16000000 0x100>; 128 clocks = <&gcc GSBI1_H_CLK>; 129 clock-names = "iface"; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 ranges; 133 134 syscon-tcsr = <&tcsr>; 135 136 status = "disabled"; 137 138 gsbi1_spi: spi@16080000 { 139 compatible = "qcom,spi-qup-v1.1.1"; 140 reg = <0x16080000 0x1000>; 141 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 143 clock-names = "core", "iface"; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 status = "disabled"; 147 }; 148 }; 149 150 gsbi3: gsbi@16200000 { 151 compatible = "qcom,gsbi-v1.0.0"; 152 cell-index = <12>; 153 reg = <0x16200000 0x100>; 154 clocks = <&gcc GSBI3_H_CLK>; 155 clock-names = "iface"; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges; 159 160 syscon-tcsr = <&tcsr>; 161 status = "disabled"; 162 163 gsbi3_i2c: i2c@16280000 { 164 compatible = "qcom,i2c-qup-v1.1.1"; 165 reg = <0x16280000 0x1000>; 166 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 168 clock-names = "core", "iface"; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 status = "disabled"; 172 }; 173 }; 174 175 gsbi6: gsbi@16500000 { 176 compatible = "qcom,gsbi-v1.0.0"; 177 cell-index = <12>; 178 reg = <0x16500000 0x100>; 179 clocks = <&gcc GSBI6_H_CLK>; 180 clock-names = "iface"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges; 184 status = "disabled"; 185 186 syscon-tcsr = <&tcsr>; 187 188 gsbi6_serial: serial@16540000 { 189 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 190 reg = <0x16540000 0x1000>, 191 <0x16500000 0x1000>; 192 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 194 clock-names = "core", "iface"; 195 status = "disabled"; 196 }; 197 198 gsbi6_i2c: i2c@16580000 { 199 compatible = "qcom,i2c-qup-v1.1.1"; 200 reg = <0x16580000 0x1000>; 201 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 203 clock-names = "core", "iface"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 status = "disabled"; 207 }; 208 }; 209 210 gsbi7: gsbi@16600000 { 211 compatible = "qcom,gsbi-v1.0.0"; 212 cell-index = <12>; 213 reg = <0x16600000 0x100>; 214 clocks = <&gcc GSBI7_H_CLK>; 215 clock-names = "iface"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 status = "disabled"; 220 221 syscon-tcsr = <&tcsr>; 222 223 gsbi7_serial: serial@16640000 { 224 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 225 reg = <0x16640000 0x1000>, 226 <0x16600000 0x1000>; 227 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 229 clock-names = "core", "iface"; 230 status = "disabled"; 231 }; 232 233 gsbi7_i2c: i2c@16680000 { 234 compatible = "qcom,i2c-qup-v1.1.1"; 235 reg = <0x16680000 0x1000>; 236 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 238 clock-names = "core", "iface"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 status = "disabled"; 242 }; 243 }; 244 245 gsbi8: gsbi@19800000 { 246 compatible = "qcom,gsbi-v1.0.0"; 247 cell-index = <12>; 248 reg = <0x19800000 0x100>; 249 clocks = <&gcc GSBI8_H_CLK>; 250 clock-names = "iface"; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges; 254 255 syscon-tcsr = <&tcsr>; 256 status = "disabled"; 257 258 gsbi8_i2c: i2c@19880000 { 259 compatible = "qcom,i2c-qup-v1.1.1"; 260 reg = <0x19880000 0x1000>; 261 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; 263 clock-names = "core", "iface"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 status = "disabled"; 267 }; 268 }; 269 270 gsbi12: gsbi@19c00000 { 271 compatible = "qcom,gsbi-v1.0.0"; 272 cell-index = <12>; 273 reg = <0x19c00000 0x100>; 274 clocks = <&gcc GSBI12_H_CLK>; 275 clock-names = "iface"; 276 #address-cells = <1>; 277 #size-cells = <1>; 278 ranges; 279 280 syscon-tcsr = <&tcsr>; 281 282 gsbi12_serial: serial@19c40000 { 283 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 284 reg = <0x19c40000 0x1000>, 285 <0x19c00000 0x1000>; 286 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; 288 clock-names = "core", "iface"; 289 status = "disabled"; 290 }; 291 292 gsbi12_i2c: i2c@19c80000 { 293 compatible = "qcom,i2c-qup-v1.1.1"; 294 reg = <0x19c80000 0x1000>; 295 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; 297 clock-names = "core", "iface"; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 }; 303 304 ebi2: external-bus@1a100000 { 305 compatible = "qcom,msm8660-ebi2"; 306 #address-cells = <2>; 307 #size-cells = <1>; 308 ranges = <0 0x0 0x1a800000 0x00800000>, 309 <1 0x0 0x1b000000 0x00800000>, 310 <2 0x0 0x1b800000 0x00800000>, 311 <3 0x0 0x1d000000 0x08000000>, 312 <4 0x0 0x1c800000 0x00800000>, 313 <5 0x0 0x1c000000 0x00800000>; 314 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; 315 reg-names = "ebi2", "xmem"; 316 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; 317 clock-names = "ebi2x", "ebi2"; 318 status = "disabled"; 319 }; 320 321 ssbi: ssbi@500000 { 322 compatible = "qcom,ssbi"; 323 reg = <0x500000 0x1000>; 324 qcom,controller-type = "pmic-arbiter"; 325 }; 326 327 l2cc: clock-controller@2082000 { 328 compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; 329 reg = <0x02082000 0x1000>; 330 }; 331 332 rpm: rpm@104000 { 333 compatible = "qcom,rpm-msm8660"; 334 reg = <0x00104000 0x1000>; 335 qcom,ipc = <&l2cc 0x8 2>; 336 337 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 338 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 339 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 340 interrupt-names = "ack", "err", "wakeup"; 341 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 342 clock-names = "ram"; 343 344 rpmcc: clock-controller { 345 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; 346 #clock-cells = <1>; 347 clocks = <&pxo_board>; 348 clock-names = "pxo"; 349 }; 350 351 regulators-0 { 352 compatible = "qcom,rpm-pm8901-regulators"; 353 354 pm8901_l0: l0 {}; 355 pm8901_l1: l1 {}; 356 pm8901_l2: l2 {}; 357 pm8901_l3: l3 {}; 358 pm8901_l4: l4 {}; 359 pm8901_l5: l5 {}; 360 pm8901_l6: l6 {}; 361 362 /* S0 and S1 Handled as SAW regulators by SPM */ 363 pm8901_s2: s2 {}; 364 pm8901_s3: s3 {}; 365 pm8901_s4: s4 {}; 366 367 pm8901_lvs0: lvs0 {}; 368 pm8901_lvs1: lvs1 {}; 369 pm8901_lvs2: lvs2 {}; 370 pm8901_lvs3: lvs3 {}; 371 372 pm8901_mvs: mvs {}; 373 }; 374 375 regulators-1 { 376 compatible = "qcom,rpm-pm8058-regulators"; 377 378 pm8058_l0: l0 {}; 379 pm8058_l1: l1 {}; 380 pm8058_l2: l2 {}; 381 pm8058_l3: l3 {}; 382 pm8058_l4: l4 {}; 383 pm8058_l5: l5 {}; 384 pm8058_l6: l6 {}; 385 pm8058_l7: l7 {}; 386 pm8058_l8: l8 {}; 387 pm8058_l9: l9 {}; 388 pm8058_l10: l10 {}; 389 pm8058_l11: l11 {}; 390 pm8058_l12: l12 {}; 391 pm8058_l13: l13 {}; 392 pm8058_l14: l14 {}; 393 pm8058_l15: l15 {}; 394 pm8058_l16: l16 {}; 395 pm8058_l17: l17 {}; 396 pm8058_l18: l18 {}; 397 pm8058_l19: l19 {}; 398 pm8058_l20: l20 {}; 399 pm8058_l21: l21 {}; 400 pm8058_l22: l22 {}; 401 pm8058_l23: l23 {}; 402 pm8058_l24: l24 {}; 403 pm8058_l25: l25 {}; 404 405 pm8058_s0: s0 {}; 406 pm8058_s1: s1 {}; 407 pm8058_s2: s2 {}; 408 pm8058_s3: s3 {}; 409 pm8058_s4: s4 {}; 410 411 pm8058_lvs0: lvs0 {}; 412 pm8058_lvs1: lvs1 {}; 413 414 pm8058_ncp: ncp {}; 415 }; 416 }; 417 418 amba { 419 compatible = "simple-bus"; 420 #address-cells = <1>; 421 #size-cells = <1>; 422 ranges; 423 sdcc1: mmc@12400000 { 424 status = "disabled"; 425 compatible = "arm,pl18x", "arm,primecell"; 426 arm,primecell-periphid = <0x00051180>; 427 reg = <0x12400000 0x8000>; 428 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 430 clock-names = "mclk", "apb_pclk"; 431 bus-width = <8>; 432 max-frequency = <48000000>; 433 non-removable; 434 cap-sd-highspeed; 435 cap-mmc-highspeed; 436 }; 437 438 sdcc2: mmc@12140000 { 439 status = "disabled"; 440 compatible = "arm,pl18x", "arm,primecell"; 441 arm,primecell-periphid = <0x00051180>; 442 reg = <0x12140000 0x8000>; 443 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 445 clock-names = "mclk", "apb_pclk"; 446 bus-width = <8>; 447 max-frequency = <48000000>; 448 cap-sd-highspeed; 449 cap-mmc-highspeed; 450 }; 451 452 sdcc3: mmc@12180000 { 453 compatible = "arm,pl18x", "arm,primecell"; 454 arm,primecell-periphid = <0x00051180>; 455 status = "disabled"; 456 reg = <0x12180000 0x8000>; 457 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 459 clock-names = "mclk", "apb_pclk"; 460 bus-width = <4>; 461 cap-sd-highspeed; 462 cap-mmc-highspeed; 463 max-frequency = <48000000>; 464 no-1-8-v; 465 }; 466 467 sdcc4: mmc@121c0000 { 468 compatible = "arm,pl18x", "arm,primecell"; 469 arm,primecell-periphid = <0x00051180>; 470 status = "disabled"; 471 reg = <0x121c0000 0x8000>; 472 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 474 clock-names = "mclk", "apb_pclk"; 475 bus-width = <4>; 476 max-frequency = <48000000>; 477 cap-sd-highspeed; 478 cap-mmc-highspeed; 479 }; 480 481 sdcc5: mmc@12200000 { 482 compatible = "arm,pl18x", "arm,primecell"; 483 arm,primecell-periphid = <0x00051180>; 484 status = "disabled"; 485 reg = <0x12200000 0x8000>; 486 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; 488 clock-names = "mclk", "apb_pclk"; 489 bus-width = <4>; 490 cap-sd-highspeed; 491 cap-mmc-highspeed; 492 max-frequency = <48000000>; 493 }; 494 }; 495 496 tcsr: syscon@1a400000 { 497 compatible = "qcom,tcsr-msm8660", "syscon"; 498 reg = <0x1a400000 0x100>; 499 }; 500 }; 501 502}; 503