1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8660.h> 7#include <dt-bindings/soc/qcom,gsbi.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 model = "Qualcomm MSM8660"; 13 compatible = "qcom,msm8660"; 14 interrupt-parent = <&intc>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "qcom,scorpion"; 22 enable-method = "qcom,gcc-msm8660"; 23 device_type = "cpu"; 24 reg = <0>; 25 next-level-cache = <&L2>; 26 }; 27 28 cpu@1 { 29 compatible = "qcom,scorpion"; 30 enable-method = "qcom,gcc-msm8660"; 31 device_type = "cpu"; 32 reg = <1>; 33 next-level-cache = <&L2>; 34 }; 35 36 L2: l2-cache { 37 compatible = "cache"; 38 cache-level = <2>; 39 cache-unified; 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x0 0x0>; 46 }; 47 48 cpu-pmu { 49 compatible = "qcom,scorpion-mp-pmu"; 50 interrupts = <1 9 0x304>; 51 }; 52 53 clocks { 54 cxo_board: cxo-board-clk { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <19200000>; 58 clock-output-names = "cxo_board"; 59 }; 60 61 pxo_board: pxo-board-clk { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <27000000>; 65 clock-output-names = "pxo_board"; 66 }; 67 68 sleep-clk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <32768>; 72 clock-output-names = "sleep_clk"; 73 }; 74 }; 75 76 /* 77 * These channels from the ADC are simply hardware monitors. 78 * That is why the ADC is referred to as "HKADC" - HouseKeeping 79 * ADC. 80 */ 81 iio-hwmon { 82 compatible = "iio-hwmon"; 83 io-channels = <&pm8058_xoadc 0x00 0x01>, /* Battery */ 84 <&pm8058_xoadc 0x00 0x02>, /* DC in (charger) */ 85 <&pm8058_xoadc 0x00 0x04>, /* VPH the main system voltage */ 86 <&pm8058_xoadc 0x00 0x0b>, /* Die temperature */ 87 <&pm8058_xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 88 <&pm8058_xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 89 <&pm8058_xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ 90 }; 91 92 soc: soc { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges; 96 compatible = "simple-bus"; 97 98 intc: interrupt-controller@2080000 { 99 compatible = "qcom,msm-8660-qgic"; 100 interrupt-controller; 101 #interrupt-cells = <3>; 102 reg = < 0x02080000 0x1000 >, 103 < 0x02081000 0x1000 >; 104 }; 105 106 timer@2000000 { 107 compatible = "qcom,scss-timer", "qcom,msm-timer"; 108 interrupts = <1 0 0x301>, 109 <1 1 0x301>, 110 <1 2 0x301>; 111 reg = <0x02000000 0x100>; 112 clock-frequency = <27000000>, 113 <32768>; 114 cpu-offset = <0x40000>; 115 }; 116 117 tlmm: pinctrl@800000 { 118 compatible = "qcom,msm8660-pinctrl"; 119 reg = <0x800000 0x4000>; 120 121 gpio-controller; 122 gpio-ranges = <&tlmm 0 0 173>; 123 #gpio-cells = <2>; 124 interrupts = <0 16 0x4>; 125 interrupt-controller; 126 #interrupt-cells = <2>; 127 128 }; 129 130 gcc: clock-controller@900000 { 131 compatible = "qcom,gcc-msm8660"; 132 #clock-cells = <1>; 133 #power-domain-cells = <1>; 134 #reset-cells = <1>; 135 reg = <0x900000 0x4000>; 136 clocks = <&pxo_board>, <&cxo_board>; 137 clock-names = "pxo", "cxo"; 138 }; 139 140 gsbi1: gsbi@16000000 { 141 compatible = "qcom,gsbi-v1.0.0"; 142 cell-index = <12>; 143 reg = <0x16000000 0x100>; 144 clocks = <&gcc GSBI1_H_CLK>; 145 clock-names = "iface"; 146 #address-cells = <1>; 147 #size-cells = <1>; 148 ranges; 149 150 syscon-tcsr = <&tcsr>; 151 152 status = "disabled"; 153 154 gsbi1_spi: spi@16080000 { 155 compatible = "qcom,spi-qup-v1.1.1"; 156 reg = <0x16080000 0x1000>; 157 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 159 clock-names = "core", "iface"; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 status = "disabled"; 163 }; 164 }; 165 166 gsbi3: gsbi@16200000 { 167 compatible = "qcom,gsbi-v1.0.0"; 168 cell-index = <12>; 169 reg = <0x16200000 0x100>; 170 clocks = <&gcc GSBI3_H_CLK>; 171 clock-names = "iface"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges; 175 176 syscon-tcsr = <&tcsr>; 177 status = "disabled"; 178 179 gsbi3_i2c: i2c@16280000 { 180 compatible = "qcom,i2c-qup-v1.1.1"; 181 reg = <0x16280000 0x1000>; 182 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 184 clock-names = "core", "iface"; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 status = "disabled"; 188 }; 189 }; 190 191 gsbi6: gsbi@16500000 { 192 compatible = "qcom,gsbi-v1.0.0"; 193 cell-index = <12>; 194 reg = <0x16500000 0x100>; 195 clocks = <&gcc GSBI6_H_CLK>; 196 clock-names = "iface"; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges; 200 status = "disabled"; 201 202 syscon-tcsr = <&tcsr>; 203 204 gsbi6_serial: serial@16540000 { 205 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 206 reg = <0x16540000 0x1000>, 207 <0x16500000 0x1000>; 208 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 210 clock-names = "core", "iface"; 211 status = "disabled"; 212 }; 213 214 gsbi6_i2c: i2c@16580000 { 215 compatible = "qcom,i2c-qup-v1.1.1"; 216 reg = <0x16580000 0x1000>; 217 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 219 clock-names = "core", "iface"; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 status = "disabled"; 223 }; 224 }; 225 226 gsbi7: gsbi@16600000 { 227 compatible = "qcom,gsbi-v1.0.0"; 228 cell-index = <12>; 229 reg = <0x16600000 0x100>; 230 clocks = <&gcc GSBI7_H_CLK>; 231 clock-names = "iface"; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges; 235 status = "disabled"; 236 237 syscon-tcsr = <&tcsr>; 238 239 gsbi7_serial: serial@16640000 { 240 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 241 reg = <0x16640000 0x1000>, 242 <0x16600000 0x1000>; 243 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 245 clock-names = "core", "iface"; 246 status = "disabled"; 247 }; 248 249 gsbi7_i2c: i2c@16680000 { 250 compatible = "qcom,i2c-qup-v1.1.1"; 251 reg = <0x16680000 0x1000>; 252 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 254 clock-names = "core", "iface"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 status = "disabled"; 258 }; 259 }; 260 261 gsbi8: gsbi@19800000 { 262 compatible = "qcom,gsbi-v1.0.0"; 263 cell-index = <12>; 264 reg = <0x19800000 0x100>; 265 clocks = <&gcc GSBI8_H_CLK>; 266 clock-names = "iface"; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 ranges; 270 271 syscon-tcsr = <&tcsr>; 272 status = "disabled"; 273 274 gsbi8_i2c: i2c@19880000 { 275 compatible = "qcom,i2c-qup-v1.1.1"; 276 reg = <0x19880000 0x1000>; 277 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; 279 clock-names = "core", "iface"; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 status = "disabled"; 283 }; 284 }; 285 286 gsbi12: gsbi@19c00000 { 287 compatible = "qcom,gsbi-v1.0.0"; 288 cell-index = <12>; 289 reg = <0x19c00000 0x100>; 290 clocks = <&gcc GSBI12_H_CLK>; 291 clock-names = "iface"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 ranges; 295 296 syscon-tcsr = <&tcsr>; 297 298 gsbi12_serial: serial@19c40000 { 299 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 300 reg = <0x19c40000 0x1000>, 301 <0x19c00000 0x1000>; 302 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; 304 clock-names = "core", "iface"; 305 status = "disabled"; 306 }; 307 308 gsbi12_i2c: i2c@19c80000 { 309 compatible = "qcom,i2c-qup-v1.1.1"; 310 reg = <0x19c80000 0x1000>; 311 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; 313 clock-names = "core", "iface"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 }; 319 320 ebi2: external-bus@1a100000 { 321 compatible = "qcom,msm8660-ebi2"; 322 #address-cells = <2>; 323 #size-cells = <1>; 324 ranges = <0 0x0 0x1a800000 0x00800000>, 325 <1 0x0 0x1b000000 0x00800000>, 326 <2 0x0 0x1b800000 0x00800000>, 327 <3 0x0 0x1d000000 0x08000000>, 328 <4 0x0 0x1c800000 0x00800000>, 329 <5 0x0 0x1c000000 0x00800000>; 330 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; 331 reg-names = "ebi2", "xmem"; 332 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; 333 clock-names = "ebi2x", "ebi2"; 334 status = "disabled"; 335 }; 336 337 ssbi@500000 { 338 compatible = "qcom,ssbi"; 339 reg = <0x500000 0x1000>; 340 qcom,controller-type = "pmic-arbiter"; 341 342 pm8058: pmic { 343 compatible = "qcom,pm8058"; 344 #interrupt-cells = <2>; 345 interrupt-controller; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 349 pm8058_gpio: gpio@150 { 350 compatible = "qcom,pm8058-gpio", 351 "qcom,ssbi-gpio"; 352 reg = <0x150>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 gpio-controller; 356 gpio-ranges = <&pm8058_gpio 0 0 44>; 357 #gpio-cells = <2>; 358 359 }; 360 361 pm8058_mpps: mpps@50 { 362 compatible = "qcom,pm8058-mpp", 363 "qcom,ssbi-mpp"; 364 reg = <0x50>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 gpio-ranges = <&pm8058_mpps 0 0 12>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 372 pwrkey@1c { 373 compatible = "qcom,pm8058-pwrkey"; 374 reg = <0x1c>; 375 interrupt-parent = <&pm8058>; 376 interrupts = <50 1>, <51 1>; 377 debounce = <15625>; 378 pull-up; 379 }; 380 381 pm8058_keypad: keypad@148 { 382 compatible = "qcom,pm8058-keypad"; 383 reg = <0x148>; 384 interrupt-parent = <&pm8058>; 385 interrupts = <74 1>, <75 1>; 386 debounce = <15>; 387 scan-delay = <32>; 388 row-hold = <91500>; 389 }; 390 391 pm8058_xoadc: xoadc@197 { 392 compatible = "qcom,pm8058-adc"; 393 reg = <0x197>; 394 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; 395 #address-cells = <2>; 396 #size-cells = <0>; 397 #io-channel-cells = <2>; 398 399 vcoin: adc-channel@0 { 400 reg = <0x00 0x00>; 401 }; 402 vbat: adc-channel@1 { 403 reg = <0x00 0x01>; 404 }; 405 dcin: adc-channel@2 { 406 reg = <0x00 0x02>; 407 }; 408 ichg: adc-channel@3 { 409 reg = <0x00 0x03>; 410 }; 411 vph_pwr: adc-channel@4 { 412 reg = <0x00 0x04>; 413 }; 414 usb_vbus: adc-channel@a { 415 reg = <0x00 0x0a>; 416 }; 417 die_temp: adc-channel@b { 418 reg = <0x00 0x0b>; 419 }; 420 ref_625mv: adc-channel@c { 421 reg = <0x00 0x0c>; 422 }; 423 ref_1250mv: adc-channel@d { 424 reg = <0x00 0x0d>; 425 }; 426 ref_325mv: adc-channel@e { 427 reg = <0x00 0x0e>; 428 }; 429 ref_muxoff: adc-channel@f { 430 reg = <0x00 0x0f>; 431 }; 432 }; 433 434 rtc@1e8 { 435 compatible = "qcom,pm8058-rtc"; 436 reg = <0x1e8>; 437 interrupt-parent = <&pm8058>; 438 interrupts = <39 1>; 439 allow-set-time; 440 }; 441 442 vibrator@4a { 443 compatible = "qcom,pm8058-vib"; 444 reg = <0x4a>; 445 }; 446 447 pm8058_led48: led@48 { 448 compatible = "qcom,pm8058-keypad-led"; 449 reg = <0x48>; 450 status = "disabled"; 451 }; 452 453 pm8058_led131: led@131 { 454 compatible = "qcom,pm8058-led"; 455 reg = <0x131>; 456 status = "disabled"; 457 }; 458 459 pm8058_led132: led@132 { 460 compatible = "qcom,pm8058-led"; 461 reg = <0x132>; 462 status = "disabled"; 463 }; 464 465 pm8058_led133: led@133 { 466 compatible = "qcom,pm8058-led"; 467 reg = <0x133>; 468 status = "disabled"; 469 }; 470 471 }; 472 }; 473 474 l2cc: clock-controller@2082000 { 475 compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; 476 reg = <0x02082000 0x1000>; 477 }; 478 479 rpm: rpm@104000 { 480 compatible = "qcom,rpm-msm8660"; 481 reg = <0x00104000 0x1000>; 482 qcom,ipc = <&l2cc 0x8 2>; 483 484 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 487 interrupt-names = "ack", "err", "wakeup"; 488 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 489 clock-names = "ram"; 490 491 rpmcc: clock-controller { 492 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; 493 #clock-cells = <1>; 494 clocks = <&pxo_board>; 495 clock-names = "pxo"; 496 }; 497 498 regulators-0 { 499 compatible = "qcom,rpm-pm8901-regulators"; 500 501 pm8901_l0: l0 {}; 502 pm8901_l1: l1 {}; 503 pm8901_l2: l2 {}; 504 pm8901_l3: l3 {}; 505 pm8901_l4: l4 {}; 506 pm8901_l5: l5 {}; 507 pm8901_l6: l6 {}; 508 509 /* S0 and S1 Handled as SAW regulators by SPM */ 510 pm8901_s2: s2 {}; 511 pm8901_s3: s3 {}; 512 pm8901_s4: s4 {}; 513 514 pm8901_lvs0: lvs0 {}; 515 pm8901_lvs1: lvs1 {}; 516 pm8901_lvs2: lvs2 {}; 517 pm8901_lvs3: lvs3 {}; 518 519 pm8901_mvs: mvs {}; 520 }; 521 522 regulators-1 { 523 compatible = "qcom,rpm-pm8058-regulators"; 524 525 pm8058_l0: l0 {}; 526 pm8058_l1: l1 {}; 527 pm8058_l2: l2 {}; 528 pm8058_l3: l3 {}; 529 pm8058_l4: l4 {}; 530 pm8058_l5: l5 {}; 531 pm8058_l6: l6 {}; 532 pm8058_l7: l7 {}; 533 pm8058_l8: l8 {}; 534 pm8058_l9: l9 {}; 535 pm8058_l10: l10 {}; 536 pm8058_l11: l11 {}; 537 pm8058_l12: l12 {}; 538 pm8058_l13: l13 {}; 539 pm8058_l14: l14 {}; 540 pm8058_l15: l15 {}; 541 pm8058_l16: l16 {}; 542 pm8058_l17: l17 {}; 543 pm8058_l18: l18 {}; 544 pm8058_l19: l19 {}; 545 pm8058_l20: l20 {}; 546 pm8058_l21: l21 {}; 547 pm8058_l22: l22 {}; 548 pm8058_l23: l23 {}; 549 pm8058_l24: l24 {}; 550 pm8058_l25: l25 {}; 551 552 pm8058_s0: s0 {}; 553 pm8058_s1: s1 {}; 554 pm8058_s2: s2 {}; 555 pm8058_s3: s3 {}; 556 pm8058_s4: s4 {}; 557 558 pm8058_lvs0: lvs0 {}; 559 pm8058_lvs1: lvs1 {}; 560 561 pm8058_ncp: ncp {}; 562 }; 563 }; 564 565 amba { 566 compatible = "simple-bus"; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 ranges; 570 sdcc1: mmc@12400000 { 571 status = "disabled"; 572 compatible = "arm,pl18x", "arm,primecell"; 573 arm,primecell-periphid = <0x00051180>; 574 reg = <0x12400000 0x8000>; 575 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 577 clock-names = "mclk", "apb_pclk"; 578 bus-width = <8>; 579 max-frequency = <48000000>; 580 non-removable; 581 cap-sd-highspeed; 582 cap-mmc-highspeed; 583 }; 584 585 sdcc2: mmc@12140000 { 586 status = "disabled"; 587 compatible = "arm,pl18x", "arm,primecell"; 588 arm,primecell-periphid = <0x00051180>; 589 reg = <0x12140000 0x8000>; 590 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 592 clock-names = "mclk", "apb_pclk"; 593 bus-width = <8>; 594 max-frequency = <48000000>; 595 cap-sd-highspeed; 596 cap-mmc-highspeed; 597 }; 598 599 sdcc3: mmc@12180000 { 600 compatible = "arm,pl18x", "arm,primecell"; 601 arm,primecell-periphid = <0x00051180>; 602 status = "disabled"; 603 reg = <0x12180000 0x8000>; 604 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 606 clock-names = "mclk", "apb_pclk"; 607 bus-width = <4>; 608 cap-sd-highspeed; 609 cap-mmc-highspeed; 610 max-frequency = <48000000>; 611 no-1-8-v; 612 }; 613 614 sdcc4: mmc@121c0000 { 615 compatible = "arm,pl18x", "arm,primecell"; 616 arm,primecell-periphid = <0x00051180>; 617 status = "disabled"; 618 reg = <0x121c0000 0x8000>; 619 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 621 clock-names = "mclk", "apb_pclk"; 622 bus-width = <4>; 623 max-frequency = <48000000>; 624 cap-sd-highspeed; 625 cap-mmc-highspeed; 626 }; 627 628 sdcc5: mmc@12200000 { 629 compatible = "arm,pl18x", "arm,primecell"; 630 arm,primecell-periphid = <0x00051180>; 631 status = "disabled"; 632 reg = <0x12200000 0x8000>; 633 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; 635 clock-names = "mclk", "apb_pclk"; 636 bus-width = <4>; 637 cap-sd-highspeed; 638 cap-mmc-highspeed; 639 max-frequency = <48000000>; 640 }; 641 }; 642 643 tcsr: syscon@1a400000 { 644 compatible = "qcom,tcsr-msm8660", "syscon"; 645 reg = <0x1a400000 0x100>; 646 }; 647 }; 648 649}; 650