1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Device Tree Source for Qualcomm MDM9615 SoC 4 * 5 * Copyright (C) 2016 BayLibre, SAS. 6 * Author : Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13#include <dt-bindings/clock/qcom,lcc-msm8960.h> 14#include <dt-bindings/reset/qcom,gcc-mdm9615.h> 15#include <dt-bindings/mfd/qcom-rpm.h> 16#include <dt-bindings/soc/qcom,gsbi.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 model = "Qualcomm MDM9615"; 22 compatible = "qcom,mdm9615"; 23 interrupt-parent = <&intc>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a5"; 31 reg = <0>; 32 device_type = "cpu"; 33 next-level-cache = <&L2>; 34 }; 35 }; 36 37 cpu-pmu { 38 compatible = "arm,cortex-a5-pmu"; 39 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 40 }; 41 42 clocks { 43 cxo_board: cxo_board { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <19200000>; 47 }; 48 }; 49 50 regulators { 51 vsdcc_fixed: vsdcc-regulator { 52 compatible = "regulator-fixed"; 53 regulator-name = "SDCC Power"; 54 regulator-min-microvolt = <2700000>; 55 regulator-max-microvolt = <2700000>; 56 regulator-always-on; 57 }; 58 }; 59 60 soc: soc { 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges; 64 compatible = "simple-bus"; 65 66 L2: cache-controller@2040000 { 67 compatible = "arm,pl310-cache"; 68 reg = <0x02040000 0x1000>; 69 arm,data-latency = <2 2 0>; 70 cache-unified; 71 cache-level = <2>; 72 }; 73 74 intc: interrupt-controller@2000000 { 75 compatible = "qcom,msm-qgic2"; 76 interrupt-controller; 77 #interrupt-cells = <3>; 78 reg = <0x02000000 0x1000>, 79 <0x02002000 0x1000>; 80 }; 81 82 timer@200a000 { 83 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", 84 "qcom,msm-timer"; 85 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 86 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 87 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>; 88 reg = <0x0200a000 0x100>; 89 clock-frequency = <27000000>; 90 cpu-offset = <0x80000>; 91 }; 92 93 msmgpio: pinctrl@800000 { 94 compatible = "qcom,mdm9615-pinctrl"; 95 gpio-controller; 96 gpio-ranges = <&msmgpio 0 0 88>; 97 #gpio-cells = <2>; 98 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 99 interrupt-controller; 100 #interrupt-cells = <2>; 101 reg = <0x800000 0x4000>; 102 }; 103 104 gcc: clock-controller@900000 { 105 compatible = "qcom,gcc-mdm9615"; 106 #clock-cells = <1>; 107 #power-domain-cells = <1>; 108 #reset-cells = <1>; 109 reg = <0x900000 0x4000>; 110 clocks = <&cxo_board>, 111 <&lcc PLL4>; 112 }; 113 114 lcc: clock-controller@28000000 { 115 compatible = "qcom,lcc-mdm9615"; 116 reg = <0x28000000 0x1000>; 117 #clock-cells = <1>; 118 #reset-cells = <1>; 119 clocks = <&cxo_board>, 120 <&gcc PLL4_VOTE>, 121 <0>, 122 <0>, <0>, 123 <0>, <0>, 124 <0>; 125 clock-names = "cxo", 126 "pll4_vote", 127 "mi2s_codec_clk", 128 "codec_i2s_mic_codec_clk", 129 "spare_i2s_mic_codec_clk", 130 "codec_i2s_spkr_codec_clk", 131 "spare_i2s_spkr_codec_clk", 132 "pcm_codec_clk"; 133 }; 134 135 l2cc: clock-controller@2011000 { 136 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; 137 reg = <0x02011000 0x1000>; 138 }; 139 140 rng@1a500000 { 141 compatible = "qcom,prng"; 142 reg = <0x1a500000 0x200>; 143 clocks = <&gcc PRNG_CLK>; 144 clock-names = "core"; 145 assigned-clocks = <&gcc PRNG_CLK>; 146 assigned-clock-rates = <32000000>; 147 }; 148 149 gsbi2: gsbi@16100000 { 150 compatible = "qcom,gsbi-v1.0.0"; 151 cell-index = <2>; 152 reg = <0x16100000 0x100>; 153 clocks = <&gcc GSBI2_H_CLK>; 154 clock-names = "iface"; 155 status = "disabled"; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges; 159 160 gsbi2_i2c: i2c@16180000 { 161 compatible = "qcom,i2c-qup-v1.1.1"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 reg = <0x16180000 0x1000>; 165 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 166 167 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 168 clock-names = "core", "iface"; 169 status = "disabled"; 170 }; 171 }; 172 173 gsbi3: gsbi@16200000 { 174 compatible = "qcom,gsbi-v1.0.0"; 175 cell-index = <3>; 176 reg = <0x16200000 0x100>; 177 clocks = <&gcc GSBI3_H_CLK>; 178 clock-names = "iface"; 179 status = "disabled"; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 184 gsbi3_spi: spi@16280000 { 185 compatible = "qcom,spi-qup-v1.1.1"; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 reg = <0x16280000 0x1000>; 189 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 190 191 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 192 clock-names = "core", "iface"; 193 status = "disabled"; 194 }; 195 }; 196 197 gsbi4: gsbi@16300000 { 198 compatible = "qcom,gsbi-v1.0.0"; 199 cell-index = <4>; 200 reg = <0x16300000 0x100>; 201 clocks = <&gcc GSBI4_H_CLK>; 202 clock-names = "iface"; 203 status = "disabled"; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges; 207 208 syscon-tcsr = <&tcsr>; 209 210 gsbi4_serial: serial@16340000 { 211 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 212 reg = <0x16340000 0x1000>, 213 <0x16300000 0x1000>; 214 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 216 clock-names = "core", "iface"; 217 status = "disabled"; 218 }; 219 }; 220 221 gsbi5: gsbi@16400000 { 222 compatible = "qcom,gsbi-v1.0.0"; 223 cell-index = <5>; 224 reg = <0x16400000 0x100>; 225 clocks = <&gcc GSBI5_H_CLK>; 226 clock-names = "iface"; 227 status = "disabled"; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges; 231 232 syscon-tcsr = <&tcsr>; 233 234 gsbi5_i2c: i2c@16480000 { 235 compatible = "qcom,i2c-qup-v1.1.1"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 reg = <0x16480000 0x1000>; 239 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 240 241 /* QUP clock is not initialized, set rate */ 242 assigned-clocks = <&gcc GSBI5_QUP_CLK>; 243 assigned-clock-rates = <24000000>; 244 245 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 246 clock-names = "core", "iface"; 247 status = "disabled"; 248 }; 249 250 gsbi5_serial: serial@16440000 { 251 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 252 reg = <0x16440000 0x1000>, 253 <0x16400000 0x1000>; 254 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 256 clock-names = "core", "iface"; 257 status = "disabled"; 258 }; 259 }; 260 261 qcom,ssbi@500000 { 262 compatible = "qcom,ssbi"; 263 reg = <0x500000 0x1000>; 264 qcom,controller-type = "pmic-arbiter"; 265 266 pmicintc: pmic { 267 compatible = "qcom,pm8018", "qcom,pm8921"; 268 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>; 269 #interrupt-cells = <2>; 270 interrupt-controller; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 pwrkey@1c { 275 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; 276 reg = <0x1c>; 277 interrupt-parent = <&pmicintc>; 278 interrupts = <50 IRQ_TYPE_EDGE_RISING>, 279 <51 IRQ_TYPE_EDGE_RISING>; 280 debounce = <15625>; 281 pull-up; 282 }; 283 284 pmicmpp: mpps@50 { 285 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; 286 interrupt-controller; 287 #interrupt-cells = <2>; 288 reg = <0x50>; 289 gpio-controller; 290 #gpio-cells = <2>; 291 gpio-ranges = <&pmicmpp 0 0 6>; 292 }; 293 294 rtc@11d { 295 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; 296 interrupt-parent = <&pmicintc>; 297 interrupts = <39 IRQ_TYPE_EDGE_RISING>; 298 reg = <0x11d>; 299 allow-set-time; 300 }; 301 302 pmicgpio: gpio@150 { 303 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; 304 reg = <0x150>; 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 gpio-controller; 308 gpio-ranges = <&pmicgpio 0 0 6>; 309 #gpio-cells = <2>; 310 }; 311 }; 312 }; 313 314 sdcc1bam: dma-controller@12182000 { 315 compatible = "qcom,bam-v1.3.0"; 316 reg = <0x12182000 0x8000>; 317 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&gcc SDC1_H_CLK>; 319 clock-names = "bam_clk"; 320 #dma-cells = <1>; 321 qcom,ee = <0>; 322 }; 323 324 sdcc2bam: dma-controller@12142000 { 325 compatible = "qcom,bam-v1.3.0"; 326 reg = <0x12142000 0x8000>; 327 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&gcc SDC2_H_CLK>; 329 clock-names = "bam_clk"; 330 #dma-cells = <1>; 331 qcom,ee = <0>; 332 }; 333 334 sdcc1: mmc@12180000 { 335 status = "disabled"; 336 compatible = "arm,pl18x", "arm,primecell"; 337 arm,primecell-periphid = <0x00051180>; 338 reg = <0x12180000 0x2000>; 339 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 341 clock-names = "mclk", "apb_pclk"; 342 bus-width = <8>; 343 max-frequency = <48000000>; 344 cap-sd-highspeed; 345 cap-mmc-highspeed; 346 vmmc-supply = <&vsdcc_fixed>; 347 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 348 dma-names = "tx", "rx"; 349 assigned-clocks = <&gcc SDC1_CLK>; 350 assigned-clock-rates = <400000>; 351 }; 352 353 sdcc2: mmc@12140000 { 354 compatible = "arm,pl18x", "arm,primecell"; 355 arm,primecell-periphid = <0x00051180>; 356 status = "disabled"; 357 reg = <0x12140000 0x2000>; 358 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 360 clock-names = "mclk", "apb_pclk"; 361 bus-width = <4>; 362 cap-sd-highspeed; 363 cap-mmc-highspeed; 364 max-frequency = <48000000>; 365 no-1-8-v; 366 vmmc-supply = <&vsdcc_fixed>; 367 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; 368 dma-names = "tx", "rx"; 369 assigned-clocks = <&gcc SDC2_CLK>; 370 assigned-clock-rates = <400000>; 371 }; 372 373 tcsr: syscon@1a400000 { 374 compatible = "qcom,tcsr-mdm9615", "syscon"; 375 reg = <0x1a400000 0x100>; 376 }; 377 378 rpm: rpm@108000 { 379 compatible = "qcom,rpm-mdm9615"; 380 reg = <0x108000 0x1000>; 381 382 qcom,ipc = <&l2cc 0x8 2>; 383 384 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 387 interrupt-names = "ack", "err", "wakeup"; 388 389 regulators { 390 compatible = "qcom,rpm-pm8018-regulators"; 391 392 vin_lvs1-supply = <&pm8018_s3>; 393 394 vdd_l7-supply = <&pm8018_s4>; 395 vdd_l8-supply = <&pm8018_s3>; 396 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; 397 398 /* Buck SMPS */ 399 pm8018_s1: s1 { 400 regulator-min-microvolt = <500000>; 401 regulator-max-microvolt = <1150000>; 402 qcom,switch-mode-frequency = <1600000>; 403 bias-pull-down; 404 }; 405 406 pm8018_s2: s2 { 407 regulator-min-microvolt = <1225000>; 408 regulator-max-microvolt = <1300000>; 409 qcom,switch-mode-frequency = <1600000>; 410 bias-pull-down; 411 }; 412 413 pm8018_s3: s3 { 414 regulator-always-on; 415 regulator-min-microvolt = <1800000>; 416 regulator-max-microvolt = <1800000>; 417 qcom,switch-mode-frequency = <1600000>; 418 bias-pull-down; 419 }; 420 421 pm8018_s4: s4 { 422 regulator-min-microvolt = <2100000>; 423 regulator-max-microvolt = <2200000>; 424 qcom,switch-mode-frequency = <1600000>; 425 bias-pull-down; 426 }; 427 428 pm8018_s5: s5 { 429 regulator-always-on; 430 regulator-min-microvolt = <1350000>; 431 regulator-max-microvolt = <1350000>; 432 qcom,switch-mode-frequency = <1600000>; 433 bias-pull-down; 434 }; 435 436 /* PMOS LDO */ 437 pm8018_l2: l2 { 438 regulator-always-on; 439 regulator-min-microvolt = <1800000>; 440 regulator-max-microvolt = <1800000>; 441 bias-pull-down; 442 }; 443 444 pm8018_l3: l3 { 445 regulator-always-on; 446 regulator-min-microvolt = <1800000>; 447 regulator-max-microvolt = <1800000>; 448 bias-pull-down; 449 }; 450 451 pm8018_l4: l4 { 452 regulator-min-microvolt = <3300000>; 453 regulator-max-microvolt = <3300000>; 454 bias-pull-down; 455 }; 456 457 pm8018_l5: l5 { 458 regulator-min-microvolt = <2850000>; 459 regulator-max-microvolt = <2850000>; 460 bias-pull-down; 461 }; 462 463 pm8018_l6: l6 { 464 regulator-min-microvolt = <1800000>; 465 regulator-max-microvolt = <2850000>; 466 bias-pull-down; 467 }; 468 469 pm8018_l7: l7 { 470 regulator-min-microvolt = <1850000>; 471 regulator-max-microvolt = <1900000>; 472 bias-pull-down; 473 }; 474 475 pm8018_l8: l8 { 476 regulator-min-microvolt = <1200000>; 477 regulator-max-microvolt = <1200000>; 478 bias-pull-down; 479 }; 480 481 pm8018_l9: l9 { 482 regulator-min-microvolt = <750000>; 483 regulator-max-microvolt = <1150000>; 484 bias-pull-down; 485 }; 486 487 pm8018_l10: l10 { 488 regulator-min-microvolt = <1050000>; 489 regulator-max-microvolt = <1050000>; 490 bias-pull-down; 491 }; 492 493 pm8018_l11: l11 { 494 regulator-min-microvolt = <1050000>; 495 regulator-max-microvolt = <1050000>; 496 bias-pull-down; 497 }; 498 499 pm8018_l12: l12 { 500 regulator-min-microvolt = <1050000>; 501 regulator-max-microvolt = <1050000>; 502 bias-pull-down; 503 }; 504 505 pm8018_l13: l13 { 506 regulator-min-microvolt = <1850000>; 507 regulator-max-microvolt = <2950000>; 508 bias-pull-down; 509 }; 510 511 pm8018_l14: l14 { 512 regulator-min-microvolt = <2850000>; 513 regulator-max-microvolt = <2850000>; 514 bias-pull-down; 515 }; 516 517 /* Low Voltage Switch */ 518 pm8018_lvs1: lvs1 { 519 bias-pull-down; 520 }; 521 }; 522 }; 523 }; 524}; 525