xref: /linux/scripts/dtc/include-prefixes/arm/qcom/qcom-mdm9615.dtsi (revision c34e9ab9a612ee8b18273398ef75c207b01f516d)

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Device Tree Source for Qualcomm MDM9615 SoC
 *
 * Copyright (C) 2016 BayLibre, SAS.
 * Author : Neil Armstrong <narmstrong@baylibre.com>
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MDM9615";
	compatible = "qcom,mdm9615";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a5";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&l2>;
		};
	};

	cpu-pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
		cxo_board: cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};
	};

	vsdcc_fixed: vsdcc-regulator {
		compatible = "regulator-fixed";
		regulator-name = "SDCC Power";
		regulator-min-microvolt = <2700000>;
		regulator-max-microvolt = <2700000>;
		regulator-always-on;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		l2: cache-controller@2040000 {
			compatible = "arm,pl310-cache";
			reg = <0x02040000 0x1000>;
			arm,data-latency = <2 2 0>;
			cache-unified;
			cache-level = <2>;
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer",
				     "qcom,msm-timer";
			interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>;
			cpu-offset = <0x80000>;
		};

		msmgpio: pinctrl@800000 {
			compatible = "qcom,mdm9615-pinctrl";
			gpio-controller;
			gpio-ranges = <&msmgpio 0 0 88>;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x800000 0x4000>;
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-mdm9615";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0x900000 0x4000>;
			clocks = <&cxo_board>,
				 <&lcc PLL4>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-mdm9615";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&cxo_board>,
				 <&gcc PLL4_VOTE>,
				 <0>,
				 <0>, <0>,
				 <0>, <0>,
				 <0>;
			clock-names = "cxo",
				      "pll4_vote",
				      "mi2s_codec_clk",
				      "codec_i2s_mic_codec_clk",
				      "spare_i2s_mic_codec_clk",
				      "codec_i2s_spkr_codec_clk",
				      "spare_i2s_spkr_codec_clk",
				      "pcm_codec_clk";
		};

		l2cc: clock-controller@2011000 {
			compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
			reg = <0x02011000 0x1000>;
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
			assigned-clocks = <&gcc PRNG_CLK>;
			assigned-clock-rates = <32000000>;
		};

		gsbi2: gsbi@16100000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x16100000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi2_i2c: i2c@16180000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x16180000 0x1000>;
				interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi3: gsbi@16200000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <3>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi3_spi: spi@16280000 {
				compatible = "qcom,spi-qup-v1.1.1";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi4: gsbi@16300000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <4>;
			reg = <0x16300000 0x100>;
			clocks = <&gcc GSBI4_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi4_serial: serial@16340000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16340000 0x1000>,
				      <0x16300000 0x1000>;
				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi5: gsbi@16400000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x16400000 0x100>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi5_i2c: i2c@16480000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x16480000 0x1000>;
				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

				/* QUP clock is not initialized, set rate */
				assigned-clocks = <&gcc GSBI5_QUP_CLK>;
				assigned-clock-rates = <24000000>;

				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi5_serial: serial@16440000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16440000 0x1000>,
				      <0x16400000 0x1000>;
				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		ssbi: ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";
		};

		sdcc1bam: dma-controller@12182000 {
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc2bam: dma-controller@12142000 {
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12142000 0x8000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC2_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc1: mmc@12180000 {
			status = "disabled";
			compatible = "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00051180>;
			reg = <0x12180000 0x2000>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
			clock-names = "mclk", "apb_pclk";
			bus-width = <8>;
			max-frequency = <48000000>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			vmmc-supply = <&vsdcc_fixed>;
			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
			dma-names = "tx", "rx";
			assigned-clocks = <&gcc SDC1_CLK>;
			assigned-clock-rates = <400000>;
		};

		sdcc2: mmc@12140000 {
			compatible = "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00051180>;
			status = "disabled";
			reg = <0x12140000 0x2000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
			clock-names = "mclk", "apb_pclk";
			bus-width = <4>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <48000000>;
			no-1-8-v;
			vmmc-supply = <&vsdcc_fixed>;
			dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
			dma-names = "tx", "rx";
			assigned-clocks = <&gcc SDC2_CLK>;
			assigned-clock-rates = <400000>;
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-mdm9615", "syscon";
			reg = <0x1a400000 0x100>;
		};

		rpm: rpm@108000 {
			compatible = "qcom,rpm-mdm9615";
			reg = <0x108000 0x1000>;

			qcom,ipc = <&l2cc 0x8 2>;

			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "ack", "err", "wakeup";
		};
	};
};