1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mfd/qcom-rpm.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11#include <dt-bindings/soc/qcom,gsbi.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Qualcomm IPQ8064"; 18 compatible = "qcom,ipq8064"; 19 interrupt-parent = <&intc>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "qcom,krait"; 27 enable-method = "qcom,kpss-acc-v1"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 qcom,acc = <&acc0>; 32 qcom,saw = <&saw0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "qcom,krait"; 37 enable-method = "qcom,kpss-acc-v1"; 38 device_type = "cpu"; 39 reg = <1>; 40 next-level-cache = <&L2>; 41 qcom,acc = <&acc1>; 42 qcom,saw = <&saw1>; 43 }; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-unified; 49 }; 50 }; 51 52 thermal-zones { 53 sensor0-thermal { 54 polling-delay-passive = <0>; 55 polling-delay = <0>; 56 thermal-sensors = <&tsens 0>; 57 58 trips { 59 cpu-critical { 60 temperature = <105000>; 61 hysteresis = <2000>; 62 type = "critical"; 63 }; 64 65 cpu-hot { 66 temperature = <95000>; 67 hysteresis = <2000>; 68 type = "hot"; 69 }; 70 }; 71 }; 72 73 sensor1-thermal { 74 polling-delay-passive = <0>; 75 polling-delay = <0>; 76 thermal-sensors = <&tsens 1>; 77 78 trips { 79 cpu-critical { 80 temperature = <105000>; 81 hysteresis = <2000>; 82 type = "critical"; 83 }; 84 85 cpu-hot { 86 temperature = <95000>; 87 hysteresis = <2000>; 88 type = "hot"; 89 }; 90 }; 91 }; 92 93 sensor2-thermal { 94 polling-delay-passive = <0>; 95 polling-delay = <0>; 96 thermal-sensors = <&tsens 2>; 97 98 trips { 99 cpu-critical { 100 temperature = <105000>; 101 hysteresis = <2000>; 102 type = "critical"; 103 }; 104 105 cpu-hot { 106 temperature = <95000>; 107 hysteresis = <2000>; 108 type = "hot"; 109 }; 110 }; 111 }; 112 113 sensor3-thermal { 114 polling-delay-passive = <0>; 115 polling-delay = <0>; 116 thermal-sensors = <&tsens 3>; 117 118 trips { 119 cpu-critical { 120 temperature = <105000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 125 cpu-hot { 126 temperature = <95000>; 127 hysteresis = <2000>; 128 type = "hot"; 129 }; 130 }; 131 }; 132 133 sensor4-thermal { 134 polling-delay-passive = <0>; 135 polling-delay = <0>; 136 thermal-sensors = <&tsens 4>; 137 138 trips { 139 cpu-critical { 140 temperature = <105000>; 141 hysteresis = <2000>; 142 type = "critical"; 143 }; 144 145 cpu-hot { 146 temperature = <95000>; 147 hysteresis = <2000>; 148 type = "hot"; 149 }; 150 }; 151 }; 152 153 sensor5-thermal { 154 polling-delay-passive = <0>; 155 polling-delay = <0>; 156 thermal-sensors = <&tsens 5>; 157 158 trips { 159 cpu-critical { 160 temperature = <105000>; 161 hysteresis = <2000>; 162 type = "critical"; 163 }; 164 165 cpu-hot { 166 temperature = <95000>; 167 hysteresis = <2000>; 168 type = "hot"; 169 }; 170 }; 171 }; 172 173 sensor6-thermal { 174 polling-delay-passive = <0>; 175 polling-delay = <0>; 176 thermal-sensors = <&tsens 6>; 177 178 trips { 179 cpu-critical { 180 temperature = <105000>; 181 hysteresis = <2000>; 182 type = "critical"; 183 }; 184 185 cpu-hot { 186 temperature = <95000>; 187 hysteresis = <2000>; 188 type = "hot"; 189 }; 190 }; 191 }; 192 193 sensor7-thermal { 194 polling-delay-passive = <0>; 195 polling-delay = <0>; 196 thermal-sensors = <&tsens 7>; 197 198 trips { 199 cpu-critical { 200 temperature = <105000>; 201 hysteresis = <2000>; 202 type = "critical"; 203 }; 204 205 cpu-hot { 206 temperature = <95000>; 207 hysteresis = <2000>; 208 type = "hot"; 209 }; 210 }; 211 }; 212 213 sensor8-thermal { 214 polling-delay-passive = <0>; 215 polling-delay = <0>; 216 thermal-sensors = <&tsens 8>; 217 218 trips { 219 cpu-critical { 220 temperature = <105000>; 221 hysteresis = <2000>; 222 type = "critical"; 223 }; 224 225 cpu-hot { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "hot"; 229 }; 230 }; 231 }; 232 233 sensor9-thermal { 234 polling-delay-passive = <0>; 235 polling-delay = <0>; 236 thermal-sensors = <&tsens 9>; 237 238 trips { 239 cpu-critical { 240 temperature = <105000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 245 cpu-hot { 246 temperature = <95000>; 247 hysteresis = <2000>; 248 type = "hot"; 249 }; 250 }; 251 }; 252 253 sensor10-thermal { 254 polling-delay-passive = <0>; 255 polling-delay = <0>; 256 thermal-sensors = <&tsens 10>; 257 258 trips { 259 cpu-critical { 260 temperature = <105000>; 261 hysteresis = <2000>; 262 type = "critical"; 263 }; 264 265 cpu-hot { 266 temperature = <95000>; 267 hysteresis = <2000>; 268 type = "hot"; 269 }; 270 }; 271 }; 272 }; 273 274 memory { 275 device_type = "memory"; 276 reg = <0x0 0x0>; 277 }; 278 279 cpu-pmu { 280 compatible = "qcom,krait-pmu"; 281 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 282 IRQ_TYPE_LEVEL_HIGH)>; 283 }; 284 285 reserved-memory { 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges; 289 290 nss@40000000 { 291 reg = <0x40000000 0x1000000>; 292 no-map; 293 }; 294 295 smem: smem@41000000 { 296 compatible = "qcom,smem"; 297 reg = <0x41000000 0x200000>; 298 no-map; 299 300 hwlocks = <&sfpb_mutex 3>; 301 }; 302 }; 303 304 clocks { 305 cxo_board: cxo_board { 306 compatible = "fixed-clock"; 307 #clock-cells = <0>; 308 clock-frequency = <25000000>; 309 }; 310 311 pxo_board: pxo_board { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 clock-frequency = <25000000>; 315 }; 316 317 sleep_clk: sleep_clk { 318 compatible = "fixed-clock"; 319 clock-frequency = <32768>; 320 #clock-cells = <0>; 321 }; 322 }; 323 324 firmware { 325 scm { 326 compatible = "qcom,scm-ipq806x", "qcom,scm"; 327 }; 328 }; 329 330 stmmac_axi_setup: stmmac-axi-config { 331 snps,wr_osr_lmt = <7>; 332 snps,rd_osr_lmt = <7>; 333 snps,blen = <16 0 0 0 0 0 0>; 334 }; 335 336 vsdcc_fixed: vsdcc-regulator { 337 compatible = "regulator-fixed"; 338 regulator-name = "SDCC Power"; 339 regulator-min-microvolt = <3300000>; 340 regulator-max-microvolt = <3300000>; 341 regulator-always-on; 342 }; 343 344 soc: soc { 345 #address-cells = <1>; 346 #size-cells = <1>; 347 ranges; 348 compatible = "simple-bus"; 349 350 rpm: rpm@108000 { 351 compatible = "qcom,rpm-ipq8064"; 352 reg = <0x00108000 0x1000>; 353 qcom,ipc = <&l2cc 0x8 2>; 354 355 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-names = "ack", "err", "wakeup"; 359 360 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 361 clock-names = "ram"; 362 363 rpmcc: clock-controller { 364 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; 365 #clock-cells = <1>; 366 }; 367 }; 368 369 ssbi@500000 { 370 compatible = "qcom,ssbi"; 371 reg = <0x00500000 0x1000>; 372 qcom,controller-type = "pmic-arbiter"; 373 }; 374 375 qfprom: qfprom@700000 { 376 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; 377 reg = <0x00700000 0x1000>; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 speedbin_efuse: speedbin@c0 { 381 reg = <0xc0 0x4>; 382 }; 383 tsens_calib: calib@400 { 384 reg = <0x400 0xb>; 385 }; 386 tsens_calib_backup: calib_backup@410 { 387 reg = <0x410 0xb>; 388 }; 389 }; 390 391 qcom_pinmux: pinmux@800000 { 392 compatible = "qcom,ipq8064-pinctrl"; 393 reg = <0x00800000 0x4000>; 394 395 gpio-controller; 396 gpio-ranges = <&qcom_pinmux 0 0 69>; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 401 402 pcie0_pins: pcie0_pinmux { 403 mux { 404 pins = "gpio3"; 405 function = "pcie1_rst"; 406 drive-strength = <12>; 407 bias-disable; 408 }; 409 }; 410 411 pcie1_pins: pcie1_pinmux { 412 mux { 413 pins = "gpio48"; 414 function = "pcie2_rst"; 415 drive-strength = <12>; 416 bias-disable; 417 }; 418 }; 419 420 pcie2_pins: pcie2_pinmux { 421 mux { 422 pins = "gpio63"; 423 function = "pcie3_rst"; 424 drive-strength = <12>; 425 bias-disable; 426 }; 427 }; 428 429 i2c4_pins: i2c4-default { 430 pins = "gpio12", "gpio13"; 431 function = "gsbi4"; 432 drive-strength = <12>; 433 bias-disable; 434 }; 435 436 spi_pins: spi_pins { 437 mux { 438 pins = "gpio18", "gpio19", "gpio21"; 439 function = "gsbi5"; 440 drive-strength = <10>; 441 bias-none; 442 }; 443 }; 444 445 leds_pins: leds_pins { 446 mux { 447 pins = "gpio7", "gpio8", "gpio9", 448 "gpio26", "gpio53"; 449 function = "gpio"; 450 drive-strength = <2>; 451 bias-pull-down; 452 output-low; 453 }; 454 }; 455 456 buttons_pins: buttons_pins { 457 mux { 458 pins = "gpio54"; 459 drive-strength = <2>; 460 bias-pull-up; 461 }; 462 }; 463 464 nand_pins: nand_pins { 465 mux { 466 pins = "gpio34", "gpio35", "gpio36", 467 "gpio37", "gpio38", "gpio39", 468 "gpio40", "gpio41", "gpio42", 469 "gpio43", "gpio44", "gpio45", 470 "gpio46", "gpio47"; 471 function = "nand"; 472 drive-strength = <10>; 473 bias-disable; 474 }; 475 476 pullups { 477 pins = "gpio39"; 478 function = "nand"; 479 drive-strength = <10>; 480 bias-pull-up; 481 }; 482 483 hold { 484 pins = "gpio40", "gpio41", "gpio42", 485 "gpio43", "gpio44", "gpio45", 486 "gpio46", "gpio47"; 487 function = "nand"; 488 drive-strength = <10>; 489 bias-bus-hold; 490 }; 491 }; 492 493 mdio0_pins: mdio0-pins { 494 mux { 495 pins = "gpio0", "gpio1"; 496 function = "mdio"; 497 drive-strength = <8>; 498 bias-disable; 499 }; 500 }; 501 502 rgmii2_pins: rgmii2-pins { 503 mux { 504 pins = "gpio27", "gpio28", "gpio29", 505 "gpio30", "gpio31", "gpio32", 506 "gpio51", "gpio52", "gpio59", 507 "gpio60", "gpio61", "gpio62"; 508 function = "rgmii2"; 509 drive-strength = <8>; 510 bias-disable; 511 }; 512 }; 513 }; 514 515 gcc: clock-controller@900000 { 516 compatible = "qcom,gcc-ipq8064", "syscon"; 517 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; 518 clock-names = "pxo", "cxo", "pll4"; 519 reg = <0x00900000 0x4000>; 520 #clock-cells = <1>; 521 #reset-cells = <1>; 522 #power-domain-cells = <1>; 523 524 tsens: thermal-sensor { 525 compatible = "qcom,ipq8064-tsens"; 526 527 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 528 nvmem-cell-names = "calib", "calib_backup"; 529 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "uplow"; 531 532 #qcom,sensors = <11>; 533 #thermal-sensor-cells = <1>; 534 }; 535 }; 536 537 sfpb_mutex: hwlock@1200600 { 538 compatible = "qcom,sfpb-mutex"; 539 reg = <0x01200600 0x100>; 540 541 #hwlock-cells = <1>; 542 }; 543 544 intc: interrupt-controller@2000000 { 545 compatible = "qcom,msm-qgic2"; 546 interrupt-controller; 547 #interrupt-cells = <3>; 548 reg = <0x02000000 0x1000>, 549 <0x02002000 0x1000>; 550 }; 551 552 timer@200a000 { 553 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", 554 "qcom,msm-timer"; 555 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 556 IRQ_TYPE_EDGE_RISING)>, 557 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 558 IRQ_TYPE_EDGE_RISING)>, 559 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 560 IRQ_TYPE_EDGE_RISING)>, 561 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 562 IRQ_TYPE_EDGE_RISING)>, 563 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 564 IRQ_TYPE_EDGE_RISING)>; 565 reg = <0x0200a000 0x100>; 566 clock-frequency = <25000000>; 567 clocks = <&sleep_clk>; 568 clock-names = "sleep"; 569 cpu-offset = <0x80000>; 570 }; 571 572 l2cc: clock-controller@2011000 { 573 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; 574 reg = <0x02011000 0x1000>; 575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 576 clock-names = "pll8_vote", "pxo"; 577 #clock-cells = <0>; 578 }; 579 580 acc0: clock-controller@2088000 { 581 compatible = "qcom,kpss-acc-v1"; 582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 583 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 584 clock-names = "pll8_vote", "pxo"; 585 clock-output-names = "acpu0_aux"; 586 #clock-cells = <0>; 587 }; 588 589 saw0: regulator@2089000 { 590 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; 591 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 592 regulator; 593 }; 594 595 acc1: clock-controller@2098000 { 596 compatible = "qcom,kpss-acc-v1"; 597 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 598 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 599 clock-names = "pll8_vote", "pxo"; 600 clock-output-names = "acpu1_aux"; 601 #clock-cells = <0>; 602 }; 603 604 saw1: regulator@2099000 { 605 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; 606 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 607 regulator; 608 }; 609 610 nss_common: syscon@3000000 { 611 compatible = "syscon"; 612 reg = <0x03000000 0x0000FFFF>; 613 }; 614 615 usb3_0: usb@100f8800 { 616 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 reg = <0x100f8800 0x8000>; 620 clocks = <&gcc USB30_0_MASTER_CLK>; 621 clock-names = "core"; 622 623 ranges; 624 625 resets = <&gcc USB30_0_MASTER_RESET>; 626 627 status = "disabled"; 628 629 dwc3_0: usb@10000000 { 630 compatible = "snps,dwc3"; 631 reg = <0x10000000 0xcd00>; 632 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 633 phys = <&hs_phy_0>, <&ss_phy_0>; 634 phy-names = "usb2-phy", "usb3-phy"; 635 dr_mode = "host"; 636 snps,dis_u3_susphy_quirk; 637 }; 638 }; 639 640 hs_phy_0: phy@100f8800 { 641 compatible = "qcom,ipq806x-usb-phy-hs"; 642 reg = <0x100f8800 0x30>; 643 clocks = <&gcc USB30_0_UTMI_CLK>; 644 clock-names = "ref"; 645 #phy-cells = <0>; 646 647 status = "disabled"; 648 }; 649 650 ss_phy_0: phy@100f8830 { 651 compatible = "qcom,ipq806x-usb-phy-ss"; 652 reg = <0x100f8830 0x30>; 653 clocks = <&gcc USB30_0_MASTER_CLK>; 654 clock-names = "ref"; 655 #phy-cells = <0>; 656 657 status = "disabled"; 658 }; 659 660 usb3_1: usb@110f8800 { 661 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 662 #address-cells = <1>; 663 #size-cells = <1>; 664 reg = <0x110f8800 0x8000>; 665 clocks = <&gcc USB30_1_MASTER_CLK>; 666 clock-names = "core"; 667 668 ranges; 669 670 resets = <&gcc USB30_1_MASTER_RESET>; 671 672 status = "disabled"; 673 674 dwc3_1: usb@11000000 { 675 compatible = "snps,dwc3"; 676 reg = <0x11000000 0xcd00>; 677 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 678 phys = <&hs_phy_1>, <&ss_phy_1>; 679 phy-names = "usb2-phy", "usb3-phy"; 680 dr_mode = "host"; 681 snps,dis_u3_susphy_quirk; 682 }; 683 }; 684 685 hs_phy_1: phy@110f8800 { 686 compatible = "qcom,ipq806x-usb-phy-hs"; 687 reg = <0x110f8800 0x30>; 688 clocks = <&gcc USB30_1_UTMI_CLK>; 689 clock-names = "ref"; 690 #phy-cells = <0>; 691 692 status = "disabled"; 693 }; 694 695 ss_phy_1: phy@110f8830 { 696 compatible = "qcom,ipq806x-usb-phy-ss"; 697 reg = <0x110f8830 0x30>; 698 clocks = <&gcc USB30_1_MASTER_CLK>; 699 clock-names = "ref"; 700 #phy-cells = <0>; 701 702 status = "disabled"; 703 }; 704 705 sdcc3bam: dma-controller@12182000 { 706 compatible = "qcom,bam-v1.3.0"; 707 reg = <0x12182000 0x8000>; 708 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&gcc SDC3_H_CLK>; 710 clock-names = "bam_clk"; 711 #dma-cells = <1>; 712 qcom,ee = <0>; 713 }; 714 715 sdcc1bam: dma-controller@12402000 { 716 compatible = "qcom,bam-v1.3.0"; 717 reg = <0x12402000 0x8000>; 718 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&gcc SDC1_H_CLK>; 720 clock-names = "bam_clk"; 721 #dma-cells = <1>; 722 qcom,ee = <0>; 723 }; 724 725 amba: amba { 726 compatible = "simple-bus"; 727 #address-cells = <1>; 728 #size-cells = <1>; 729 ranges; 730 731 sdcc3: mmc@12180000 { 732 compatible = "arm,pl18x", "arm,primecell"; 733 arm,primecell-periphid = <0x00051180>; 734 status = "disabled"; 735 reg = <0x12180000 0x2000>; 736 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 738 clock-names = "mclk", "apb_pclk"; 739 bus-width = <8>; 740 cap-sd-highspeed; 741 cap-mmc-highspeed; 742 max-frequency = <192000000>; 743 sd-uhs-sdr104; 744 sd-uhs-ddr50; 745 vqmmc-supply = <&vsdcc_fixed>; 746 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 747 dma-names = "tx", "rx"; 748 }; 749 750 sdcc1: mmc@12400000 { 751 status = "disabled"; 752 compatible = "arm,pl18x", "arm,primecell"; 753 arm,primecell-periphid = <0x00051180>; 754 reg = <0x12400000 0x2000>; 755 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 757 clock-names = "mclk", "apb_pclk"; 758 bus-width = <8>; 759 max-frequency = <96000000>; 760 non-removable; 761 cap-sd-highspeed; 762 cap-mmc-highspeed; 763 vmmc-supply = <&vsdcc_fixed>; 764 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 765 dma-names = "tx", "rx"; 766 }; 767 }; 768 769 gsbi1: gsbi@12440000 { 770 compatible = "qcom,gsbi-v1.0.0"; 771 reg = <0x12440000 0x100>; 772 cell-index = <1>; 773 clocks = <&gcc GSBI1_H_CLK>; 774 clock-names = "iface"; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 ranges; 778 779 syscon-tcsr = <&tcsr>; 780 781 status = "disabled"; 782 783 gsbi1_serial: serial@12450000 { 784 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 785 reg = <0x12450000 0x100>, 786 <0x12400000 0x03>; 787 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 789 clock-names = "core", "iface"; 790 791 status = "disabled"; 792 }; 793 794 gsbi1_i2c: i2c@12460000 { 795 compatible = "qcom,i2c-qup-v1.1.1"; 796 reg = <0x12460000 0x1000>; 797 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 799 clock-names = "core", "iface"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 803 status = "disabled"; 804 }; 805 }; 806 807 gsbi2: gsbi@12480000 { 808 compatible = "qcom,gsbi-v1.0.0"; 809 cell-index = <2>; 810 reg = <0x12480000 0x100>; 811 clocks = <&gcc GSBI2_H_CLK>; 812 clock-names = "iface"; 813 #address-cells = <1>; 814 #size-cells = <1>; 815 ranges; 816 status = "disabled"; 817 818 syscon-tcsr = <&tcsr>; 819 820 gsbi2_serial: serial@12490000 { 821 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 822 reg = <0x12490000 0x1000>, 823 <0x12480000 0x1000>; 824 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 826 clock-names = "core", "iface"; 827 status = "disabled"; 828 }; 829 830 gsbi2_i2c: i2c@124a0000 { 831 compatible = "qcom,i2c-qup-v1.1.1"; 832 reg = <0x124a0000 0x1000>; 833 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 834 835 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 836 clock-names = "core", "iface"; 837 status = "disabled"; 838 839 #address-cells = <1>; 840 #size-cells = <0>; 841 }; 842 }; 843 844 gsbi4: gsbi@16300000 { 845 compatible = "qcom,gsbi-v1.0.0"; 846 cell-index = <4>; 847 reg = <0x16300000 0x100>; 848 clocks = <&gcc GSBI4_H_CLK>; 849 clock-names = "iface"; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 ranges; 853 status = "disabled"; 854 855 syscon-tcsr = <&tcsr>; 856 857 gsbi4_serial: serial@16340000 { 858 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 859 reg = <0x16340000 0x1000>, 860 <0x16300000 0x1000>; 861 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 863 clock-names = "core", "iface"; 864 status = "disabled"; 865 }; 866 867 i2c@16380000 { 868 compatible = "qcom,i2c-qup-v1.1.1"; 869 reg = <0x16380000 0x1000>; 870 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 871 872 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 873 clock-names = "core", "iface"; 874 status = "disabled"; 875 876 #address-cells = <1>; 877 #size-cells = <0>; 878 }; 879 }; 880 881 gsbi6: gsbi@16500000 { 882 compatible = "qcom,gsbi-v1.0.0"; 883 reg = <0x16500000 0x100>; 884 cell-index = <6>; 885 clocks = <&gcc GSBI6_H_CLK>; 886 clock-names = "iface"; 887 #address-cells = <1>; 888 #size-cells = <1>; 889 ranges; 890 891 syscon-tcsr = <&tcsr>; 892 893 status = "disabled"; 894 895 gsbi6_i2c: i2c@16580000 { 896 compatible = "qcom,i2c-qup-v1.1.1"; 897 reg = <0x16580000 0x1000>; 898 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 899 900 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 901 clock-names = "core", "iface"; 902 903 #address-cells = <1>; 904 #size-cells = <0>; 905 906 status = "disabled"; 907 }; 908 909 gsbi6_spi: spi@16580000 { 910 compatible = "qcom,spi-qup-v1.1.1"; 911 reg = <0x16580000 0x1000>; 912 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 913 914 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 915 clock-names = "core", "iface"; 916 917 #address-cells = <1>; 918 #size-cells = <0>; 919 920 status = "disabled"; 921 }; 922 }; 923 924 gsbi7: gsbi@16600000 { 925 status = "disabled"; 926 compatible = "qcom,gsbi-v1.0.0"; 927 cell-index = <7>; 928 reg = <0x16600000 0x100>; 929 clocks = <&gcc GSBI7_H_CLK>; 930 clock-names = "iface"; 931 #address-cells = <1>; 932 #size-cells = <1>; 933 ranges; 934 syscon-tcsr = <&tcsr>; 935 936 gsbi7_serial: serial@16640000 { 937 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 938 reg = <0x16640000 0x1000>, 939 <0x16600000 0x1000>; 940 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 942 clock-names = "core", "iface"; 943 status = "disabled"; 944 }; 945 946 gsbi7_i2c: i2c@16680000 { 947 compatible = "qcom,i2c-qup-v1.1.1"; 948 reg = <0x16680000 0x1000>; 949 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 950 951 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 952 clock-names = "core", "iface"; 953 954 #address-cells = <1>; 955 #size-cells = <0>; 956 957 status = "disabled"; 958 }; 959 }; 960 961 adm_dma: dma-controller@18300000 { 962 compatible = "qcom,adm"; 963 reg = <0x18300000 0x100000>; 964 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 965 #dma-cells = <1>; 966 967 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 968 clock-names = "core", "iface"; 969 970 resets = <&gcc ADM0_RESET>, 971 <&gcc ADM0_PBUS_RESET>, 972 <&gcc ADM0_C0_RESET>, 973 <&gcc ADM0_C1_RESET>, 974 <&gcc ADM0_C2_RESET>; 975 reset-names = "clk", "pbus", "c0", "c1", "c2"; 976 qcom,ee = <0>; 977 978 status = "disabled"; 979 }; 980 981 gsbi5: gsbi@1a200000 { 982 compatible = "qcom,gsbi-v1.0.0"; 983 cell-index = <5>; 984 reg = <0x1a200000 0x100>; 985 clocks = <&gcc GSBI5_H_CLK>; 986 clock-names = "iface"; 987 #address-cells = <1>; 988 989 #size-cells = <1>; 990 ranges; 991 status = "disabled"; 992 993 syscon-tcsr = <&tcsr>; 994 995 gsbi5_serial: serial@1a240000 { 996 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 997 reg = <0x1a240000 0x1000>, 998 <0x1a200000 0x1000>; 999 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 1001 clock-names = "core", "iface"; 1002 status = "disabled"; 1003 }; 1004 1005 i2c@1a280000 { 1006 compatible = "qcom,i2c-qup-v1.1.1"; 1007 reg = <0x1a280000 0x1000>; 1008 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1009 1010 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1011 clock-names = "core", "iface"; 1012 status = "disabled"; 1013 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 }; 1017 1018 spi@1a280000 { 1019 compatible = "qcom,spi-qup-v1.1.1"; 1020 reg = <0x1a280000 0x1000>; 1021 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1022 1023 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1024 clock-names = "core", "iface"; 1025 status = "disabled"; 1026 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 }; 1030 }; 1031 1032 tcsr: syscon@1a400000 { 1033 compatible = "qcom,tcsr-ipq8064", "syscon"; 1034 reg = <0x1a400000 0x100>; 1035 }; 1036 1037 rng@1a500000 { 1038 compatible = "qcom,prng"; 1039 reg = <0x1a500000 0x200>; 1040 clocks = <&gcc PRNG_CLK>; 1041 clock-names = "core"; 1042 }; 1043 1044 nand: nand-controller@1ac00000 { 1045 compatible = "qcom,ipq806x-nand"; 1046 reg = <0x1ac00000 0x800>; 1047 1048 pinctrl-0 = <&nand_pins>; 1049 pinctrl-names = "default"; 1050 1051 clocks = <&gcc EBI2_CLK>, 1052 <&gcc EBI2_AON_CLK>; 1053 clock-names = "core", "aon"; 1054 1055 dmas = <&adm_dma 3>; 1056 dma-names = "rxtx"; 1057 qcom,cmd-crci = <15>; 1058 qcom,data-crci = <3>; 1059 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 1063 status = "disabled"; 1064 }; 1065 1066 sata_phy: sata-phy@1b400000 { 1067 compatible = "qcom,ipq806x-sata-phy"; 1068 reg = <0x1b400000 0x200>; 1069 1070 clocks = <&gcc SATA_PHY_CFG_CLK>; 1071 clock-names = "cfg"; 1072 1073 #phy-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 1077 pcie0: pcie@1b500000 { 1078 compatible = "qcom,pcie-ipq8064"; 1079 reg = <0x1b500000 0x1000 1080 0x1b502000 0x80 1081 0x1b600000 0x100 1082 0x0ff00000 0x100000>; 1083 reg-names = "dbi", "elbi", "parf", "config"; 1084 device_type = "pci"; 1085 linux,pci-domain = <0>; 1086 bus-range = <0x00 0xff>; 1087 num-lanes = <1>; 1088 #address-cells = <3>; 1089 #size-cells = <2>; 1090 1091 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ 1092 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ 1093 1094 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1095 interrupt-names = "msi"; 1096 #interrupt-cells = <1>; 1097 interrupt-map-mask = <0 0 0 0x7>; 1098 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1099 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1100 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1101 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1102 1103 clocks = <&gcc PCIE_A_CLK>, 1104 <&gcc PCIE_H_CLK>, 1105 <&gcc PCIE_PHY_CLK>, 1106 <&gcc PCIE_AUX_CLK>, 1107 <&gcc PCIE_ALT_REF_CLK>; 1108 clock-names = "core", "iface", "phy", "aux", "ref"; 1109 1110 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 1111 assigned-clock-rates = <100000000>; 1112 1113 resets = <&gcc PCIE_ACLK_RESET>, 1114 <&gcc PCIE_HCLK_RESET>, 1115 <&gcc PCIE_POR_RESET>, 1116 <&gcc PCIE_PCI_RESET>, 1117 <&gcc PCIE_PHY_RESET>, 1118 <&gcc PCIE_EXT_RESET>; 1119 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1120 1121 pinctrl-0 = <&pcie0_pins>; 1122 pinctrl-names = "default"; 1123 1124 status = "disabled"; 1125 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 1126 }; 1127 1128 pcie1: pcie@1b700000 { 1129 compatible = "qcom,pcie-ipq8064"; 1130 reg = <0x1b700000 0x1000 1131 0x1b702000 0x80 1132 0x1b800000 0x100 1133 0x31f00000 0x100000>; 1134 reg-names = "dbi", "elbi", "parf", "config"; 1135 device_type = "pci"; 1136 linux,pci-domain = <1>; 1137 bus-range = <0x00 0xff>; 1138 num-lanes = <1>; 1139 #address-cells = <3>; 1140 #size-cells = <2>; 1141 1142 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ 1143 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ 1144 1145 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1146 interrupt-names = "msi"; 1147 #interrupt-cells = <1>; 1148 interrupt-map-mask = <0 0 0 0x7>; 1149 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1150 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1151 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1152 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1153 1154 clocks = <&gcc PCIE_1_A_CLK>, 1155 <&gcc PCIE_1_H_CLK>, 1156 <&gcc PCIE_1_PHY_CLK>, 1157 <&gcc PCIE_1_AUX_CLK>, 1158 <&gcc PCIE_1_ALT_REF_CLK>; 1159 clock-names = "core", "iface", "phy", "aux", "ref"; 1160 1161 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 1162 assigned-clock-rates = <100000000>; 1163 1164 resets = <&gcc PCIE_1_ACLK_RESET>, 1165 <&gcc PCIE_1_HCLK_RESET>, 1166 <&gcc PCIE_1_POR_RESET>, 1167 <&gcc PCIE_1_PCI_RESET>, 1168 <&gcc PCIE_1_PHY_RESET>, 1169 <&gcc PCIE_1_EXT_RESET>; 1170 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1171 1172 pinctrl-0 = <&pcie1_pins>; 1173 pinctrl-names = "default"; 1174 1175 status = "disabled"; 1176 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 1177 }; 1178 1179 pcie2: pcie@1b900000 { 1180 compatible = "qcom,pcie-ipq8064"; 1181 reg = <0x1b900000 0x1000 1182 0x1b902000 0x80 1183 0x1ba00000 0x100 1184 0x35f00000 0x100000>; 1185 reg-names = "dbi", "elbi", "parf", "config"; 1186 device_type = "pci"; 1187 linux,pci-domain = <2>; 1188 bus-range = <0x00 0xff>; 1189 num-lanes = <1>; 1190 #address-cells = <3>; 1191 #size-cells = <2>; 1192 1193 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ 1194 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ 1195 1196 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1197 interrupt-names = "msi"; 1198 #interrupt-cells = <1>; 1199 interrupt-map-mask = <0 0 0 0x7>; 1200 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1201 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1202 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1203 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1204 1205 clocks = <&gcc PCIE_2_A_CLK>, 1206 <&gcc PCIE_2_H_CLK>, 1207 <&gcc PCIE_2_PHY_CLK>, 1208 <&gcc PCIE_2_AUX_CLK>, 1209 <&gcc PCIE_2_ALT_REF_CLK>; 1210 clock-names = "core", "iface", "phy", "aux", "ref"; 1211 1212 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 1213 assigned-clock-rates = <100000000>; 1214 1215 resets = <&gcc PCIE_2_ACLK_RESET>, 1216 <&gcc PCIE_2_HCLK_RESET>, 1217 <&gcc PCIE_2_POR_RESET>, 1218 <&gcc PCIE_2_PCI_RESET>, 1219 <&gcc PCIE_2_PHY_RESET>, 1220 <&gcc PCIE_2_EXT_RESET>; 1221 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1222 1223 pinctrl-0 = <&pcie2_pins>; 1224 pinctrl-names = "default"; 1225 1226 status = "disabled"; 1227 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 1228 }; 1229 1230 qsgmii_csr: syscon@1bb00000 { 1231 compatible = "syscon"; 1232 reg = <0x1bb00000 0x000001FF>; 1233 }; 1234 1235 lcc: clock-controller@28000000 { 1236 compatible = "qcom,lcc-ipq8064"; 1237 reg = <0x28000000 0x1000>; 1238 #clock-cells = <1>; 1239 #reset-cells = <1>; 1240 }; 1241 1242 lpass@28100000 { 1243 compatible = "qcom,lpass-cpu"; 1244 status = "disabled"; 1245 clocks = <&lcc AHBIX_CLK>, 1246 <&lcc MI2S_OSR_CLK>, 1247 <&lcc MI2S_BIT_CLK>; 1248 clock-names = "ahbix-clk", 1249 "mi2s-osr-clk", 1250 "mi2s-bit-clk"; 1251 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1252 interrupt-names = "lpass-irq-lpaif"; 1253 reg = <0x28100000 0x10000>; 1254 reg-names = "lpass-lpaif"; 1255 }; 1256 1257 sata: sata@29000000 { 1258 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 1259 reg = <0x29000000 0x180>; 1260 1261 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1262 1263 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1264 <&gcc SATA_H_CLK>, 1265 <&gcc SATA_A_CLK>, 1266 <&gcc SATA_RXOOB_CLK>, 1267 <&gcc SATA_PMALIVE_CLK>; 1268 clock-names = "slave_face", "iface", "core", 1269 "rxoob", "pmalive"; 1270 1271 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 1272 assigned-clock-rates = <100000000>, <100000000>; 1273 1274 phys = <&sata_phy>; 1275 phy-names = "sata-phy"; 1276 status = "disabled"; 1277 }; 1278 1279 gmac0: ethernet@37000000 { 1280 device_type = "network"; 1281 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1282 reg = <0x37000000 0x200000>; 1283 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1284 interrupt-names = "macirq"; 1285 1286 snps,axi-config = <&stmmac_axi_setup>; 1287 snps,pbl = <32>; 1288 snps,aal; 1289 1290 qcom,nss-common = <&nss_common>; 1291 qcom,qsgmii-csr = <&qsgmii_csr>; 1292 1293 clocks = <&gcc GMAC_CORE1_CLK>; 1294 clock-names = "stmmaceth"; 1295 1296 resets = <&gcc GMAC_CORE1_RESET>, 1297 <&gcc GMAC_AHB_RESET>; 1298 reset-names = "stmmaceth", "ahb"; 1299 1300 status = "disabled"; 1301 }; 1302 1303 gmac1: ethernet@37200000 { 1304 device_type = "network"; 1305 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1306 reg = <0x37200000 0x200000>; 1307 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1308 interrupt-names = "macirq"; 1309 1310 snps,axi-config = <&stmmac_axi_setup>; 1311 snps,pbl = <32>; 1312 snps,aal; 1313 1314 qcom,nss-common = <&nss_common>; 1315 qcom,qsgmii-csr = <&qsgmii_csr>; 1316 1317 clocks = <&gcc GMAC_CORE2_CLK>; 1318 clock-names = "stmmaceth"; 1319 1320 resets = <&gcc GMAC_CORE2_RESET>, 1321 <&gcc GMAC_AHB_RESET>; 1322 reset-names = "stmmaceth", "ahb"; 1323 1324 status = "disabled"; 1325 }; 1326 1327 gmac2: ethernet@37400000 { 1328 device_type = "network"; 1329 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1330 reg = <0x37400000 0x200000>; 1331 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1332 interrupt-names = "macirq"; 1333 1334 snps,axi-config = <&stmmac_axi_setup>; 1335 snps,pbl = <32>; 1336 snps,aal; 1337 1338 qcom,nss-common = <&nss_common>; 1339 qcom,qsgmii-csr = <&qsgmii_csr>; 1340 1341 clocks = <&gcc GMAC_CORE3_CLK>; 1342 clock-names = "stmmaceth"; 1343 1344 resets = <&gcc GMAC_CORE3_RESET>, 1345 <&gcc GMAC_AHB_RESET>; 1346 reset-names = "stmmaceth", "ahb"; 1347 1348 status = "disabled"; 1349 }; 1350 1351 gmac3: ethernet@37600000 { 1352 device_type = "network"; 1353 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1354 reg = <0x37600000 0x200000>; 1355 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1356 interrupt-names = "macirq"; 1357 1358 snps,axi-config = <&stmmac_axi_setup>; 1359 snps,pbl = <32>; 1360 snps,aal; 1361 1362 qcom,nss-common = <&nss_common>; 1363 qcom,qsgmii-csr = <&qsgmii_csr>; 1364 1365 clocks = <&gcc GMAC_CORE4_CLK>; 1366 clock-names = "stmmaceth"; 1367 1368 resets = <&gcc GMAC_CORE4_RESET>, 1369 <&gcc GMAC_AHB_RESET>; 1370 reset-names = "stmmaceth", "ahb"; 1371 1372 status = "disabled"; 1373 }; 1374 }; 1375}; 1376