xref: /linux/scripts/dtc/include-prefixes/arm/qcom/qcom-apq8084.dtsi (revision a4bd03e7cb78ff743d811a09273b40d31e861def) 
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-apq8084.h>
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	model = "Qualcomm APQ 8084";
12	compatible = "qcom,apq8084";
13	interrupt-parent = <&intc>;
14
15	reserved-memory {
16		#address-cells = <1>;
17		#size-cells = <1>;
18		ranges;
19
20		smem_mem: smem_region@fa00000 {
21			reg = <0xfa00000 0x200000>;
22			no-map;
23		};
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu@0 {
31			device_type = "cpu";
32			compatible = "qcom,krait";
33			reg = <0>;
34			enable-method = "qcom,kpss-acc-v2";
35			next-level-cache = <&L2>;
36			qcom,acc = <&acc0>;
37			qcom,saw = <&saw0>;
38			cpu-idle-states = <&CPU_SPC>;
39		};
40
41		cpu@1 {
42			device_type = "cpu";
43			compatible = "qcom,krait";
44			reg = <1>;
45			enable-method = "qcom,kpss-acc-v2";
46			next-level-cache = <&L2>;
47			qcom,acc = <&acc1>;
48			qcom,saw = <&saw1>;
49			cpu-idle-states = <&CPU_SPC>;
50		};
51
52		cpu@2 {
53			device_type = "cpu";
54			compatible = "qcom,krait";
55			reg = <2>;
56			enable-method = "qcom,kpss-acc-v2";
57			next-level-cache = <&L2>;
58			qcom,acc = <&acc2>;
59			qcom,saw = <&saw2>;
60			cpu-idle-states = <&CPU_SPC>;
61		};
62
63		cpu@3 {
64			device_type = "cpu";
65			compatible = "qcom,krait";
66			reg = <3>;
67			enable-method = "qcom,kpss-acc-v2";
68			next-level-cache = <&L2>;
69			qcom,acc = <&acc3>;
70			qcom,saw = <&saw3>;
71			cpu-idle-states = <&CPU_SPC>;
72		};
73
74		L2: l2-cache {
75			compatible = "cache";
76			cache-level = <2>;
77			qcom,saw = <&saw_l2>;
78		};
79
80		idle-states {
81			CPU_SPC: spc {
82				compatible = "qcom,idle-state-spc",
83						"arm,idle-state";
84				entry-latency-us = <150>;
85				exit-latency-us = <200>;
86				min-residency-us = <2000>;
87			};
88		};
89	};
90
91	memory {
92		device_type = "memory";
93		reg = <0x0 0x0>;
94	};
95
96	firmware {
97		scm {
98			compatible = "qcom,scm-apq8084", "qcom,scm";
99			clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
100			clock-names = "core", "bus", "iface";
101		};
102	};
103
104	thermal-zones {
105		cpu0-thermal {
106			polling-delay-passive = <250>;
107			polling-delay = <1000>;
108
109			thermal-sensors = <&tsens 5>;
110
111			trips {
112				cpu_alert0: trip0 {
113					temperature = <75000>;
114					hysteresis = <2000>;
115					type = "passive";
116				};
117				cpu_crit0: trip1 {
118					temperature = <110000>;
119					hysteresis = <2000>;
120					type = "critical";
121				};
122			};
123		};
124
125		cpu1-thermal {
126			polling-delay-passive = <250>;
127			polling-delay = <1000>;
128
129			thermal-sensors = <&tsens 6>;
130
131			trips {
132				cpu_alert1: trip0 {
133					temperature = <75000>;
134					hysteresis = <2000>;
135					type = "passive";
136				};
137				cpu_crit1: trip1 {
138					temperature = <110000>;
139					hysteresis = <2000>;
140					type = "critical";
141				};
142			};
143		};
144
145		cpu2-thermal {
146			polling-delay-passive = <250>;
147			polling-delay = <1000>;
148
149			thermal-sensors = <&tsens 7>;
150
151			trips {
152				cpu_alert2: trip0 {
153					temperature = <75000>;
154					hysteresis = <2000>;
155					type = "passive";
156				};
157				cpu_crit2: trip1 {
158					temperature = <110000>;
159					hysteresis = <2000>;
160					type = "critical";
161				};
162			};
163		};
164
165		cpu3-thermal {
166			polling-delay-passive = <250>;
167			polling-delay = <1000>;
168
169			thermal-sensors = <&tsens 8>;
170
171			trips {
172				cpu_alert3: trip0 {
173					temperature = <75000>;
174					hysteresis = <2000>;
175					type = "passive";
176				};
177				cpu_crit3: trip1 {
178					temperature = <110000>;
179					hysteresis = <2000>;
180					type = "critical";
181				};
182			};
183		};
184	};
185
186	cpu-pmu {
187		compatible = "qcom,krait-pmu";
188		interrupts = <GIC_PPI 7 0xf04>;
189	};
190
191	clocks {
192		xo_board: xo_board {
193			compatible = "fixed-clock";
194			#clock-cells = <0>;
195			clock-frequency = <19200000>;
196		};
197
198		sleep_clk: sleep_clk {
199			compatible = "fixed-clock";
200			#clock-cells = <0>;
201			clock-frequency = <32768>;
202		};
203	};
204
205	timer {
206		compatible = "arm,armv7-timer";
207		interrupts = <GIC_PPI 2 0xf08>,
208			     <GIC_PPI 3 0xf08>,
209			     <GIC_PPI 4 0xf08>,
210			     <GIC_PPI 1 0xf08>;
211		clock-frequency = <19200000>;
212	};
213
214	smem {
215		compatible = "qcom,smem";
216
217		qcom,rpm-msg-ram = <&rpm_msg_ram>;
218		memory-region = <&smem_mem>;
219
220		hwlocks = <&tcsr_mutex 3>;
221	};
222
223	soc: soc {
224		#address-cells = <1>;
225		#size-cells = <1>;
226		ranges;
227		compatible = "simple-bus";
228
229		intc: interrupt-controller@f9000000 {
230			compatible = "qcom,msm-qgic2";
231			interrupt-controller;
232			#interrupt-cells = <3>;
233			reg = <0xf9000000 0x1000>,
234			      <0xf9002000 0x1000>;
235		};
236
237		apcs: syscon@f9011000 {
238			compatible = "syscon";
239			reg = <0xf9011000 0x1000>;
240		};
241
242		sram@fc190000 {
243			compatible = "qcom,apq8084-rpm-stats";
244			reg = <0xfc190000 0x10000>;
245		};
246
247		qfprom: qfprom@fc4bc000 {
248			compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
249			reg = <0xfc4bc000 0x1000>;
250			#address-cells = <1>;
251			#size-cells = <1>;
252
253			tsens_base1: base1@d0 {
254				reg = <0xd0 0x1>;
255				bits = <0 8>;
256			};
257
258			tsens_s0_p1: s0-p1@d1 {
259				reg = <0xd1 0x1>;
260				bits = <0 6>;
261			};
262
263			tsens_s1_p1: s1-p1@d2 {
264				reg = <0xd1 0x2>;
265				bits = <6 6>;
266			};
267
268			tsens_s2_p1: s2-p1@d2 {
269				reg = <0xd2 0x2>;
270				bits = <4 6>;
271			};
272
273			tsens_s3_p1: s3-p1@d3 {
274				reg = <0xd3 0x1>;
275				bits = <2 6>;
276			};
277
278			tsens_s4_p1: s4-p1@d4 {
279				reg = <0xd4 0x1>;
280				bits = <0 6>;
281			};
282
283			tsens_s5_p1: s5-p1@d4 {
284				reg = <0xd4 0x2>;
285				bits = <6 6>;
286			};
287
288			tsens_s6_p1: s6-p1@d5 {
289				reg = <0xd5 0x2>;
290				bits = <4 6>;
291			};
292
293			tsens_s7_p1: s7-p1@d6 {
294				reg = <0xd6 0x1>;
295				bits = <2 6>;
296			};
297
298			tsens_s8_p1: s8-p1@d7 {
299				reg = <0xd7 0x1>;
300				bits = <0 6>;
301			};
302
303			tsens_mode: mode@d7 {
304				reg = <0xd7 0x1>;
305				bits = <6 2>;
306			};
307
308			tsens_s9_p1: s9-p1@d8 {
309				reg = <0xd8 0x1>;
310				bits = <0 6>;
311			};
312
313			tsens_s10_p1: s10_p1@d8 {
314				reg = <0xd8 0x2>;
315				bits = <6 6>;
316			};
317
318			tsens_base2: base2@d9 {
319				reg = <0xd9 0x2>;
320				bits = <4 8>;
321			};
322
323			tsens_s0_p2: s0-p2@da {
324				reg = <0xda 0x2>;
325				bits = <4 6>;
326			};
327
328			tsens_s1_p2: s1-p2@db {
329				reg = <0xdb 0x1>;
330				bits = <2 6>;
331			};
332
333			tsens_s2_p2: s2-p2@dc {
334				reg = <0xdc 0x1>;
335				bits = <0 6>;
336			};
337
338			tsens_s3_p2: s3-p2@dc {
339				reg = <0xdc 0x2>;
340				bits = <6 6>;
341			};
342
343			tsens_s4_p2: s4-p2@dd {
344				reg = <0xdd 0x2>;
345				bits = <4 6>;
346			};
347
348			tsens_s5_p2: s5-p2@de {
349				reg = <0xde 0x2>;
350				bits = <2 6>;
351			};
352
353			tsens_s6_p2: s6-p2@df {
354				reg = <0xdf 0x1>;
355				bits = <0 6>;
356			};
357
358			tsens_s7_p2: s7-p2@e0 {
359				reg = <0xe0 0x1>;
360				bits = <0 6>;
361			};
362
363			tsens_s8_p2: s8-p2@e0 {
364				reg = <0xe0 0x2>;
365				bits = <6 6>;
366			};
367
368			tsens_s9_p2: s9-p2@e1 {
369				reg = <0xe1 0x2>;
370				bits = <4 6>;
371			};
372
373			tsens_s10_p2: s10_p2@e2 {
374				reg = <0xe2 0x2>;
375				bits = <2 6>;
376			};
377
378			tsens_s5_p2_backup: s5-p2_backup@e3 {
379				reg = <0xe3 0x2>;
380				bits = <0 6>;
381			};
382
383			tsens_mode_backup: mode_backup@e3 {
384				reg = <0xe3 0x1>;
385				bits = <6 2>;
386			};
387
388			tsens_s6_p2_backup: s6-p2_backup@e4 {
389				reg = <0xe4 0x1>;
390				bits = <0 6>;
391			};
392
393			tsens_s7_p2_backup: s7-p2_backup@e4 {
394				reg = <0xe4 0x2>;
395				bits = <6 6>;
396			};
397
398			tsens_s8_p2_backup: s8-p2_backup@e5 {
399				reg = <0xe5 0x2>;
400				bits = <4 6>;
401			};
402
403			tsens_s9_p2_backup: s9-p2_backup@e6 {
404				reg = <0xe6 0x2>;
405				bits = <2 6>;
406			};
407
408			tsens_s10_p2_backup: s10_p2_backup@e7 {
409				reg = <0xe7 0x1>;
410				bits = <0 6>;
411			};
412
413			tsens_base1_backup: base1_backup@440 {
414				reg = <0x440 0x1>;
415				bits = <0 8>;
416			};
417
418			tsens_s0_p1_backup: s0-p1_backup@441 {
419				reg = <0x441 0x1>;
420				bits = <0 6>;
421			};
422
423			tsens_s1_p1_backup: s1-p1_backup@442 {
424				reg = <0x441 0x2>;
425				bits = <6 6>;
426			};
427
428			tsens_s2_p1_backup: s2-p1_backup@442 {
429				reg = <0x442 0x2>;
430				bits = <4 6>;
431			};
432
433			tsens_s3_p1_backup: s3-p1_backup@443 {
434				reg = <0x443 0x1>;
435				bits = <2 6>;
436			};
437
438			tsens_s4_p1_backup: s4-p1_backup@444 {
439				reg = <0x444 0x1>;
440				bits = <0 6>;
441			};
442
443			tsens_s5_p1_backup: s5-p1_backup@444 {
444				reg = <0x444 0x2>;
445				bits = <6 6>;
446			};
447
448			tsens_s6_p1_backup: s6-p1_backup@445 {
449				reg = <0x445 0x2>;
450				bits = <4 6>;
451			};
452
453			tsens_s7_p1_backup: s7-p1_backup@446 {
454				reg = <0x446 0x1>;
455				bits = <2 6>;
456			};
457
458			tsens_use_backup: use_backup@447 {
459				reg = <0x447 0x1>;
460				bits = <5 3>;
461			};
462
463			tsens_s8_p1_backup: s8-p1_backup@448 {
464				reg = <0x448 0x1>;
465				bits = <0 6>;
466			};
467
468			tsens_s9_p1_backup: s9-p1_backup@448 {
469				reg = <0x448 0x2>;
470				bits = <6 6>;
471			};
472
473			tsens_s10_p1_backup: s10_p1_backup@449 {
474				reg = <0x449 0x2>;
475				bits = <4 6>;
476			};
477
478			tsens_base2_backup: base2_backup@44a {
479				reg = <0x44a 0x2>;
480				bits = <2 8>;
481			};
482
483			tsens_s0_p2_backup: s0-p2_backup@44b {
484				reg = <0x44b 0x3>;
485				bits = <2 6>;
486			};
487
488			tsens_s1_p2_backup: s1-p2_backup@44c {
489				reg = <0x44c 0x1>;
490				bits = <0 6>;
491			};
492
493			tsens_s2_p2_backup: s2-p2_backup@44c {
494				reg = <0x44c 0x2>;
495				bits = <6 6>;
496			};
497
498			tsens_s3_p2_backup: s3-p2_backup@44d {
499				reg = <0x44d 0x2>;
500				bits = <4 6>;
501			};
502
503			tsens_s4_p2_backup: s4-p2_backup@44e {
504				reg = <0x44e 0x1>;
505				bits = <2 6>;
506			};
507		};
508
509		tsens: thermal-sensor@fc4a9000 {
510			compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
511			reg = <0xfc4a9000 0x1000>, /* TM */
512			      <0xfc4a8000 0x1000>; /* SROT */
513			nvmem-cells = <&tsens_mode>,
514				      <&tsens_base1>, <&tsens_base2>,
515				      <&tsens_use_backup>,
516				      <&tsens_mode_backup>,
517				      <&tsens_base1_backup>, <&tsens_base2_backup>,
518				      <&tsens_s0_p1>, <&tsens_s0_p2>,
519				      <&tsens_s1_p1>, <&tsens_s1_p2>,
520				      <&tsens_s2_p1>, <&tsens_s2_p2>,
521				      <&tsens_s3_p1>, <&tsens_s3_p2>,
522				      <&tsens_s4_p1>, <&tsens_s4_p2>,
523				      <&tsens_s5_p1>, <&tsens_s5_p2>,
524				      <&tsens_s6_p1>, <&tsens_s6_p2>,
525				      <&tsens_s7_p1>, <&tsens_s7_p2>,
526				      <&tsens_s8_p1>, <&tsens_s8_p2>,
527				      <&tsens_s9_p1>, <&tsens_s9_p2>,
528				      <&tsens_s10_p1>, <&tsens_s10_p2>,
529				      <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
530				      <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
531				      <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
532				      <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
533				      <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
534				      <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
535				      <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
536				      <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
537				      <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
538				      <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
539				      <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
540			nvmem-cell-names = "mode",
541					   "base1", "base2",
542					   "use_backup",
543					   "mode_backup",
544					   "base1_backup", "base2_backup",
545					   "s0_p1", "s0_p2",
546					   "s1_p1", "s1_p2",
547					   "s2_p1", "s2_p2",
548					   "s3_p1", "s3_p2",
549					   "s4_p1", "s4_p2",
550					   "s5_p1", "s5_p2",
551					   "s6_p1", "s6_p2",
552					   "s7_p1", "s7_p2",
553					   "s8_p1", "s8_p2",
554					   "s9_p1", "s9_p2",
555					   "s10_p1", "s10_p2",
556					   "s0_p1_backup", "s0_p2_backup",
557					   "s1_p1_backup", "s1_p2_backup",
558					   "s2_p1_backup", "s2_p2_backup",
559					   "s3_p1_backup", "s3_p2_backup",
560					   "s4_p1_backup", "s4_p2_backup",
561					   "s5_p1_backup", "s5_p2_backup",
562					   "s6_p1_backup", "s6_p2_backup",
563					   "s7_p1_backup", "s7_p2_backup",
564					   "s8_p1_backup", "s8_p2_backup",
565					   "s9_p1_backup", "s9_p2_backup",
566					   "s10_p1_backup", "s10_p2_backup";
567			#qcom,sensors = <11>;
568			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
569			interrupt-names = "uplow";
570			#thermal-sensor-cells = <1>;
571		};
572		timer@f9020000 {
573			#address-cells = <1>;
574			#size-cells = <1>;
575			ranges;
576			compatible = "arm,armv7-timer-mem";
577			reg = <0xf9020000 0x1000>;
578			clock-frequency = <19200000>;
579
580			frame@f9021000 {
581				frame-number = <0>;
582				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
583					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
584				reg = <0xf9021000 0x1000>,
585				      <0xf9022000 0x1000>;
586			};
587
588			frame@f9023000 {
589				frame-number = <1>;
590				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
591				reg = <0xf9023000 0x1000>;
592				status = "disabled";
593			};
594
595			frame@f9024000 {
596				frame-number = <2>;
597				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
598				reg = <0xf9024000 0x1000>;
599				status = "disabled";
600			};
601
602			frame@f9025000 {
603				frame-number = <3>;
604				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
605				reg = <0xf9025000 0x1000>;
606				status = "disabled";
607			};
608
609			frame@f9026000 {
610				frame-number = <4>;
611				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
612				reg = <0xf9026000 0x1000>;
613				status = "disabled";
614			};
615
616			frame@f9027000 {
617				frame-number = <5>;
618				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
619				reg = <0xf9027000 0x1000>;
620				status = "disabled";
621			};
622
623			frame@f9028000 {
624				frame-number = <6>;
625				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
626				reg = <0xf9028000 0x1000>;
627				status = "disabled";
628			};
629		};
630
631		saw0: power-controller@f9089000 {
632			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
633			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
634		};
635
636		saw1: power-controller@f9099000 {
637			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
638			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
639		};
640
641		saw2: power-controller@f90a9000 {
642			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
643			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
644		};
645
646		saw3: power-controller@f90b9000 {
647			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
648			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
649		};
650
651		saw_l2: power-controller@f9012000 {
652			compatible = "qcom,saw2";
653			reg = <0xf9012000 0x1000>;
654			regulator;
655		};
656
657		acc0: power-manager@f9088000 {
658			compatible = "qcom,kpss-acc-v2";
659			reg = <0xf9088000 0x1000>,
660			      <0xf9008000 0x1000>;
661		};
662
663		acc1: power-manager@f9098000 {
664			compatible = "qcom,kpss-acc-v2";
665			reg = <0xf9098000 0x1000>,
666			      <0xf9008000 0x1000>;
667		};
668
669		acc2: power-manager@f90a8000 {
670			compatible = "qcom,kpss-acc-v2";
671			reg = <0xf90a8000 0x1000>,
672			      <0xf9008000 0x1000>;
673		};
674
675		acc3: power-manager@f90b8000 {
676			compatible = "qcom,kpss-acc-v2";
677			reg = <0xf90b8000 0x1000>,
678			      <0xf9008000 0x1000>;
679		};
680
681		restart@fc4ab000 {
682			compatible = "qcom,pshold";
683			reg = <0xfc4ab000 0x4>;
684		};
685
686		gcc: clock-controller@fc400000 {
687			compatible = "qcom,gcc-apq8084";
688			#clock-cells = <1>;
689			#reset-cells = <1>;
690			#power-domain-cells = <1>;
691			reg = <0xfc400000 0x4000>;
692			clocks = <&xo_board>,
693				 <&sleep_clk>,
694				 <0>, /* ufs */
695				 <0>,
696				 <0>,
697				 <0>,
698				 <0>, /* sata */
699				 <0>,
700				 <0>; /* pcie */
701			clock-names = "xo",
702				      "sleep_clk",
703				      "ufs_rx_symbol_0_clk_src",
704				      "ufs_rx_symbol_1_clk_src",
705				      "ufs_tx_symbol_0_clk_src",
706				      "ufs_tx_symbol_1_clk_src",
707				      "sata_asic0_clk",
708				      "sata_rx_clk",
709				      "pcie_pipe";
710		};
711
712		tcsr_mutex: hwlock@fd484000 {
713			compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
714			reg = <0xfd484000 0x1000>;
715			#hwlock-cells = <1>;
716		};
717
718		rpm_msg_ram: sram@fc428000 {
719			compatible = "qcom,rpm-msg-ram";
720			reg = <0xfc428000 0x4000>;
721		};
722
723		tlmm: pinctrl@fd510000 {
724			compatible = "qcom,apq8084-pinctrl";
725			reg = <0xfd510000 0x4000>;
726			gpio-controller;
727			gpio-ranges = <&tlmm 0 0 147>;
728			#gpio-cells = <2>;
729			interrupt-controller;
730			#interrupt-cells = <2>;
731			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
732		};
733
734		blsp2_uart2: serial@f995e000 {
735			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
736			reg = <0xf995e000 0x1000>;
737			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
738			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
739			clock-names = "core", "iface";
740			status = "disabled";
741		};
742
743		sdhc_1: mmc@f9824900 {
744			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
745			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
746			reg-names = "hc", "core";
747			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
748			interrupt-names = "hc_irq", "pwr_irq";
749			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
750				 <&gcc GCC_SDCC1_APPS_CLK>,
751				 <&xo_board>;
752			clock-names = "iface", "core", "xo";
753			status = "disabled";
754		};
755
756		sdhc_2: mmc@f98a4900 {
757			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
758			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
759			reg-names = "hc", "core";
760			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
761			interrupt-names = "hc_irq", "pwr_irq";
762			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
763				 <&gcc GCC_SDCC2_APPS_CLK>,
764				 <&xo_board>;
765			clock-names = "iface", "core", "xo";
766			status = "disabled";
767		};
768
769		spmi_bus: spmi@fc4cf000 {
770			compatible = "qcom,spmi-pmic-arb";
771			reg-names = "core", "intr", "cnfg";
772			reg = <0xfc4cf000 0x1000>,
773			      <0xfc4cb000 0x1000>,
774			      <0xfc4ca000 0x1000>;
775			interrupt-names = "periph_irq";
776			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
777			qcom,ee = <0>;
778			qcom,channel = <0>;
779			#address-cells = <2>;
780			#size-cells = <0>;
781			interrupt-controller;
782			#interrupt-cells = <4>;
783		};
784	};
785
786	smd {
787		compatible = "qcom,smd";
788
789		rpm {
790			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
791			qcom,ipc = <&apcs 8 0>;
792			qcom,smd-edge = <15>;
793
794			rpm-requests {
795				compatible = "qcom,rpm-apq8084";
796				qcom,smd-channels = "rpm_requests";
797
798				regulators-0 {
799					compatible = "qcom,rpm-pma8084-regulators";
800
801					pma8084_s1: s1 {};
802					pma8084_s2: s2 {};
803					pma8084_s3: s3 {};
804					pma8084_s4: s4 {};
805					pma8084_s5: s5 {};
806					pma8084_s6: s6 {};
807					pma8084_s7: s7 {};
808					pma8084_s8: s8 {};
809					pma8084_s9: s9 {};
810					pma8084_s10: s10 {};
811					pma8084_s11: s11 {};
812					pma8084_s12: s12 {};
813
814					pma8084_l1: l1 {};
815					pma8084_l2: l2 {};
816					pma8084_l3: l3 {};
817					pma8084_l4: l4 {};
818					pma8084_l5: l5 {};
819					pma8084_l6: l6 {};
820					pma8084_l7: l7 {};
821					pma8084_l8: l8 {};
822					pma8084_l9: l9 {};
823					pma8084_l10: l10 {};
824					pma8084_l11: l11 {};
825					pma8084_l12: l12 {};
826					pma8084_l13: l13 {};
827					pma8084_l14: l14 {};
828					pma8084_l15: l15 {};
829					pma8084_l16: l16 {};
830					pma8084_l17: l17 {};
831					pma8084_l18: l18 {};
832					pma8084_l19: l19 {};
833					pma8084_l20: l20 {};
834					pma8084_l21: l21 {};
835					pma8084_l22: l22 {};
836					pma8084_l23: l23 {};
837					pma8084_l24: l24 {};
838					pma8084_l25: l25 {};
839					pma8084_l26: l26 {};
840					pma8084_l27: l27 {};
841
842					pma8084_lvs1: lvs1 {};
843					pma8084_lvs2: lvs2 {};
844					pma8084_lvs3: lvs3 {};
845					pma8084_lvs4: lvs4 {};
846
847					pma8084_5vs1: 5vs1 {};
848				};
849			};
850		};
851	};
852};
853