1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,lcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm APQ8064"; 16 compatible = "qcom,apq8064"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 smem_region: smem@80000000 { 25 reg = <0x80000000 0x200000>; 26 no-map; 27 }; 28 29 wcnss_mem: wcnss@8f000000 { 30 reg = <0x8f000000 0x700000>; 31 no-map; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v1"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&L2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&CPU_SPC>; 48 }; 49 50 CPU1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v1"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&L2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&CPU_SPC>; 59 }; 60 61 CPU2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v1"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&L2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&CPU_SPC>; 70 }; 71 72 CPU3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v1"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&L2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&CPU_SPC>; 81 }; 82 83 L2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 CPU_SPC: spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <400>; 94 exit-latency-us = <900>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 }; 99 100 memory@0 { 101 device_type = "memory"; 102 reg = <0x0 0x0>; 103 }; 104 105 thermal-zones { 106 cpu0-thermal { 107 polling-delay-passive = <250>; 108 polling-delay = <1000>; 109 110 thermal-sensors = <&tsens 7>; 111 coefficients = <1199 0>; 112 113 trips { 114 cpu_alert0: trip0 { 115 temperature = <75000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 cpu_crit0: trip1 { 120 temperature = <110000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 }; 125 }; 126 127 cpu1-thermal { 128 polling-delay-passive = <250>; 129 polling-delay = <1000>; 130 131 thermal-sensors = <&tsens 8>; 132 coefficients = <1132 0>; 133 134 trips { 135 cpu_alert1: trip0 { 136 temperature = <75000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 cpu_crit1: trip1 { 141 temperature = <110000>; 142 hysteresis = <2000>; 143 type = "critical"; 144 }; 145 }; 146 }; 147 148 cpu2-thermal { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens 9>; 153 coefficients = <1199 0>; 154 155 trips { 156 cpu_alert2: trip0 { 157 temperature = <75000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 cpu_crit2: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu3-thermal { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens 10>; 174 coefficients = <1132 0>; 175 176 trips { 177 cpu_alert3: trip0 { 178 temperature = <75000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 cpu_crit3: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 }; 190 191 cpu-pmu { 192 compatible = "qcom,krait-pmu"; 193 interrupts = <1 10 0x304>; 194 }; 195 196 clocks { 197 cxo_board: cxo_board { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <19200000>; 201 }; 202 203 pxo_board: pxo_board { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <27000000>; 207 }; 208 209 sleep_clk: sleep_clk { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32768>; 213 }; 214 }; 215 216 sfpb_mutex: hwmutex { 217 compatible = "qcom,sfpb-mutex"; 218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 219 #hwlock-cells = <1>; 220 }; 221 222 smem { 223 compatible = "qcom,smem"; 224 memory-region = <&smem_region>; 225 226 hwlocks = <&sfpb_mutex 3>; 227 }; 228 229 smsm { 230 compatible = "qcom,smsm"; 231 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 qcom,ipc-1 = <&l2cc 8 4>; 236 qcom,ipc-2 = <&l2cc 8 14>; 237 qcom,ipc-3 = <&l2cc 8 23>; 238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 239 240 apps_smsm: apps@0 { 241 reg = <0>; 242 #qcom,smem-state-cells = <1>; 243 }; 244 245 modem_smsm: modem@1 { 246 reg = <1>; 247 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; 248 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 253 q6_smsm: q6@2 { 254 reg = <2>; 255 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; 256 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 }; 260 261 wcnss_smsm: wcnss@3 { 262 reg = <3>; 263 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; 264 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 }; 268 269 dsps_smsm: dsps@4 { 270 reg = <4>; 271 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; 272 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 }; 276 }; 277 278 firmware { 279 scm { 280 compatible = "qcom,scm-apq8064", "qcom,scm"; 281 282 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 283 clock-names = "core"; 284 }; 285 }; 286 287 288 /* 289 * These channels from the ADC are simply hardware monitors. 290 * That is why the ADC is referred to as "HKADC" - HouseKeeping 291 * ADC. 292 */ 293 iio-hwmon { 294 compatible = "iio-hwmon"; 295 io-channels = <&xoadc 0x00 0x01>, /* Battery */ 296 <&xoadc 0x00 0x02>, /* DC in (charger) */ 297 <&xoadc 0x00 0x04>, /* VPH the main system voltage */ 298 <&xoadc 0x00 0x0b>, /* Die temperature */ 299 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 300 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 301 <&xoadc 0x00 0x0e>; /* Charger temperature */ 302 }; 303 304 soc: soc { 305 #address-cells = <1>; 306 #size-cells = <1>; 307 ranges; 308 compatible = "simple-bus"; 309 310 tlmm_pinmux: pinctrl@800000 { 311 compatible = "qcom,apq8064-pinctrl"; 312 reg = <0x800000 0x4000>; 313 314 gpio-controller; 315 gpio-ranges = <&tlmm_pinmux 0 0 90>; 316 #gpio-cells = <2>; 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 320 321 pinctrl-names = "default"; 322 pinctrl-0 = <&ps_hold>; 323 }; 324 325 sfpb_wrapper_mutex: syscon@1200000 { 326 compatible = "syscon"; 327 reg = <0x01200000 0x8000>; 328 }; 329 330 intc: interrupt-controller@2000000 { 331 compatible = "qcom,msm-qgic2"; 332 interrupt-controller; 333 #interrupt-cells = <3>; 334 reg = <0x02000000 0x1000>, 335 <0x02002000 0x1000>; 336 }; 337 338 timer@200a000 { 339 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", 340 "qcom,msm-timer"; 341 interrupts = <1 1 0x301>, 342 <1 2 0x301>, 343 <1 3 0x301>; 344 reg = <0x0200a000 0x100>; 345 clock-frequency = <27000000>; 346 cpu-offset = <0x80000>; 347 }; 348 349 acc0: clock-controller@2088000 { 350 compatible = "qcom,kpss-acc-v1"; 351 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 352 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 353 clock-names = "pll8_vote", "pxo"; 354 clock-output-names = "acpu0_aux"; 355 #clock-cells = <0>; 356 }; 357 358 acc1: clock-controller@2098000 { 359 compatible = "qcom,kpss-acc-v1"; 360 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 361 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 362 clock-names = "pll8_vote", "pxo"; 363 clock-output-names = "acpu1_aux"; 364 #clock-cells = <0>; 365 }; 366 367 acc2: clock-controller@20a8000 { 368 compatible = "qcom,kpss-acc-v1"; 369 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 370 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 371 clock-names = "pll8_vote", "pxo"; 372 clock-output-names = "acpu2_aux"; 373 #clock-cells = <0>; 374 }; 375 376 acc3: clock-controller@20b8000 { 377 compatible = "qcom,kpss-acc-v1"; 378 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 379 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 380 clock-names = "pll8_vote", "pxo"; 381 clock-output-names = "acpu3_aux"; 382 #clock-cells = <0>; 383 }; 384 385 saw0: power-controller@2089000 { 386 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 387 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 388 regulator; 389 }; 390 391 saw1: power-controller@2099000 { 392 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 393 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 394 regulator; 395 }; 396 397 saw2: power-controller@20a9000 { 398 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 399 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 400 regulator; 401 }; 402 403 saw3: power-controller@20b9000 { 404 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 405 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 406 regulator; 407 }; 408 409 sps_sic_non_secure: sps-sic-non-secure@12100000 { 410 compatible = "syscon"; 411 reg = <0x12100000 0x10000>; 412 }; 413 414 gsbi1: gsbi@12440000 { 415 status = "disabled"; 416 compatible = "qcom,gsbi-v1.0.0"; 417 cell-index = <1>; 418 reg = <0x12440000 0x100>; 419 clocks = <&gcc GSBI1_H_CLK>; 420 clock-names = "iface"; 421 #address-cells = <1>; 422 #size-cells = <1>; 423 ranges; 424 425 syscon-tcsr = <&tcsr>; 426 427 gsbi1_serial: serial@12450000 { 428 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 429 reg = <0x12450000 0x100>, 430 <0x12400000 0x03>; 431 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 433 clock-names = "core", "iface"; 434 status = "disabled"; 435 }; 436 437 gsbi1_i2c: i2c@12460000 { 438 compatible = "qcom,i2c-qup-v1.1.1"; 439 pinctrl-0 = <&i2c1_pins>; 440 pinctrl-1 = <&i2c1_pins_sleep>; 441 pinctrl-names = "default", "sleep"; 442 reg = <0x12460000 0x1000>; 443 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 445 clock-names = "core", "iface"; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 status = "disabled"; 449 }; 450 451 }; 452 453 gsbi2: gsbi@12480000 { 454 status = "disabled"; 455 compatible = "qcom,gsbi-v1.0.0"; 456 cell-index = <2>; 457 reg = <0x12480000 0x100>; 458 clocks = <&gcc GSBI2_H_CLK>; 459 clock-names = "iface"; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 ranges; 463 464 syscon-tcsr = <&tcsr>; 465 466 gsbi2_i2c: i2c@124a0000 { 467 compatible = "qcom,i2c-qup-v1.1.1"; 468 reg = <0x124a0000 0x1000>; 469 pinctrl-0 = <&i2c2_pins>; 470 pinctrl-1 = <&i2c2_pins_sleep>; 471 pinctrl-names = "default", "sleep"; 472 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 474 clock-names = "core", "iface"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 status = "disabled"; 478 }; 479 }; 480 481 gsbi3: gsbi@16200000 { 482 status = "disabled"; 483 compatible = "qcom,gsbi-v1.0.0"; 484 cell-index = <3>; 485 reg = <0x16200000 0x100>; 486 clocks = <&gcc GSBI3_H_CLK>; 487 clock-names = "iface"; 488 #address-cells = <1>; 489 #size-cells = <1>; 490 ranges; 491 gsbi3_i2c: i2c@16280000 { 492 compatible = "qcom,i2c-qup-v1.1.1"; 493 pinctrl-0 = <&i2c3_pins>; 494 pinctrl-1 = <&i2c3_pins_sleep>; 495 pinctrl-names = "default", "sleep"; 496 reg = <0x16280000 0x1000>; 497 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&gcc GSBI3_QUP_CLK>, 499 <&gcc GSBI3_H_CLK>; 500 clock-names = "core", "iface"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "disabled"; 504 }; 505 }; 506 507 gsbi4: gsbi@16300000 { 508 status = "disabled"; 509 compatible = "qcom,gsbi-v1.0.0"; 510 cell-index = <4>; 511 reg = <0x16300000 0x03>; 512 clocks = <&gcc GSBI4_H_CLK>; 513 clock-names = "iface"; 514 #address-cells = <1>; 515 #size-cells = <1>; 516 ranges; 517 518 gsbi4_i2c: i2c@16380000 { 519 compatible = "qcom,i2c-qup-v1.1.1"; 520 pinctrl-0 = <&i2c4_pins>; 521 pinctrl-1 = <&i2c4_pins_sleep>; 522 pinctrl-names = "default", "sleep"; 523 reg = <0x16380000 0x1000>; 524 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&gcc GSBI4_QUP_CLK>, 526 <&gcc GSBI4_H_CLK>; 527 clock-names = "core", "iface"; 528 status = "disabled"; 529 }; 530 }; 531 532 gsbi5: gsbi@1a200000 { 533 status = "disabled"; 534 compatible = "qcom,gsbi-v1.0.0"; 535 cell-index = <5>; 536 reg = <0x1a200000 0x03>; 537 clocks = <&gcc GSBI5_H_CLK>; 538 clock-names = "iface"; 539 #address-cells = <1>; 540 #size-cells = <1>; 541 ranges; 542 543 gsbi5_serial: serial@1a240000 { 544 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 545 reg = <0x1a240000 0x100>, 546 <0x1a200000 0x03>; 547 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 549 clock-names = "core", "iface"; 550 status = "disabled"; 551 }; 552 553 gsbi5_spi: spi@1a280000 { 554 compatible = "qcom,spi-qup-v1.1.1"; 555 reg = <0x1a280000 0x1000>; 556 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 557 pinctrl-0 = <&spi5_default>; 558 pinctrl-1 = <&spi5_sleep>; 559 pinctrl-names = "default", "sleep"; 560 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 561 clock-names = "core", "iface"; 562 status = "disabled"; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 }; 566 }; 567 568 gsbi6: gsbi@16500000 { 569 status = "disabled"; 570 compatible = "qcom,gsbi-v1.0.0"; 571 cell-index = <6>; 572 reg = <0x16500000 0x03>; 573 clocks = <&gcc GSBI6_H_CLK>; 574 clock-names = "iface"; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 ranges; 578 579 gsbi6_serial: serial@16540000 { 580 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 581 reg = <0x16540000 0x100>, 582 <0x16500000 0x03>; 583 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 585 clock-names = "core", "iface"; 586 status = "disabled"; 587 }; 588 589 gsbi6_i2c: i2c@16580000 { 590 compatible = "qcom,i2c-qup-v1.1.1"; 591 pinctrl-0 = <&i2c6_pins>; 592 pinctrl-1 = <&i2c6_pins_sleep>; 593 pinctrl-names = "default", "sleep"; 594 reg = <0x16580000 0x1000>; 595 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&gcc GSBI6_QUP_CLK>, 597 <&gcc GSBI6_H_CLK>; 598 clock-names = "core", "iface"; 599 status = "disabled"; 600 }; 601 }; 602 603 gsbi7: gsbi@16600000 { 604 status = "disabled"; 605 compatible = "qcom,gsbi-v1.0.0"; 606 cell-index = <7>; 607 reg = <0x16600000 0x100>; 608 clocks = <&gcc GSBI7_H_CLK>; 609 clock-names = "iface"; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges; 613 syscon-tcsr = <&tcsr>; 614 615 gsbi7_serial: serial@16640000 { 616 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 617 reg = <0x16640000 0x1000>, 618 <0x16600000 0x1000>; 619 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 621 clock-names = "core", "iface"; 622 status = "disabled"; 623 }; 624 625 gsbi7_i2c: i2c@16680000 { 626 compatible = "qcom,i2c-qup-v1.1.1"; 627 pinctrl-0 = <&i2c7_pins>; 628 pinctrl-1 = <&i2c7_pins_sleep>; 629 pinctrl-names = "default", "sleep"; 630 reg = <0x16680000 0x1000>; 631 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&gcc GSBI7_QUP_CLK>, 633 <&gcc GSBI7_H_CLK>; 634 clock-names = "core", "iface"; 635 status = "disabled"; 636 }; 637 }; 638 639 rng@1a500000 { 640 compatible = "qcom,prng"; 641 reg = <0x1a500000 0x200>; 642 clocks = <&gcc PRNG_CLK>; 643 clock-names = "core"; 644 }; 645 646 ssbi@c00000 { 647 compatible = "qcom,ssbi"; 648 reg = <0x00c00000 0x1000>; 649 qcom,controller-type = "pmic-arbiter"; 650 651 pm8821: pmic { 652 compatible = "qcom,pm8821"; 653 interrupt-parent = <&tlmm_pinmux>; 654 interrupts = <76 IRQ_TYPE_LEVEL_LOW>; 655 #interrupt-cells = <2>; 656 interrupt-controller; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 pm8821_mpps: mpps@50 { 661 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; 662 reg = <0x50>; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 gpio-controller; 666 #gpio-cells = <2>; 667 gpio-ranges = <&pm8821_mpps 0 0 4>; 668 }; 669 }; 670 }; 671 672 ssbi@500000 { 673 compatible = "qcom,ssbi"; 674 reg = <0x00500000 0x1000>; 675 qcom,controller-type = "pmic-arbiter"; 676 677 pmicintc: pmic { 678 compatible = "qcom,pm8921"; 679 interrupt-parent = <&tlmm_pinmux>; 680 interrupts = <74 8>; 681 #interrupt-cells = <2>; 682 interrupt-controller; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 686 pm8921_gpio: gpio@150 { 687 688 compatible = "qcom,pm8921-gpio", 689 "qcom,ssbi-gpio"; 690 reg = <0x150>; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 gpio-controller; 694 gpio-ranges = <&pm8921_gpio 0 0 44>; 695 #gpio-cells = <2>; 696 697 }; 698 699 pm8921_mpps: mpps@50 { 700 compatible = "qcom,pm8921-mpp", 701 "qcom,ssbi-mpp"; 702 reg = <0x50>; 703 gpio-controller; 704 #gpio-cells = <2>; 705 gpio-ranges = <&pm8921_mpps 0 0 12>; 706 interrupt-controller; 707 #interrupt-cells = <2>; 708 }; 709 710 rtc@11d { 711 compatible = "qcom,pm8921-rtc"; 712 interrupt-parent = <&pmicintc>; 713 interrupts = <39 1>; 714 reg = <0x11d>; 715 allow-set-time; 716 }; 717 718 pwrkey@1c { 719 compatible = "qcom,pm8921-pwrkey"; 720 reg = <0x1c>; 721 interrupt-parent = <&pmicintc>; 722 interrupts = <50 1>, <51 1>; 723 debounce = <15625>; 724 pull-up; 725 }; 726 727 xoadc: xoadc@197 { 728 compatible = "qcom,pm8921-adc"; 729 reg = <197>; 730 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; 731 #address-cells = <2>; 732 #size-cells = <0>; 733 #io-channel-cells = <2>; 734 735 vcoin: adc-channel@0 { 736 reg = <0x00 0x00>; 737 }; 738 vbat: adc-channel@1 { 739 reg = <0x00 0x01>; 740 }; 741 dcin: adc-channel@2 { 742 reg = <0x00 0x02>; 743 }; 744 vph_pwr: adc-channel@4 { 745 reg = <0x00 0x04>; 746 }; 747 batt_therm: adc-channel@8 { 748 reg = <0x00 0x08>; 749 }; 750 batt_id: adc-channel@9 { 751 reg = <0x00 0x09>; 752 }; 753 usb_vbus: adc-channel@a { 754 reg = <0x00 0x0a>; 755 }; 756 die_temp: adc-channel@b { 757 reg = <0x00 0x0b>; 758 }; 759 ref_625mv: adc-channel@c { 760 reg = <0x00 0x0c>; 761 }; 762 ref_1250mv: adc-channel@d { 763 reg = <0x00 0x0d>; 764 }; 765 chg_temp: adc-channel@e { 766 reg = <0x00 0x0e>; 767 }; 768 ref_muxoff: adc-channel@f { 769 reg = <0x00 0x0f>; 770 }; 771 }; 772 }; 773 }; 774 775 qfprom: qfprom@700000 { 776 compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 777 reg = <0x00700000 0x1000>; 778 #address-cells = <1>; 779 #size-cells = <1>; 780 ranges; 781 tsens_calib: calib@404 { 782 reg = <0x404 0x10>; 783 }; 784 tsens_backup: backup_calib@414 { 785 reg = <0x414 0x10>; 786 }; 787 }; 788 789 gcc: clock-controller@900000 { 790 compatible = "qcom,gcc-apq8064", "syscon"; 791 reg = <0x00900000 0x4000>; 792 #clock-cells = <1>; 793 #power-domain-cells = <1>; 794 #reset-cells = <1>; 795 clocks = <&cxo_board>, 796 <&pxo_board>, 797 <&lcc PLL4>; 798 clock-names = "cxo", "pxo", "pll4"; 799 800 tsens: thermal-sensor { 801 compatible = "qcom,msm8960-tsens"; 802 803 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 804 nvmem-cell-names = "calib", "calib_backup"; 805 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 806 interrupt-names = "uplow"; 807 808 #qcom,sensors = <11>; 809 #thermal-sensor-cells = <1>; 810 }; 811 }; 812 813 lcc: clock-controller@28000000 { 814 compatible = "qcom,lcc-apq8064"; 815 reg = <0x28000000 0x1000>; 816 #clock-cells = <1>; 817 #reset-cells = <1>; 818 clocks = <&pxo_board>, 819 <&gcc PLL4_VOTE>, 820 <0>, 821 <0>, <0>, 822 <0>, <0>, 823 <0>; 824 clock-names = "pxo", 825 "pll4_vote", 826 "mi2s_codec_clk", 827 "codec_i2s_mic_codec_clk", 828 "spare_i2s_mic_codec_clk", 829 "codec_i2s_spkr_codec_clk", 830 "spare_i2s_spkr_codec_clk", 831 "pcm_codec_clk"; 832 }; 833 834 mmcc: clock-controller@4000000 { 835 compatible = "qcom,mmcc-apq8064"; 836 reg = <0x4000000 0x1000>; 837 #clock-cells = <1>; 838 #power-domain-cells = <1>; 839 #reset-cells = <1>; 840 clocks = <&pxo_board>, 841 <&gcc PLL3>, 842 <&gcc PLL8_VOTE>, 843 <&dsi0_phy 1>, 844 <&dsi0_phy 0>, 845 <&dsi1_phy 1>, 846 <&dsi1_phy 0>, 847 <&hdmi_phy>; 848 clock-names = "pxo", 849 "pll3", 850 "pll8_vote", 851 "dsi1pll", 852 "dsi1pllbyte", 853 "dsi2pll", 854 "dsi2pllbyte", 855 "hdmipll"; 856 }; 857 858 l2cc: clock-controller@2011000 { 859 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 860 reg = <0x2011000 0x1000>; 861 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 862 clock-names = "pll8_vote", "pxo"; 863 #clock-cells = <0>; 864 }; 865 866 rpm: rpm@108000 { 867 compatible = "qcom,rpm-apq8064"; 868 reg = <0x108000 0x1000>; 869 qcom,ipc = <&l2cc 0x8 2>; 870 871 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 872 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 873 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 874 interrupt-names = "ack", "err", "wakeup"; 875 876 rpmcc: clock-controller { 877 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 878 #clock-cells = <1>; 879 clocks = <&pxo_board>, <&cxo_board>; 880 clock-names = "pxo", "cxo"; 881 }; 882 883 regulators { 884 compatible = "qcom,rpm-pm8921-regulators"; 885 886 pm8921_s1: s1 {}; 887 pm8921_s2: s2 {}; 888 pm8921_s3: s3 {}; 889 pm8921_s4: s4 {}; 890 pm8921_s7: s7 {}; 891 pm8921_s8: s8 {}; 892 893 pm8921_l1: l1 {}; 894 pm8921_l2: l2 {}; 895 pm8921_l3: l3 {}; 896 pm8921_l4: l4 {}; 897 pm8921_l5: l5 {}; 898 pm8921_l6: l6 {}; 899 pm8921_l7: l7 {}; 900 pm8921_l8: l8 {}; 901 pm8921_l9: l9 {}; 902 pm8921_l10: l10 {}; 903 pm8921_l11: l11 {}; 904 pm8921_l12: l12 {}; 905 pm8921_l14: l14 {}; 906 pm8921_l15: l15 {}; 907 pm8921_l16: l16 {}; 908 pm8921_l17: l17 {}; 909 pm8921_l18: l18 {}; 910 pm8921_l21: l21 {}; 911 pm8921_l22: l22 {}; 912 pm8921_l23: l23 {}; 913 pm8921_l24: l24 {}; 914 pm8921_l25: l25 {}; 915 pm8921_l26: l26 {}; 916 pm8921_l27: l27 {}; 917 pm8921_l28: l28 {}; 918 pm8921_l29: l29 {}; 919 920 pm8921_lvs1: lvs1 {}; 921 pm8921_lvs2: lvs2 {}; 922 pm8921_lvs3: lvs3 {}; 923 pm8921_lvs4: lvs4 {}; 924 pm8921_lvs5: lvs5 {}; 925 pm8921_lvs6: lvs6 {}; 926 pm8921_lvs7: lvs7 {}; 927 928 pm8921_usb_switch: usb-switch {}; 929 930 pm8921_hdmi_switch: hdmi-switch { 931 bias-pull-down; 932 }; 933 934 pm8921_ncp: ncp {}; 935 }; 936 }; 937 938 usb1: usb@12500000 { 939 compatible = "qcom,ci-hdrc"; 940 reg = <0x12500000 0x200>, 941 <0x12500200 0x200>; 942 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 944 clock-names = "core", "iface"; 945 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 946 assigned-clock-rates = <60000000>; 947 resets = <&gcc USB_HS1_RESET>; 948 reset-names = "core"; 949 phy_type = "ulpi"; 950 ahb-burst-config = <0>; 951 phys = <&usb_hs1_phy>; 952 phy-names = "usb-phy"; 953 status = "disabled"; 954 #reset-cells = <1>; 955 956 ulpi { 957 usb_hs1_phy: phy { 958 compatible = "qcom,usb-hs-phy-apq8064", 959 "qcom,usb-hs-phy"; 960 clocks = <&sleep_clk>, <&cxo_board>; 961 clock-names = "sleep", "ref"; 962 resets = <&usb1 0>; 963 reset-names = "por"; 964 #phy-cells = <0>; 965 }; 966 }; 967 }; 968 969 usb3: usb@12520000 { 970 compatible = "qcom,ci-hdrc"; 971 reg = <0x12520000 0x200>, 972 <0x12520200 0x200>; 973 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 975 clock-names = "core", "iface"; 976 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 977 assigned-clock-rates = <60000000>; 978 resets = <&gcc USB_HS3_RESET>; 979 reset-names = "core"; 980 phy_type = "ulpi"; 981 ahb-burst-config = <0>; 982 phys = <&usb_hs3_phy>; 983 phy-names = "usb-phy"; 984 status = "disabled"; 985 #reset-cells = <1>; 986 987 ulpi { 988 usb_hs3_phy: phy { 989 compatible = "qcom,usb-hs-phy-apq8064", 990 "qcom,usb-hs-phy"; 991 #phy-cells = <0>; 992 clocks = <&sleep_clk>, <&cxo_board>; 993 clock-names = "sleep", "ref"; 994 resets = <&usb3 0>; 995 reset-names = "por"; 996 }; 997 }; 998 }; 999 1000 usb4: usb@12530000 { 1001 compatible = "qcom,ci-hdrc"; 1002 reg = <0x12530000 0x200>, 1003 <0x12530200 0x200>; 1004 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 1006 clock-names = "core", "iface"; 1007 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 1008 assigned-clock-rates = <60000000>; 1009 resets = <&gcc USB_HS4_RESET>; 1010 reset-names = "core"; 1011 phy_type = "ulpi"; 1012 ahb-burst-config = <0>; 1013 phys = <&usb_hs4_phy>; 1014 phy-names = "usb-phy"; 1015 status = "disabled"; 1016 #reset-cells = <1>; 1017 1018 ulpi { 1019 usb_hs4_phy: phy { 1020 compatible = "qcom,usb-hs-phy-apq8064", 1021 "qcom,usb-hs-phy"; 1022 #phy-cells = <0>; 1023 clocks = <&sleep_clk>, <&cxo_board>; 1024 clock-names = "sleep", "ref"; 1025 resets = <&usb4 0>; 1026 reset-names = "por"; 1027 }; 1028 }; 1029 }; 1030 1031 sata_phy0: phy@1b400000 { 1032 compatible = "qcom,apq8064-sata-phy"; 1033 status = "disabled"; 1034 reg = <0x1b400000 0x200>; 1035 reg-names = "phy_mem"; 1036 clocks = <&gcc SATA_PHY_CFG_CLK>; 1037 clock-names = "cfg"; 1038 #phy-cells = <0>; 1039 }; 1040 1041 sata0: sata@29000000 { 1042 compatible = "qcom,apq8064-ahci", "generic-ahci"; 1043 status = "disabled"; 1044 reg = <0x29000000 0x180>; 1045 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1046 1047 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1048 <&gcc SATA_H_CLK>, 1049 <&gcc SATA_A_CLK>, 1050 <&gcc SATA_RXOOB_CLK>, 1051 <&gcc SATA_PMALIVE_CLK>; 1052 clock-names = "slave_iface", 1053 "iface", 1054 "bus", 1055 "rxoob", 1056 "core_pmalive"; 1057 1058 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1059 <&gcc SATA_PMALIVE_CLK>; 1060 assigned-clock-rates = <100000000>, <100000000>; 1061 1062 phys = <&sata_phy0>; 1063 phy-names = "sata-phy"; 1064 ports-implemented = <0x1>; 1065 }; 1066 1067 sdcc3: mmc@12180000 { 1068 compatible = "arm,pl18x", "arm,primecell"; 1069 arm,primecell-periphid = <0x00051180>; 1070 status = "disabled"; 1071 reg = <0x12180000 0x2000>; 1072 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1074 clock-names = "mclk", "apb_pclk"; 1075 bus-width = <4>; 1076 cap-sd-highspeed; 1077 cap-mmc-highspeed; 1078 max-frequency = <192000000>; 1079 no-1-8-v; 1080 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1081 dma-names = "tx", "rx"; 1082 }; 1083 1084 sdcc3bam: dma-controller@12182000 { 1085 compatible = "qcom,bam-v1.3.0"; 1086 reg = <0x12182000 0x8000>; 1087 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&gcc SDC3_H_CLK>; 1089 clock-names = "bam_clk"; 1090 #dma-cells = <1>; 1091 qcom,ee = <0>; 1092 }; 1093 1094 sdcc4: mmc@121c0000 { 1095 compatible = "arm,pl18x", "arm,primecell"; 1096 arm,primecell-periphid = <0x00051180>; 1097 status = "disabled"; 1098 reg = <0x121c0000 0x2000>; 1099 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1101 clock-names = "mclk", "apb_pclk"; 1102 bus-width = <4>; 1103 cap-sd-highspeed; 1104 cap-mmc-highspeed; 1105 max-frequency = <48000000>; 1106 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 1107 dma-names = "tx", "rx"; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&sdc4_gpios>; 1110 }; 1111 1112 sdcc4bam: dma-controller@121c2000 { 1113 compatible = "qcom,bam-v1.3.0"; 1114 reg = <0x121c2000 0x8000>; 1115 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&gcc SDC4_H_CLK>; 1117 clock-names = "bam_clk"; 1118 #dma-cells = <1>; 1119 qcom,ee = <0>; 1120 }; 1121 1122 sdcc1: mmc@12400000 { 1123 status = "disabled"; 1124 compatible = "arm,pl18x", "arm,primecell"; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&sdcc1_pins>; 1127 arm,primecell-periphid = <0x00051180>; 1128 reg = <0x12400000 0x2000>; 1129 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1131 clock-names = "mclk", "apb_pclk"; 1132 bus-width = <8>; 1133 max-frequency = <96000000>; 1134 non-removable; 1135 cap-sd-highspeed; 1136 cap-mmc-highspeed; 1137 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1138 dma-names = "tx", "rx"; 1139 }; 1140 1141 sdcc1bam: dma-controller@12402000 { 1142 compatible = "qcom,bam-v1.3.0"; 1143 reg = <0x12402000 0x8000>; 1144 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&gcc SDC1_H_CLK>; 1146 clock-names = "bam_clk"; 1147 #dma-cells = <1>; 1148 qcom,ee = <0>; 1149 }; 1150 1151 tcsr: syscon@1a400000 { 1152 compatible = "qcom,tcsr-apq8064", "syscon"; 1153 reg = <0x1a400000 0x100>; 1154 }; 1155 1156 gpu: adreno-3xx@4300000 { 1157 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1158 reg = <0x04300000 0x20000>; 1159 reg-names = "kgsl_3d0_reg_memory"; 1160 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1161 interrupt-names = "kgsl_3d0_irq"; 1162 clock-names = 1163 "core", 1164 "iface", 1165 "mem", 1166 "mem_iface"; 1167 clocks = 1168 <&mmcc GFX3D_CLK>, 1169 <&mmcc GFX3D_AHB_CLK>, 1170 <&mmcc GFX3D_AXI_CLK>, 1171 <&mmcc MMSS_IMEM_AHB_CLK>; 1172 1173 iommus = <&gfx3d 0 1174 &gfx3d 1 1175 &gfx3d 2 1176 &gfx3d 3 1177 &gfx3d 4 1178 &gfx3d 5 1179 &gfx3d 6 1180 &gfx3d 7 1181 &gfx3d 8 1182 &gfx3d 9 1183 &gfx3d 10 1184 &gfx3d 11 1185 &gfx3d 12 1186 &gfx3d 13 1187 &gfx3d 14 1188 &gfx3d 15 1189 &gfx3d 16 1190 &gfx3d 17 1191 &gfx3d 18 1192 &gfx3d 19 1193 &gfx3d 20 1194 &gfx3d 21 1195 &gfx3d 22 1196 &gfx3d 23 1197 &gfx3d 24 1198 &gfx3d 25 1199 &gfx3d 26 1200 &gfx3d 27 1201 &gfx3d 28 1202 &gfx3d 29 1203 &gfx3d 30 1204 &gfx3d 31 1205 &gfx3d1 0 1206 &gfx3d1 1 1207 &gfx3d1 2 1208 &gfx3d1 3 1209 &gfx3d1 4 1210 &gfx3d1 5 1211 &gfx3d1 6 1212 &gfx3d1 7 1213 &gfx3d1 8 1214 &gfx3d1 9 1215 &gfx3d1 10 1216 &gfx3d1 11 1217 &gfx3d1 12 1218 &gfx3d1 13 1219 &gfx3d1 14 1220 &gfx3d1 15 1221 &gfx3d1 16 1222 &gfx3d1 17 1223 &gfx3d1 18 1224 &gfx3d1 19 1225 &gfx3d1 20 1226 &gfx3d1 21 1227 &gfx3d1 22 1228 &gfx3d1 23 1229 &gfx3d1 24 1230 &gfx3d1 25 1231 &gfx3d1 26 1232 &gfx3d1 27 1233 &gfx3d1 28 1234 &gfx3d1 29 1235 &gfx3d1 30 1236 &gfx3d1 31>; 1237 1238 operating-points-v2 = <&gpu_opp_table>; 1239 1240 gpu_opp_table: opp-table { 1241 compatible = "operating-points-v2"; 1242 1243 opp-450000000 { 1244 opp-hz = /bits/ 64 <450000000>; 1245 }; 1246 1247 opp-27000000 { 1248 opp-hz = /bits/ 64 <27000000>; 1249 }; 1250 }; 1251 }; 1252 1253 mmss_sfpb: syscon@5700000 { 1254 compatible = "syscon"; 1255 reg = <0x5700000 0x70>; 1256 }; 1257 1258 dsi0: dsi@4700000 { 1259 compatible = "qcom,apq8064-dsi-ctrl", 1260 "qcom,mdss-dsi-ctrl"; 1261 label = "MDSS DSI CTRL->0"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1265 reg = <0x04700000 0x200>; 1266 reg-names = "dsi_ctrl"; 1267 1268 clocks = <&mmcc DSI_M_AHB_CLK>, 1269 <&mmcc DSI_S_AHB_CLK>, 1270 <&mmcc AMP_AHB_CLK>, 1271 <&mmcc DSI_CLK>, 1272 <&mmcc DSI1_BYTE_CLK>, 1273 <&mmcc DSI_PIXEL_CLK>, 1274 <&mmcc DSI1_ESC_CLK>; 1275 clock-names = "iface", "bus", "core_mmss", 1276 "src", "byte", "pixel", 1277 "core"; 1278 1279 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1280 <&mmcc DSI1_ESC_SRC>, 1281 <&mmcc DSI_SRC>, 1282 <&mmcc DSI_PIXEL_SRC>; 1283 assigned-clock-parents = <&dsi0_phy 0>, 1284 <&dsi0_phy 0>, 1285 <&dsi0_phy 1>, 1286 <&dsi0_phy 1>; 1287 syscon-sfpb = <&mmss_sfpb>; 1288 phys = <&dsi0_phy>; 1289 status = "disabled"; 1290 1291 ports { 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 1295 port@0 { 1296 reg = <0>; 1297 dsi0_in: endpoint { 1298 }; 1299 }; 1300 1301 port@1 { 1302 reg = <1>; 1303 dsi0_out: endpoint { 1304 }; 1305 }; 1306 }; 1307 }; 1308 1309 1310 dsi0_phy: phy@4700200 { 1311 compatible = "qcom,dsi-phy-28nm-8960"; 1312 #clock-cells = <1>; 1313 #phy-cells = <0>; 1314 1315 reg = <0x04700200 0x100>, 1316 <0x04700300 0x200>, 1317 <0x04700500 0x5c>; 1318 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1319 clock-names = "iface", "ref"; 1320 clocks = <&mmcc DSI_M_AHB_CLK>, 1321 <&pxo_board>; 1322 status = "disabled"; 1323 }; 1324 1325 dsi1: dsi@5800000 { 1326 compatible = "qcom,mdss-dsi-ctrl"; 1327 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1328 reg = <0x05800000 0x200>; 1329 reg-names = "dsi_ctrl"; 1330 1331 clocks = <&mmcc DSI2_M_AHB_CLK>, 1332 <&mmcc DSI2_S_AHB_CLK>, 1333 <&mmcc AMP_AHB_CLK>, 1334 <&mmcc DSI2_CLK>, 1335 <&mmcc DSI2_BYTE_CLK>, 1336 <&mmcc DSI2_PIXEL_CLK>, 1337 <&mmcc DSI2_ESC_CLK>; 1338 clock-names = "iface", 1339 "bus", 1340 "core_mmss", 1341 "src", 1342 "byte", 1343 "pixel", 1344 "core"; 1345 1346 assigned-clocks = <&mmcc DSI2_BYTE_SRC>, 1347 <&mmcc DSI2_ESC_SRC>, 1348 <&mmcc DSI2_SRC>, 1349 <&mmcc DSI2_PIXEL_SRC>; 1350 assigned-clock-parents = <&dsi1_phy 0>, 1351 <&dsi1_phy 0>, 1352 <&dsi1_phy 1>, 1353 <&dsi1_phy 1>; 1354 1355 syscon-sfpb = <&mmss_sfpb>; 1356 phys = <&dsi1_phy>; 1357 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 1361 status = "disabled"; 1362 1363 ports { 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 1367 port@0 { 1368 reg = <0>; 1369 dsi1_in: endpoint { 1370 }; 1371 }; 1372 1373 port@1 { 1374 reg = <1>; 1375 dsi1_out: endpoint { 1376 }; 1377 }; 1378 }; 1379 }; 1380 1381 1382 dsi1_phy: dsi-phy@5800200 { 1383 compatible = "qcom,dsi-phy-28nm-8960"; 1384 reg = <0x05800200 0x100>, 1385 <0x05800300 0x200>, 1386 <0x05800500 0x5c>; 1387 reg-names = "dsi_pll", 1388 "dsi_phy", 1389 "dsi_phy_regulator"; 1390 clock-names = "iface", 1391 "ref"; 1392 clocks = <&mmcc DSI2_M_AHB_CLK>, 1393 <&pxo_board>; 1394 #clock-cells = <1>; 1395 #phy-cells = <0>; 1396 1397 status = "disabled"; 1398 }; 1399 1400 mdp_port0: iommu@7500000 { 1401 compatible = "qcom,apq8064-iommu"; 1402 #iommu-cells = <1>; 1403 clock-names = 1404 "smmu_pclk", 1405 "iommu_clk"; 1406 clocks = 1407 <&mmcc SMMU_AHB_CLK>, 1408 <&mmcc MDP_AXI_CLK>; 1409 reg = <0x07500000 0x100000>; 1410 interrupts = 1411 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1413 qcom,ncb = <2>; 1414 }; 1415 1416 mdp_port1: iommu@7600000 { 1417 compatible = "qcom,apq8064-iommu"; 1418 #iommu-cells = <1>; 1419 clock-names = 1420 "smmu_pclk", 1421 "iommu_clk"; 1422 clocks = 1423 <&mmcc SMMU_AHB_CLK>, 1424 <&mmcc MDP_AXI_CLK>; 1425 reg = <0x07600000 0x100000>; 1426 interrupts = 1427 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1429 qcom,ncb = <2>; 1430 }; 1431 1432 gfx3d: iommu@7c00000 { 1433 compatible = "qcom,apq8064-iommu"; 1434 #iommu-cells = <1>; 1435 clock-names = 1436 "smmu_pclk", 1437 "iommu_clk"; 1438 clocks = 1439 <&mmcc SMMU_AHB_CLK>, 1440 <&mmcc GFX3D_AXI_CLK>; 1441 reg = <0x07c00000 0x100000>; 1442 interrupts = 1443 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1445 qcom,ncb = <3>; 1446 }; 1447 1448 gfx3d1: iommu@7d00000 { 1449 compatible = "qcom,apq8064-iommu"; 1450 #iommu-cells = <1>; 1451 clock-names = 1452 "smmu_pclk", 1453 "iommu_clk"; 1454 clocks = 1455 <&mmcc SMMU_AHB_CLK>, 1456 <&mmcc GFX3D_AXI_CLK>; 1457 reg = <0x07d00000 0x100000>; 1458 interrupts = 1459 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1461 qcom,ncb = <3>; 1462 }; 1463 1464 pcie: pci@1b500000 { 1465 compatible = "qcom,pcie-apq8064"; 1466 reg = <0x1b500000 0x1000>, 1467 <0x1b502000 0x80>, 1468 <0x1b600000 0x100>, 1469 <0x0ff00000 0x100000>; 1470 reg-names = "dbi", "elbi", "parf", "config"; 1471 device_type = "pci"; 1472 linux,pci-domain = <0>; 1473 bus-range = <0x00 0xff>; 1474 num-lanes = <1>; 1475 #address-cells = <3>; 1476 #size-cells = <2>; 1477 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1478 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1479 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1480 interrupt-names = "msi"; 1481 #interrupt-cells = <1>; 1482 interrupt-map-mask = <0 0 0 0x7>; 1483 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1484 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1485 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1486 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1487 clocks = <&gcc PCIE_A_CLK>, 1488 <&gcc PCIE_H_CLK>, 1489 <&gcc PCIE_PHY_REF_CLK>; 1490 clock-names = "core", "iface", "phy"; 1491 resets = <&gcc PCIE_ACLK_RESET>, 1492 <&gcc PCIE_HCLK_RESET>, 1493 <&gcc PCIE_POR_RESET>, 1494 <&gcc PCIE_PCI_RESET>, 1495 <&gcc PCIE_PHY_RESET>; 1496 reset-names = "axi", "ahb", "por", "pci", "phy"; 1497 status = "disabled"; 1498 }; 1499 1500 hdmi: hdmi-tx@4a00000 { 1501 compatible = "qcom,hdmi-tx-8960"; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&hdmi_pinctrl>; 1504 reg = <0x04a00000 0x2f0>; 1505 reg-names = "core_physical"; 1506 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&mmcc HDMI_APP_CLK>, 1508 <&mmcc HDMI_M_AHB_CLK>, 1509 <&mmcc HDMI_S_AHB_CLK>; 1510 clock-names = "core", 1511 "master_iface", 1512 "slave_iface"; 1513 1514 phys = <&hdmi_phy>; 1515 1516 status = "disabled"; 1517 1518 ports { 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 1522 port@0 { 1523 reg = <0>; 1524 hdmi_in: endpoint { 1525 }; 1526 }; 1527 1528 port@1 { 1529 reg = <1>; 1530 hdmi_out: endpoint { 1531 }; 1532 }; 1533 }; 1534 }; 1535 1536 hdmi_phy: phy@4a00400 { 1537 compatible = "qcom,hdmi-phy-8960"; 1538 reg = <0x4a00400 0x60>, 1539 <0x4a00500 0x100>; 1540 reg-names = "hdmi_phy", 1541 "hdmi_pll"; 1542 1543 clocks = <&mmcc HDMI_S_AHB_CLK>; 1544 clock-names = "slave_iface"; 1545 #phy-cells = <0>; 1546 #clock-cells = <0>; 1547 1548 status = "disabled"; 1549 }; 1550 1551 mdp: display-controller@5100000 { 1552 compatible = "qcom,mdp4"; 1553 reg = <0x05100000 0xf0000>; 1554 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1555 clocks = <&mmcc MDP_CLK>, 1556 <&mmcc MDP_AHB_CLK>, 1557 <&mmcc MDP_AXI_CLK>, 1558 <&mmcc MDP_LUT_CLK>, 1559 <&mmcc HDMI_TV_CLK>, 1560 <&mmcc MDP_TV_CLK>; 1561 clock-names = "core_clk", 1562 "iface_clk", 1563 "bus_clk", 1564 "lut_clk", 1565 "hdmi_clk", 1566 "tv_clk"; 1567 1568 iommus = <&mdp_port0 0 1569 &mdp_port0 2 1570 &mdp_port1 0 1571 &mdp_port1 2>; 1572 1573 ports { 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 1577 port@0 { 1578 reg = <0>; 1579 mdp_lvds_out: endpoint { 1580 }; 1581 }; 1582 1583 port@1 { 1584 reg = <1>; 1585 mdp_dsi1_out: endpoint { 1586 }; 1587 }; 1588 1589 port@2 { 1590 reg = <2>; 1591 mdp_dsi2_out: endpoint { 1592 }; 1593 }; 1594 1595 port@3 { 1596 reg = <3>; 1597 mdp_dtv_out: endpoint { 1598 }; 1599 }; 1600 }; 1601 }; 1602 1603 riva: riva-pil@3200800 { 1604 compatible = "qcom,riva-pil"; 1605 1606 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1607 reg-names = "ccu", "dxe", "pmu"; 1608 1609 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1610 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1611 interrupt-names = "wdog", "fatal"; 1612 1613 memory-region = <&wcnss_mem>; 1614 1615 vddcx-supply = <&pm8921_s3>; 1616 vddmx-supply = <&pm8921_l24>; 1617 vddpx-supply = <&pm8921_s4>; 1618 1619 status = "disabled"; 1620 1621 iris { 1622 compatible = "qcom,wcn3660"; 1623 1624 clocks = <&cxo_board>; 1625 clock-names = "xo"; 1626 1627 vddxo-supply = <&pm8921_l4>; 1628 vddrfa-supply = <&pm8921_s2>; 1629 vddpa-supply = <&pm8921_l10>; 1630 vdddig-supply = <&pm8921_lvs2>; 1631 }; 1632 1633 smd-edge { 1634 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1635 1636 qcom,ipc = <&l2cc 8 25>; 1637 qcom,smd-edge = <6>; 1638 1639 label = "riva"; 1640 1641 wcnss { 1642 compatible = "qcom,wcnss"; 1643 qcom,smd-channels = "WCNSS_CTRL"; 1644 1645 qcom,mmio = <&riva>; 1646 1647 bluetooth { 1648 compatible = "qcom,wcnss-bt"; 1649 }; 1650 1651 wifi { 1652 compatible = "qcom,wcnss-wlan"; 1653 1654 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1656 interrupt-names = "tx", "rx"; 1657 1658 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1659 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1660 }; 1661 }; 1662 }; 1663 }; 1664 1665 etb@1a01000 { 1666 compatible = "arm,coresight-etb10", "arm,primecell"; 1667 reg = <0x1a01000 0x1000>; 1668 1669 clocks = <&rpmcc RPM_QDSS_CLK>; 1670 clock-names = "apb_pclk"; 1671 1672 in-ports { 1673 port { 1674 etb_in: endpoint { 1675 remote-endpoint = <&replicator_out0>; 1676 }; 1677 }; 1678 }; 1679 }; 1680 1681 tpiu@1a03000 { 1682 compatible = "arm,coresight-tpiu", "arm,primecell"; 1683 reg = <0x1a03000 0x1000>; 1684 1685 clocks = <&rpmcc RPM_QDSS_CLK>; 1686 clock-names = "apb_pclk"; 1687 1688 in-ports { 1689 port { 1690 tpiu_in: endpoint { 1691 remote-endpoint = <&replicator_out1>; 1692 }; 1693 }; 1694 }; 1695 }; 1696 1697 replicator { 1698 compatible = "arm,coresight-static-replicator"; 1699 1700 clocks = <&rpmcc RPM_QDSS_CLK>; 1701 clock-names = "apb_pclk"; 1702 1703 out-ports { 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 1707 port@0 { 1708 reg = <0>; 1709 replicator_out0: endpoint { 1710 remote-endpoint = <&etb_in>; 1711 }; 1712 }; 1713 port@1 { 1714 reg = <1>; 1715 replicator_out1: endpoint { 1716 remote-endpoint = <&tpiu_in>; 1717 }; 1718 }; 1719 }; 1720 1721 in-ports { 1722 port { 1723 replicator_in: endpoint { 1724 remote-endpoint = <&funnel_out>; 1725 }; 1726 }; 1727 }; 1728 }; 1729 1730 funnel@1a04000 { 1731 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1732 reg = <0x1a04000 0x1000>; 1733 1734 clocks = <&rpmcc RPM_QDSS_CLK>; 1735 clock-names = "apb_pclk"; 1736 1737 in-ports { 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 1741 /* 1742 * Not described input ports: 1743 * 2 - connected to STM component 1744 * 3 - not-connected 1745 * 6 - not-connected 1746 * 7 - not-connected 1747 */ 1748 port@0 { 1749 reg = <0>; 1750 funnel_in0: endpoint { 1751 remote-endpoint = <&etm0_out>; 1752 }; 1753 }; 1754 port@1 { 1755 reg = <1>; 1756 funnel_in1: endpoint { 1757 remote-endpoint = <&etm1_out>; 1758 }; 1759 }; 1760 port@4 { 1761 reg = <4>; 1762 funnel_in4: endpoint { 1763 remote-endpoint = <&etm2_out>; 1764 }; 1765 }; 1766 port@5 { 1767 reg = <5>; 1768 funnel_in5: endpoint { 1769 remote-endpoint = <&etm3_out>; 1770 }; 1771 }; 1772 }; 1773 1774 out-ports { 1775 port { 1776 funnel_out: endpoint { 1777 remote-endpoint = <&replicator_in>; 1778 }; 1779 }; 1780 }; 1781 }; 1782 1783 etm@1a1c000 { 1784 compatible = "arm,coresight-etm3x", "arm,primecell"; 1785 reg = <0x1a1c000 0x1000>; 1786 1787 clocks = <&rpmcc RPM_QDSS_CLK>; 1788 clock-names = "apb_pclk"; 1789 1790 cpu = <&CPU0>; 1791 1792 out-ports { 1793 port { 1794 etm0_out: endpoint { 1795 remote-endpoint = <&funnel_in0>; 1796 }; 1797 }; 1798 }; 1799 }; 1800 1801 etm@1a1d000 { 1802 compatible = "arm,coresight-etm3x", "arm,primecell"; 1803 reg = <0x1a1d000 0x1000>; 1804 1805 clocks = <&rpmcc RPM_QDSS_CLK>; 1806 clock-names = "apb_pclk"; 1807 1808 cpu = <&CPU1>; 1809 1810 out-ports { 1811 port { 1812 etm1_out: endpoint { 1813 remote-endpoint = <&funnel_in1>; 1814 }; 1815 }; 1816 }; 1817 }; 1818 1819 etm@1a1e000 { 1820 compatible = "arm,coresight-etm3x", "arm,primecell"; 1821 reg = <0x1a1e000 0x1000>; 1822 1823 clocks = <&rpmcc RPM_QDSS_CLK>; 1824 clock-names = "apb_pclk"; 1825 1826 cpu = <&CPU2>; 1827 1828 out-ports { 1829 port { 1830 etm2_out: endpoint { 1831 remote-endpoint = <&funnel_in4>; 1832 }; 1833 }; 1834 }; 1835 }; 1836 1837 etm@1a1f000 { 1838 compatible = "arm,coresight-etm3x", "arm,primecell"; 1839 reg = <0x1a1f000 0x1000>; 1840 1841 clocks = <&rpmcc RPM_QDSS_CLK>; 1842 clock-names = "apb_pclk"; 1843 1844 cpu = <&CPU3>; 1845 1846 out-ports { 1847 port { 1848 etm3_out: endpoint { 1849 remote-endpoint = <&funnel_in5>; 1850 }; 1851 }; 1852 }; 1853 }; 1854 }; 1855}; 1856#include "qcom-apq8064-pins.dtsi" 1857