1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,lcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm APQ8064"; 16 compatible = "qcom,apq8064"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 smem_region: smem@80000000 { 25 reg = <0x80000000 0x200000>; 26 no-map; 27 }; 28 29 wcnss_mem: wcnss@8f000000 { 30 reg = <0x8f000000 0x700000>; 31 no-map; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v1"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&L2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&CPU_SPC>; 48 }; 49 50 CPU1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v1"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&L2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&CPU_SPC>; 59 }; 60 61 CPU2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v1"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&L2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&CPU_SPC>; 70 }; 71 72 CPU3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v1"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&L2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&CPU_SPC>; 81 }; 82 83 L2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 CPU_SPC: spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <400>; 94 exit-latency-us = <900>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 }; 99 100 memory@0 { 101 device_type = "memory"; 102 reg = <0x0 0x0>; 103 }; 104 105 thermal-zones { 106 cpu0-thermal { 107 polling-delay-passive = <250>; 108 polling-delay = <1000>; 109 110 thermal-sensors = <&tsens 7>; 111 coefficients = <1199 0>; 112 113 trips { 114 cpu_alert0: trip0 { 115 temperature = <75000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 cpu_crit0: trip1 { 120 temperature = <110000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 }; 125 }; 126 127 cpu1-thermal { 128 polling-delay-passive = <250>; 129 polling-delay = <1000>; 130 131 thermal-sensors = <&tsens 8>; 132 coefficients = <1132 0>; 133 134 trips { 135 cpu_alert1: trip0 { 136 temperature = <75000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 cpu_crit1: trip1 { 141 temperature = <110000>; 142 hysteresis = <2000>; 143 type = "critical"; 144 }; 145 }; 146 }; 147 148 cpu2-thermal { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens 9>; 153 coefficients = <1199 0>; 154 155 trips { 156 cpu_alert2: trip0 { 157 temperature = <75000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 cpu_crit2: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu3-thermal { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens 10>; 174 coefficients = <1132 0>; 175 176 trips { 177 cpu_alert3: trip0 { 178 temperature = <75000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 cpu_crit3: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 }; 190 191 cpu-pmu { 192 compatible = "qcom,krait-pmu"; 193 interrupts = <1 10 0x304>; 194 }; 195 196 clocks { 197 cxo_board: cxo_board { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <19200000>; 201 }; 202 203 pxo_board: pxo_board { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <27000000>; 207 }; 208 209 sleep_clk: sleep_clk { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32768>; 213 }; 214 }; 215 216 sfpb_mutex: hwmutex { 217 compatible = "qcom,sfpb-mutex"; 218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 219 #hwlock-cells = <1>; 220 }; 221 222 smem { 223 compatible = "qcom,smem"; 224 memory-region = <&smem_region>; 225 226 hwlocks = <&sfpb_mutex 3>; 227 }; 228 229 smsm { 230 compatible = "qcom,smsm"; 231 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 qcom,ipc-1 = <&l2cc 8 4>; 236 qcom,ipc-2 = <&l2cc 8 14>; 237 qcom,ipc-3 = <&l2cc 8 23>; 238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 239 240 apps_smsm: apps@0 { 241 reg = <0>; 242 #qcom,smem-state-cells = <1>; 243 }; 244 245 modem_smsm: modem@1 { 246 reg = <1>; 247 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; 248 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 253 q6_smsm: q6@2 { 254 reg = <2>; 255 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; 256 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 }; 260 261 wcnss_smsm: wcnss@3 { 262 reg = <3>; 263 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; 264 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 }; 268 269 dsps_smsm: dsps@4 { 270 reg = <4>; 271 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; 272 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 }; 276 }; 277 278 firmware { 279 scm { 280 compatible = "qcom,scm-apq8064", "qcom,scm"; 281 282 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 283 clock-names = "core"; 284 }; 285 }; 286 287 soc: soc { 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges; 291 compatible = "simple-bus"; 292 293 tlmm_pinmux: pinctrl@800000 { 294 compatible = "qcom,apq8064-pinctrl"; 295 reg = <0x800000 0x4000>; 296 297 gpio-controller; 298 gpio-ranges = <&tlmm_pinmux 0 0 90>; 299 #gpio-cells = <2>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 303 304 pinctrl-names = "default"; 305 pinctrl-0 = <&ps_hold>; 306 }; 307 308 sfpb_wrapper_mutex: syscon@1200000 { 309 compatible = "syscon"; 310 reg = <0x01200000 0x8000>; 311 }; 312 313 intc: interrupt-controller@2000000 { 314 compatible = "qcom,msm-qgic2"; 315 interrupt-controller; 316 #interrupt-cells = <3>; 317 reg = <0x02000000 0x1000>, 318 <0x02002000 0x1000>; 319 }; 320 321 timer@200a000 { 322 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", 323 "qcom,msm-timer"; 324 interrupts = <1 1 0x301>, 325 <1 2 0x301>, 326 <1 3 0x301>; 327 reg = <0x0200a000 0x100>; 328 clock-frequency = <27000000>; 329 cpu-offset = <0x80000>; 330 }; 331 332 acc0: clock-controller@2088000 { 333 compatible = "qcom,kpss-acc-v1"; 334 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 335 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 336 clock-names = "pll8_vote", "pxo"; 337 clock-output-names = "acpu0_aux"; 338 #clock-cells = <0>; 339 }; 340 341 acc1: clock-controller@2098000 { 342 compatible = "qcom,kpss-acc-v1"; 343 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 344 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 345 clock-names = "pll8_vote", "pxo"; 346 clock-output-names = "acpu1_aux"; 347 #clock-cells = <0>; 348 }; 349 350 acc2: clock-controller@20a8000 { 351 compatible = "qcom,kpss-acc-v1"; 352 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 353 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 354 clock-names = "pll8_vote", "pxo"; 355 clock-output-names = "acpu2_aux"; 356 #clock-cells = <0>; 357 }; 358 359 acc3: clock-controller@20b8000 { 360 compatible = "qcom,kpss-acc-v1"; 361 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 362 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 363 clock-names = "pll8_vote", "pxo"; 364 clock-output-names = "acpu3_aux"; 365 #clock-cells = <0>; 366 }; 367 368 saw0: power-controller@2089000 { 369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 370 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 371 regulator; 372 }; 373 374 saw1: power-controller@2099000 { 375 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 376 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 377 regulator; 378 }; 379 380 saw2: power-controller@20a9000 { 381 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 382 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 383 regulator; 384 }; 385 386 saw3: power-controller@20b9000 { 387 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 388 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 389 regulator; 390 }; 391 392 sps_sic_non_secure: sps-sic-non-secure@12100000 { 393 compatible = "syscon"; 394 reg = <0x12100000 0x10000>; 395 }; 396 397 gsbi1: gsbi@12440000 { 398 status = "disabled"; 399 compatible = "qcom,gsbi-v1.0.0"; 400 cell-index = <1>; 401 reg = <0x12440000 0x100>; 402 clocks = <&gcc GSBI1_H_CLK>; 403 clock-names = "iface"; 404 #address-cells = <1>; 405 #size-cells = <1>; 406 ranges; 407 408 syscon-tcsr = <&tcsr>; 409 410 gsbi1_serial: serial@12450000 { 411 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 412 reg = <0x12450000 0x100>, 413 <0x12400000 0x03>; 414 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 416 clock-names = "core", "iface"; 417 status = "disabled"; 418 }; 419 420 gsbi1_i2c: i2c@12460000 { 421 compatible = "qcom,i2c-qup-v1.1.1"; 422 pinctrl-0 = <&i2c1_pins>; 423 pinctrl-1 = <&i2c1_pins_sleep>; 424 pinctrl-names = "default", "sleep"; 425 reg = <0x12460000 0x1000>; 426 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 428 clock-names = "core", "iface"; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 status = "disabled"; 432 }; 433 434 }; 435 436 gsbi2: gsbi@12480000 { 437 status = "disabled"; 438 compatible = "qcom,gsbi-v1.0.0"; 439 cell-index = <2>; 440 reg = <0x12480000 0x100>; 441 clocks = <&gcc GSBI2_H_CLK>; 442 clock-names = "iface"; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 ranges; 446 447 syscon-tcsr = <&tcsr>; 448 449 gsbi2_i2c: i2c@124a0000 { 450 compatible = "qcom,i2c-qup-v1.1.1"; 451 reg = <0x124a0000 0x1000>; 452 pinctrl-0 = <&i2c2_pins>; 453 pinctrl-1 = <&i2c2_pins_sleep>; 454 pinctrl-names = "default", "sleep"; 455 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 457 clock-names = "core", "iface"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 }; 463 464 gsbi3: gsbi@16200000 { 465 status = "disabled"; 466 compatible = "qcom,gsbi-v1.0.0"; 467 cell-index = <3>; 468 reg = <0x16200000 0x100>; 469 clocks = <&gcc GSBI3_H_CLK>; 470 clock-names = "iface"; 471 #address-cells = <1>; 472 #size-cells = <1>; 473 ranges; 474 gsbi3_i2c: i2c@16280000 { 475 compatible = "qcom,i2c-qup-v1.1.1"; 476 pinctrl-0 = <&i2c3_pins>; 477 pinctrl-1 = <&i2c3_pins_sleep>; 478 pinctrl-names = "default", "sleep"; 479 reg = <0x16280000 0x1000>; 480 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&gcc GSBI3_QUP_CLK>, 482 <&gcc GSBI3_H_CLK>; 483 clock-names = "core", "iface"; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 }; 489 490 gsbi4: gsbi@16300000 { 491 status = "disabled"; 492 compatible = "qcom,gsbi-v1.0.0"; 493 cell-index = <4>; 494 reg = <0x16300000 0x03>; 495 clocks = <&gcc GSBI4_H_CLK>; 496 clock-names = "iface"; 497 #address-cells = <1>; 498 #size-cells = <1>; 499 ranges; 500 501 gsbi4_serial: serial@16340000 { 502 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 503 reg = <0x16340000 0x100>, 504 <0x16300000 0x3>; 505 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 506 pinctrl-0 = <&gsbi4_uart_pin_a>; 507 pinctrl-names = "default"; 508 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 509 clock-names = "core", "iface"; 510 status = "disabled"; 511 }; 512 513 gsbi4_i2c: i2c@16380000 { 514 compatible = "qcom,i2c-qup-v1.1.1"; 515 pinctrl-0 = <&i2c4_pins>; 516 pinctrl-1 = <&i2c4_pins_sleep>; 517 pinctrl-names = "default", "sleep"; 518 reg = <0x16380000 0x1000>; 519 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&gcc GSBI4_QUP_CLK>, 521 <&gcc GSBI4_H_CLK>; 522 clock-names = "core", "iface"; 523 status = "disabled"; 524 }; 525 }; 526 527 gsbi5: gsbi@1a200000 { 528 status = "disabled"; 529 compatible = "qcom,gsbi-v1.0.0"; 530 cell-index = <5>; 531 reg = <0x1a200000 0x03>; 532 clocks = <&gcc GSBI5_H_CLK>; 533 clock-names = "iface"; 534 #address-cells = <1>; 535 #size-cells = <1>; 536 ranges; 537 538 gsbi5_serial: serial@1a240000 { 539 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 540 reg = <0x1a240000 0x100>, 541 <0x1a200000 0x03>; 542 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 544 clock-names = "core", "iface"; 545 status = "disabled"; 546 }; 547 548 gsbi5_spi: spi@1a280000 { 549 compatible = "qcom,spi-qup-v1.1.1"; 550 reg = <0x1a280000 0x1000>; 551 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 552 pinctrl-0 = <&spi5_default>; 553 pinctrl-1 = <&spi5_sleep>; 554 pinctrl-names = "default", "sleep"; 555 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 556 clock-names = "core", "iface"; 557 status = "disabled"; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 }; 561 }; 562 563 gsbi6: gsbi@16500000 { 564 status = "disabled"; 565 compatible = "qcom,gsbi-v1.0.0"; 566 cell-index = <6>; 567 reg = <0x16500000 0x03>; 568 clocks = <&gcc GSBI6_H_CLK>; 569 clock-names = "iface"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges; 573 574 gsbi6_serial: serial@16540000 { 575 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 576 reg = <0x16540000 0x100>, 577 <0x16500000 0x03>; 578 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 580 clock-names = "core", "iface"; 581 status = "disabled"; 582 }; 583 584 gsbi6_i2c: i2c@16580000 { 585 compatible = "qcom,i2c-qup-v1.1.1"; 586 pinctrl-0 = <&i2c6_pins>; 587 pinctrl-1 = <&i2c6_pins_sleep>; 588 pinctrl-names = "default", "sleep"; 589 reg = <0x16580000 0x1000>; 590 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&gcc GSBI6_QUP_CLK>, 592 <&gcc GSBI6_H_CLK>; 593 clock-names = "core", "iface"; 594 status = "disabled"; 595 }; 596 }; 597 598 gsbi7: gsbi@16600000 { 599 status = "disabled"; 600 compatible = "qcom,gsbi-v1.0.0"; 601 cell-index = <7>; 602 reg = <0x16600000 0x100>; 603 clocks = <&gcc GSBI7_H_CLK>; 604 clock-names = "iface"; 605 #address-cells = <1>; 606 #size-cells = <1>; 607 ranges; 608 syscon-tcsr = <&tcsr>; 609 610 gsbi7_serial: serial@16640000 { 611 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 612 reg = <0x16640000 0x1000>, 613 <0x16600000 0x1000>; 614 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 616 clock-names = "core", "iface"; 617 status = "disabled"; 618 }; 619 620 gsbi7_i2c: i2c@16680000 { 621 compatible = "qcom,i2c-qup-v1.1.1"; 622 pinctrl-0 = <&i2c7_pins>; 623 pinctrl-1 = <&i2c7_pins_sleep>; 624 pinctrl-names = "default", "sleep"; 625 reg = <0x16680000 0x1000>; 626 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&gcc GSBI7_QUP_CLK>, 628 <&gcc GSBI7_H_CLK>; 629 clock-names = "core", "iface"; 630 status = "disabled"; 631 }; 632 }; 633 634 rng@1a500000 { 635 compatible = "qcom,prng"; 636 reg = <0x1a500000 0x200>; 637 clocks = <&gcc PRNG_CLK>; 638 clock-names = "core"; 639 }; 640 641 ssbi2: ssbi@c00000 { 642 compatible = "qcom,ssbi"; 643 reg = <0x00c00000 0x1000>; 644 qcom,controller-type = "pmic-arbiter"; 645 }; 646 647 ssbi: ssbi@500000 { 648 compatible = "qcom,ssbi"; 649 reg = <0x00500000 0x1000>; 650 qcom,controller-type = "pmic-arbiter"; 651 }; 652 653 qfprom: qfprom@700000 { 654 compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 655 reg = <0x00700000 0x1000>; 656 #address-cells = <1>; 657 #size-cells = <1>; 658 ranges; 659 tsens_calib: calib@404 { 660 reg = <0x404 0x10>; 661 }; 662 tsens_backup: backup_calib@414 { 663 reg = <0x414 0x10>; 664 }; 665 }; 666 667 gcc: clock-controller@900000 { 668 compatible = "qcom,gcc-apq8064", "syscon"; 669 reg = <0x00900000 0x4000>; 670 #clock-cells = <1>; 671 #power-domain-cells = <1>; 672 #reset-cells = <1>; 673 clocks = <&cxo_board>, 674 <&pxo_board>, 675 <&lcc PLL4>; 676 clock-names = "cxo", "pxo", "pll4"; 677 678 tsens: thermal-sensor { 679 compatible = "qcom,msm8960-tsens"; 680 681 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 682 nvmem-cell-names = "calib", "calib_backup"; 683 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 684 interrupt-names = "uplow"; 685 686 #qcom,sensors = <11>; 687 #thermal-sensor-cells = <1>; 688 }; 689 }; 690 691 lcc: clock-controller@28000000 { 692 compatible = "qcom,lcc-apq8064"; 693 reg = <0x28000000 0x1000>; 694 #clock-cells = <1>; 695 #reset-cells = <1>; 696 clocks = <&pxo_board>, 697 <&gcc PLL4_VOTE>, 698 <0>, 699 <0>, <0>, 700 <0>, <0>, 701 <0>; 702 clock-names = "pxo", 703 "pll4_vote", 704 "mi2s_codec_clk", 705 "codec_i2s_mic_codec_clk", 706 "spare_i2s_mic_codec_clk", 707 "codec_i2s_spkr_codec_clk", 708 "spare_i2s_spkr_codec_clk", 709 "pcm_codec_clk"; 710 }; 711 712 mmcc: clock-controller@4000000 { 713 compatible = "qcom,mmcc-apq8064"; 714 reg = <0x4000000 0x1000>; 715 #clock-cells = <1>; 716 #power-domain-cells = <1>; 717 #reset-cells = <1>; 718 clocks = <&pxo_board>, 719 <&gcc PLL3>, 720 <&gcc PLL8_VOTE>, 721 <&dsi0_phy 1>, 722 <&dsi0_phy 0>, 723 <&dsi1_phy 1>, 724 <&dsi1_phy 0>, 725 <&hdmi_phy>; 726 clock-names = "pxo", 727 "pll3", 728 "pll8_vote", 729 "dsi1pll", 730 "dsi1pllbyte", 731 "dsi2pll", 732 "dsi2pllbyte", 733 "hdmipll"; 734 }; 735 736 l2cc: clock-controller@2011000 { 737 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 738 reg = <0x2011000 0x1000>; 739 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 740 clock-names = "pll8_vote", "pxo"; 741 #clock-cells = <0>; 742 }; 743 744 rpm: rpm@108000 { 745 compatible = "qcom,rpm-apq8064"; 746 reg = <0x108000 0x1000>; 747 qcom,ipc = <&l2cc 0x8 2>; 748 749 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 750 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 751 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 752 interrupt-names = "ack", "err", "wakeup"; 753 754 rpmcc: clock-controller { 755 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 756 #clock-cells = <1>; 757 clocks = <&pxo_board>, <&cxo_board>; 758 clock-names = "pxo", "cxo"; 759 }; 760 761 regulators { 762 compatible = "qcom,rpm-pm8921-regulators"; 763 764 pm8921_s1: s1 {}; 765 pm8921_s2: s2 {}; 766 pm8921_s3: s3 {}; 767 pm8921_s4: s4 {}; 768 pm8921_s7: s7 {}; 769 pm8921_s8: s8 {}; 770 771 pm8921_l1: l1 {}; 772 pm8921_l2: l2 {}; 773 pm8921_l3: l3 {}; 774 pm8921_l4: l4 {}; 775 pm8921_l5: l5 {}; 776 pm8921_l6: l6 {}; 777 pm8921_l7: l7 {}; 778 pm8921_l8: l8 {}; 779 pm8921_l9: l9 {}; 780 pm8921_l10: l10 {}; 781 pm8921_l11: l11 {}; 782 pm8921_l12: l12 {}; 783 pm8921_l14: l14 {}; 784 pm8921_l15: l15 {}; 785 pm8921_l16: l16 {}; 786 pm8921_l17: l17 {}; 787 pm8921_l18: l18 {}; 788 pm8921_l21: l21 {}; 789 pm8921_l22: l22 {}; 790 pm8921_l23: l23 {}; 791 pm8921_l24: l24 {}; 792 pm8921_l25: l25 {}; 793 pm8921_l26: l26 {}; 794 pm8921_l27: l27 {}; 795 pm8921_l28: l28 {}; 796 pm8921_l29: l29 {}; 797 798 pm8921_lvs1: lvs1 {}; 799 pm8921_lvs2: lvs2 {}; 800 pm8921_lvs3: lvs3 {}; 801 pm8921_lvs4: lvs4 {}; 802 pm8921_lvs5: lvs5 {}; 803 pm8921_lvs6: lvs6 {}; 804 pm8921_lvs7: lvs7 {}; 805 806 pm8921_usb_switch: usb-switch {}; 807 808 pm8921_hdmi_switch: hdmi-switch { 809 bias-pull-down; 810 }; 811 812 pm8921_ncp: ncp {}; 813 }; 814 }; 815 816 usb1: usb@12500000 { 817 compatible = "qcom,ci-hdrc"; 818 reg = <0x12500000 0x200>, 819 <0x12500200 0x200>; 820 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 822 clock-names = "core", "iface"; 823 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 824 assigned-clock-rates = <60000000>; 825 resets = <&gcc USB_HS1_RESET>; 826 reset-names = "core"; 827 phy_type = "ulpi"; 828 ahb-burst-config = <0>; 829 phys = <&usb_hs1_phy>; 830 phy-names = "usb-phy"; 831 status = "disabled"; 832 #reset-cells = <1>; 833 834 ulpi { 835 usb_hs1_phy: phy { 836 compatible = "qcom,usb-hs-phy-apq8064", 837 "qcom,usb-hs-phy"; 838 clocks = <&sleep_clk>, <&cxo_board>; 839 clock-names = "sleep", "ref"; 840 resets = <&usb1 0>; 841 reset-names = "por"; 842 #phy-cells = <0>; 843 }; 844 }; 845 }; 846 847 usb3: usb@12520000 { 848 compatible = "qcom,ci-hdrc"; 849 reg = <0x12520000 0x200>, 850 <0x12520200 0x200>; 851 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 853 clock-names = "core", "iface"; 854 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 855 assigned-clock-rates = <60000000>; 856 resets = <&gcc USB_HS3_RESET>; 857 reset-names = "core"; 858 phy_type = "ulpi"; 859 ahb-burst-config = <0>; 860 phys = <&usb_hs3_phy>; 861 phy-names = "usb-phy"; 862 status = "disabled"; 863 #reset-cells = <1>; 864 865 ulpi { 866 usb_hs3_phy: phy { 867 compatible = "qcom,usb-hs-phy-apq8064", 868 "qcom,usb-hs-phy"; 869 #phy-cells = <0>; 870 clocks = <&sleep_clk>, <&cxo_board>; 871 clock-names = "sleep", "ref"; 872 resets = <&usb3 0>; 873 reset-names = "por"; 874 }; 875 }; 876 }; 877 878 usb4: usb@12530000 { 879 compatible = "qcom,ci-hdrc"; 880 reg = <0x12530000 0x200>, 881 <0x12530200 0x200>; 882 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 884 clock-names = "core", "iface"; 885 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 886 assigned-clock-rates = <60000000>; 887 resets = <&gcc USB_HS4_RESET>; 888 reset-names = "core"; 889 phy_type = "ulpi"; 890 ahb-burst-config = <0>; 891 phys = <&usb_hs4_phy>; 892 phy-names = "usb-phy"; 893 status = "disabled"; 894 #reset-cells = <1>; 895 896 ulpi { 897 usb_hs4_phy: phy { 898 compatible = "qcom,usb-hs-phy-apq8064", 899 "qcom,usb-hs-phy"; 900 #phy-cells = <0>; 901 clocks = <&sleep_clk>, <&cxo_board>; 902 clock-names = "sleep", "ref"; 903 resets = <&usb4 0>; 904 reset-names = "por"; 905 }; 906 }; 907 }; 908 909 sata_phy0: phy@1b400000 { 910 compatible = "qcom,apq8064-sata-phy"; 911 status = "disabled"; 912 reg = <0x1b400000 0x200>; 913 reg-names = "phy_mem"; 914 clocks = <&gcc SATA_PHY_CFG_CLK>; 915 clock-names = "cfg"; 916 #phy-cells = <0>; 917 }; 918 919 sata0: sata@29000000 { 920 compatible = "qcom,apq8064-ahci", "generic-ahci"; 921 status = "disabled"; 922 reg = <0x29000000 0x180>; 923 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 924 925 clocks = <&gcc SFAB_SATA_S_H_CLK>, 926 <&gcc SATA_H_CLK>, 927 <&gcc SATA_A_CLK>, 928 <&gcc SATA_RXOOB_CLK>, 929 <&gcc SATA_PMALIVE_CLK>; 930 clock-names = "slave_iface", 931 "iface", 932 "bus", 933 "rxoob", 934 "core_pmalive"; 935 936 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 937 <&gcc SATA_PMALIVE_CLK>; 938 assigned-clock-rates = <100000000>, <100000000>; 939 940 phys = <&sata_phy0>; 941 phy-names = "sata-phy"; 942 ports-implemented = <0x1>; 943 }; 944 945 sdcc3: mmc@12180000 { 946 compatible = "arm,pl18x", "arm,primecell"; 947 arm,primecell-periphid = <0x00051180>; 948 status = "disabled"; 949 reg = <0x12180000 0x2000>; 950 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 952 clock-names = "mclk", "apb_pclk"; 953 bus-width = <4>; 954 cap-sd-highspeed; 955 cap-mmc-highspeed; 956 max-frequency = <192000000>; 957 no-1-8-v; 958 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 959 dma-names = "tx", "rx"; 960 }; 961 962 sdcc3bam: dma-controller@12182000 { 963 compatible = "qcom,bam-v1.3.0"; 964 reg = <0x12182000 0x8000>; 965 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&gcc SDC3_H_CLK>; 967 clock-names = "bam_clk"; 968 #dma-cells = <1>; 969 qcom,ee = <0>; 970 }; 971 972 sdcc4: mmc@121c0000 { 973 compatible = "arm,pl18x", "arm,primecell"; 974 arm,primecell-periphid = <0x00051180>; 975 status = "disabled"; 976 reg = <0x121c0000 0x2000>; 977 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 979 clock-names = "mclk", "apb_pclk"; 980 bus-width = <4>; 981 cap-sd-highspeed; 982 cap-mmc-highspeed; 983 max-frequency = <48000000>; 984 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 985 dma-names = "tx", "rx"; 986 pinctrl-names = "default"; 987 pinctrl-0 = <&sdc4_gpios>; 988 }; 989 990 sdcc4bam: dma-controller@121c2000 { 991 compatible = "qcom,bam-v1.3.0"; 992 reg = <0x121c2000 0x8000>; 993 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&gcc SDC4_H_CLK>; 995 clock-names = "bam_clk"; 996 #dma-cells = <1>; 997 qcom,ee = <0>; 998 }; 999 1000 sdcc1: mmc@12400000 { 1001 status = "disabled"; 1002 compatible = "arm,pl18x", "arm,primecell"; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&sdcc1_pins>; 1005 arm,primecell-periphid = <0x00051180>; 1006 reg = <0x12400000 0x2000>; 1007 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1009 clock-names = "mclk", "apb_pclk"; 1010 bus-width = <8>; 1011 max-frequency = <96000000>; 1012 non-removable; 1013 cap-sd-highspeed; 1014 cap-mmc-highspeed; 1015 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1016 dma-names = "tx", "rx"; 1017 }; 1018 1019 sdcc1bam: dma-controller@12402000 { 1020 compatible = "qcom,bam-v1.3.0"; 1021 reg = <0x12402000 0x8000>; 1022 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&gcc SDC1_H_CLK>; 1024 clock-names = "bam_clk"; 1025 #dma-cells = <1>; 1026 qcom,ee = <0>; 1027 }; 1028 1029 tcsr: syscon@1a400000 { 1030 compatible = "qcom,tcsr-apq8064", "syscon"; 1031 reg = <0x1a400000 0x100>; 1032 }; 1033 1034 gpu: adreno-3xx@4300000 { 1035 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1036 reg = <0x04300000 0x20000>; 1037 reg-names = "kgsl_3d0_reg_memory"; 1038 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1039 interrupt-names = "kgsl_3d0_irq"; 1040 clock-names = 1041 "core", 1042 "iface", 1043 "mem", 1044 "mem_iface"; 1045 clocks = 1046 <&mmcc GFX3D_CLK>, 1047 <&mmcc GFX3D_AHB_CLK>, 1048 <&mmcc GFX3D_AXI_CLK>, 1049 <&mmcc MMSS_IMEM_AHB_CLK>; 1050 1051 iommus = <&gfx3d 0 1052 &gfx3d 1 1053 &gfx3d 2 1054 &gfx3d 3 1055 &gfx3d 4 1056 &gfx3d 5 1057 &gfx3d 6 1058 &gfx3d 7 1059 &gfx3d 8 1060 &gfx3d 9 1061 &gfx3d 10 1062 &gfx3d 11 1063 &gfx3d 12 1064 &gfx3d 13 1065 &gfx3d 14 1066 &gfx3d 15 1067 &gfx3d 16 1068 &gfx3d 17 1069 &gfx3d 18 1070 &gfx3d 19 1071 &gfx3d 20 1072 &gfx3d 21 1073 &gfx3d 22 1074 &gfx3d 23 1075 &gfx3d 24 1076 &gfx3d 25 1077 &gfx3d 26 1078 &gfx3d 27 1079 &gfx3d 28 1080 &gfx3d 29 1081 &gfx3d 30 1082 &gfx3d 31 1083 &gfx3d1 0 1084 &gfx3d1 1 1085 &gfx3d1 2 1086 &gfx3d1 3 1087 &gfx3d1 4 1088 &gfx3d1 5 1089 &gfx3d1 6 1090 &gfx3d1 7 1091 &gfx3d1 8 1092 &gfx3d1 9 1093 &gfx3d1 10 1094 &gfx3d1 11 1095 &gfx3d1 12 1096 &gfx3d1 13 1097 &gfx3d1 14 1098 &gfx3d1 15 1099 &gfx3d1 16 1100 &gfx3d1 17 1101 &gfx3d1 18 1102 &gfx3d1 19 1103 &gfx3d1 20 1104 &gfx3d1 21 1105 &gfx3d1 22 1106 &gfx3d1 23 1107 &gfx3d1 24 1108 &gfx3d1 25 1109 &gfx3d1 26 1110 &gfx3d1 27 1111 &gfx3d1 28 1112 &gfx3d1 29 1113 &gfx3d1 30 1114 &gfx3d1 31>; 1115 1116 operating-points-v2 = <&gpu_opp_table>; 1117 1118 gpu_opp_table: opp-table { 1119 compatible = "operating-points-v2"; 1120 1121 opp-450000000 { 1122 opp-hz = /bits/ 64 <450000000>; 1123 }; 1124 1125 opp-27000000 { 1126 opp-hz = /bits/ 64 <27000000>; 1127 }; 1128 }; 1129 }; 1130 1131 mmss_sfpb: syscon@5700000 { 1132 compatible = "syscon"; 1133 reg = <0x5700000 0x70>; 1134 }; 1135 1136 dsi0: dsi@4700000 { 1137 compatible = "qcom,apq8064-dsi-ctrl", 1138 "qcom,mdss-dsi-ctrl"; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1142 reg = <0x04700000 0x200>; 1143 reg-names = "dsi_ctrl"; 1144 1145 clocks = <&mmcc DSI_M_AHB_CLK>, 1146 <&mmcc DSI_S_AHB_CLK>, 1147 <&mmcc AMP_AHB_CLK>, 1148 <&mmcc DSI_CLK>, 1149 <&mmcc DSI1_BYTE_CLK>, 1150 <&mmcc DSI_PIXEL_CLK>, 1151 <&mmcc DSI1_ESC_CLK>; 1152 clock-names = "iface", "bus", "core_mmss", 1153 "src", "byte", "pixel", 1154 "core"; 1155 1156 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1157 <&mmcc DSI1_ESC_SRC>, 1158 <&mmcc DSI_SRC>, 1159 <&mmcc DSI_PIXEL_SRC>; 1160 assigned-clock-parents = <&dsi0_phy 0>, 1161 <&dsi0_phy 0>, 1162 <&dsi0_phy 1>, 1163 <&dsi0_phy 1>; 1164 syscon-sfpb = <&mmss_sfpb>; 1165 phys = <&dsi0_phy>; 1166 status = "disabled"; 1167 1168 ports { 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 1172 port@0 { 1173 reg = <0>; 1174 dsi0_in: endpoint { 1175 }; 1176 }; 1177 1178 port@1 { 1179 reg = <1>; 1180 dsi0_out: endpoint { 1181 }; 1182 }; 1183 }; 1184 }; 1185 1186 1187 dsi0_phy: phy@4700200 { 1188 compatible = "qcom,dsi-phy-28nm-8960"; 1189 #clock-cells = <1>; 1190 #phy-cells = <0>; 1191 1192 reg = <0x04700200 0x100>, 1193 <0x04700300 0x200>, 1194 <0x04700500 0x5c>; 1195 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1196 clock-names = "iface", "ref"; 1197 clocks = <&mmcc DSI_M_AHB_CLK>, 1198 <&pxo_board>; 1199 status = "disabled"; 1200 }; 1201 1202 dsi1: dsi@5800000 { 1203 compatible = "qcom,mdss-dsi-ctrl"; 1204 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1205 reg = <0x05800000 0x200>; 1206 reg-names = "dsi_ctrl"; 1207 1208 clocks = <&mmcc DSI2_M_AHB_CLK>, 1209 <&mmcc DSI2_S_AHB_CLK>, 1210 <&mmcc AMP_AHB_CLK>, 1211 <&mmcc DSI2_CLK>, 1212 <&mmcc DSI2_BYTE_CLK>, 1213 <&mmcc DSI2_PIXEL_CLK>, 1214 <&mmcc DSI2_ESC_CLK>; 1215 clock-names = "iface", 1216 "bus", 1217 "core_mmss", 1218 "src", 1219 "byte", 1220 "pixel", 1221 "core"; 1222 1223 assigned-clocks = <&mmcc DSI2_BYTE_SRC>, 1224 <&mmcc DSI2_ESC_SRC>, 1225 <&mmcc DSI2_SRC>, 1226 <&mmcc DSI2_PIXEL_SRC>; 1227 assigned-clock-parents = <&dsi1_phy 0>, 1228 <&dsi1_phy 0>, 1229 <&dsi1_phy 1>, 1230 <&dsi1_phy 1>; 1231 1232 syscon-sfpb = <&mmss_sfpb>; 1233 phys = <&dsi1_phy>; 1234 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 1238 status = "disabled"; 1239 1240 ports { 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 1244 port@0 { 1245 reg = <0>; 1246 dsi1_in: endpoint { 1247 }; 1248 }; 1249 1250 port@1 { 1251 reg = <1>; 1252 dsi1_out: endpoint { 1253 }; 1254 }; 1255 }; 1256 }; 1257 1258 1259 dsi1_phy: dsi-phy@5800200 { 1260 compatible = "qcom,dsi-phy-28nm-8960"; 1261 reg = <0x05800200 0x100>, 1262 <0x05800300 0x200>, 1263 <0x05800500 0x5c>; 1264 reg-names = "dsi_pll", 1265 "dsi_phy", 1266 "dsi_phy_regulator"; 1267 clock-names = "iface", 1268 "ref"; 1269 clocks = <&mmcc DSI2_M_AHB_CLK>, 1270 <&pxo_board>; 1271 #clock-cells = <1>; 1272 #phy-cells = <0>; 1273 1274 status = "disabled"; 1275 }; 1276 1277 mdp_port0: iommu@7500000 { 1278 compatible = "qcom,apq8064-iommu"; 1279 #iommu-cells = <1>; 1280 clock-names = 1281 "smmu_pclk", 1282 "iommu_clk"; 1283 clocks = 1284 <&mmcc SMMU_AHB_CLK>, 1285 <&mmcc MDP_AXI_CLK>; 1286 reg = <0x07500000 0x100000>; 1287 interrupts = 1288 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1290 qcom,ncb = <2>; 1291 }; 1292 1293 mdp_port1: iommu@7600000 { 1294 compatible = "qcom,apq8064-iommu"; 1295 #iommu-cells = <1>; 1296 clock-names = 1297 "smmu_pclk", 1298 "iommu_clk"; 1299 clocks = 1300 <&mmcc SMMU_AHB_CLK>, 1301 <&mmcc MDP_AXI_CLK>; 1302 reg = <0x07600000 0x100000>; 1303 interrupts = 1304 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1306 qcom,ncb = <2>; 1307 }; 1308 1309 gfx3d: iommu@7c00000 { 1310 compatible = "qcom,apq8064-iommu"; 1311 #iommu-cells = <1>; 1312 clock-names = 1313 "smmu_pclk", 1314 "iommu_clk"; 1315 clocks = 1316 <&mmcc SMMU_AHB_CLK>, 1317 <&mmcc GFX3D_AXI_CLK>; 1318 reg = <0x07c00000 0x100000>; 1319 interrupts = 1320 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1322 qcom,ncb = <3>; 1323 }; 1324 1325 gfx3d1: iommu@7d00000 { 1326 compatible = "qcom,apq8064-iommu"; 1327 #iommu-cells = <1>; 1328 clock-names = 1329 "smmu_pclk", 1330 "iommu_clk"; 1331 clocks = 1332 <&mmcc SMMU_AHB_CLK>, 1333 <&mmcc GFX3D_AXI_CLK>; 1334 reg = <0x07d00000 0x100000>; 1335 interrupts = 1336 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1338 qcom,ncb = <3>; 1339 }; 1340 1341 pcie: pci@1b500000 { 1342 compatible = "qcom,pcie-apq8064"; 1343 reg = <0x1b500000 0x1000>, 1344 <0x1b502000 0x80>, 1345 <0x1b600000 0x100>, 1346 <0x0ff00000 0x100000>; 1347 reg-names = "dbi", "elbi", "parf", "config"; 1348 device_type = "pci"; 1349 linux,pci-domain = <0>; 1350 bus-range = <0x00 0xff>; 1351 num-lanes = <1>; 1352 #address-cells = <3>; 1353 #size-cells = <2>; 1354 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1355 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1356 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1357 interrupt-names = "msi"; 1358 #interrupt-cells = <1>; 1359 interrupt-map-mask = <0 0 0 0x7>; 1360 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1361 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1362 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1363 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1364 clocks = <&gcc PCIE_A_CLK>, 1365 <&gcc PCIE_H_CLK>, 1366 <&gcc PCIE_PHY_REF_CLK>; 1367 clock-names = "core", "iface", "phy"; 1368 resets = <&gcc PCIE_ACLK_RESET>, 1369 <&gcc PCIE_HCLK_RESET>, 1370 <&gcc PCIE_POR_RESET>, 1371 <&gcc PCIE_PCI_RESET>, 1372 <&gcc PCIE_PHY_RESET>; 1373 reset-names = "axi", "ahb", "por", "pci", "phy"; 1374 status = "disabled"; 1375 }; 1376 1377 hdmi: hdmi-tx@4a00000 { 1378 compatible = "qcom,hdmi-tx-8960"; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&hdmi_pinctrl>; 1381 reg = <0x04a00000 0x2f0>; 1382 reg-names = "core_physical"; 1383 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&mmcc HDMI_APP_CLK>, 1385 <&mmcc HDMI_M_AHB_CLK>, 1386 <&mmcc HDMI_S_AHB_CLK>; 1387 clock-names = "core", 1388 "master_iface", 1389 "slave_iface"; 1390 1391 phys = <&hdmi_phy>; 1392 1393 status = "disabled"; 1394 1395 ports { 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 1399 port@0 { 1400 reg = <0>; 1401 hdmi_in: endpoint { 1402 }; 1403 }; 1404 1405 port@1 { 1406 reg = <1>; 1407 hdmi_out: endpoint { 1408 }; 1409 }; 1410 }; 1411 }; 1412 1413 hdmi_phy: phy@4a00400 { 1414 compatible = "qcom,hdmi-phy-8960"; 1415 reg = <0x4a00400 0x60>, 1416 <0x4a00500 0x100>; 1417 reg-names = "hdmi_phy", 1418 "hdmi_pll"; 1419 1420 clocks = <&mmcc HDMI_S_AHB_CLK>; 1421 clock-names = "slave_iface"; 1422 #phy-cells = <0>; 1423 #clock-cells = <0>; 1424 1425 status = "disabled"; 1426 }; 1427 1428 mdp: display-controller@5100000 { 1429 compatible = "qcom,mdp4"; 1430 reg = <0x05100000 0xf0000>; 1431 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&mmcc MDP_CLK>, 1433 <&mmcc MDP_AHB_CLK>, 1434 <&mmcc MDP_AXI_CLK>, 1435 <&mmcc MDP_LUT_CLK>, 1436 <&mmcc HDMI_TV_CLK>, 1437 <&mmcc MDP_TV_CLK>; 1438 clock-names = "core_clk", 1439 "iface_clk", 1440 "bus_clk", 1441 "lut_clk", 1442 "hdmi_clk", 1443 "tv_clk"; 1444 1445 iommus = <&mdp_port0 0 1446 &mdp_port0 2 1447 &mdp_port1 0 1448 &mdp_port1 2>; 1449 1450 ports { 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 1454 port@0 { 1455 reg = <0>; 1456 mdp_lvds_out: endpoint { 1457 }; 1458 }; 1459 1460 port@1 { 1461 reg = <1>; 1462 mdp_dsi1_out: endpoint { 1463 }; 1464 }; 1465 1466 port@2 { 1467 reg = <2>; 1468 mdp_dsi2_out: endpoint { 1469 }; 1470 }; 1471 1472 port@3 { 1473 reg = <3>; 1474 mdp_dtv_out: endpoint { 1475 }; 1476 }; 1477 }; 1478 }; 1479 1480 riva: riva-pil@3200800 { 1481 compatible = "qcom,riva-pil"; 1482 1483 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1484 reg-names = "ccu", "dxe", "pmu"; 1485 1486 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1487 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1488 interrupt-names = "wdog", "fatal"; 1489 1490 memory-region = <&wcnss_mem>; 1491 1492 vddcx-supply = <&pm8921_s3>; 1493 vddmx-supply = <&pm8921_l24>; 1494 vddpx-supply = <&pm8921_s4>; 1495 1496 status = "disabled"; 1497 1498 iris { 1499 compatible = "qcom,wcn3660"; 1500 1501 clocks = <&cxo_board>; 1502 clock-names = "xo"; 1503 1504 vddxo-supply = <&pm8921_l4>; 1505 vddrfa-supply = <&pm8921_s2>; 1506 vddpa-supply = <&pm8921_l10>; 1507 vdddig-supply = <&pm8921_lvs2>; 1508 }; 1509 1510 smd-edge { 1511 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1512 1513 qcom,ipc = <&l2cc 8 25>; 1514 qcom,smd-edge = <6>; 1515 1516 label = "riva"; 1517 1518 wcnss { 1519 compatible = "qcom,wcnss"; 1520 qcom,smd-channels = "WCNSS_CTRL"; 1521 1522 qcom,mmio = <&riva>; 1523 1524 bluetooth { 1525 compatible = "qcom,wcnss-bt"; 1526 }; 1527 1528 wifi { 1529 compatible = "qcom,wcnss-wlan"; 1530 1531 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1533 interrupt-names = "tx", "rx"; 1534 1535 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1536 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1537 }; 1538 }; 1539 }; 1540 }; 1541 1542 etb@1a01000 { 1543 compatible = "arm,coresight-etb10", "arm,primecell"; 1544 reg = <0x1a01000 0x1000>; 1545 1546 clocks = <&rpmcc RPM_QDSS_CLK>; 1547 clock-names = "apb_pclk"; 1548 1549 in-ports { 1550 port { 1551 etb_in: endpoint { 1552 remote-endpoint = <&replicator_out0>; 1553 }; 1554 }; 1555 }; 1556 }; 1557 1558 tpiu@1a03000 { 1559 compatible = "arm,coresight-tpiu", "arm,primecell"; 1560 reg = <0x1a03000 0x1000>; 1561 1562 clocks = <&rpmcc RPM_QDSS_CLK>; 1563 clock-names = "apb_pclk"; 1564 1565 in-ports { 1566 port { 1567 tpiu_in: endpoint { 1568 remote-endpoint = <&replicator_out1>; 1569 }; 1570 }; 1571 }; 1572 }; 1573 1574 replicator { 1575 compatible = "arm,coresight-static-replicator"; 1576 1577 clocks = <&rpmcc RPM_QDSS_CLK>; 1578 clock-names = "apb_pclk"; 1579 1580 out-ports { 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 1584 port@0 { 1585 reg = <0>; 1586 replicator_out0: endpoint { 1587 remote-endpoint = <&etb_in>; 1588 }; 1589 }; 1590 port@1 { 1591 reg = <1>; 1592 replicator_out1: endpoint { 1593 remote-endpoint = <&tpiu_in>; 1594 }; 1595 }; 1596 }; 1597 1598 in-ports { 1599 port { 1600 replicator_in: endpoint { 1601 remote-endpoint = <&funnel_out>; 1602 }; 1603 }; 1604 }; 1605 }; 1606 1607 funnel@1a04000 { 1608 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1609 reg = <0x1a04000 0x1000>; 1610 1611 clocks = <&rpmcc RPM_QDSS_CLK>; 1612 clock-names = "apb_pclk"; 1613 1614 in-ports { 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 1618 /* 1619 * Not described input ports: 1620 * 2 - connected to STM component 1621 * 3 - not-connected 1622 * 6 - not-connected 1623 * 7 - not-connected 1624 */ 1625 port@0 { 1626 reg = <0>; 1627 funnel_in0: endpoint { 1628 remote-endpoint = <&etm0_out>; 1629 }; 1630 }; 1631 port@1 { 1632 reg = <1>; 1633 funnel_in1: endpoint { 1634 remote-endpoint = <&etm1_out>; 1635 }; 1636 }; 1637 port@4 { 1638 reg = <4>; 1639 funnel_in4: endpoint { 1640 remote-endpoint = <&etm2_out>; 1641 }; 1642 }; 1643 port@5 { 1644 reg = <5>; 1645 funnel_in5: endpoint { 1646 remote-endpoint = <&etm3_out>; 1647 }; 1648 }; 1649 }; 1650 1651 out-ports { 1652 port { 1653 funnel_out: endpoint { 1654 remote-endpoint = <&replicator_in>; 1655 }; 1656 }; 1657 }; 1658 }; 1659 1660 etm@1a1c000 { 1661 compatible = "arm,coresight-etm3x", "arm,primecell"; 1662 reg = <0x1a1c000 0x1000>; 1663 1664 clocks = <&rpmcc RPM_QDSS_CLK>; 1665 clock-names = "apb_pclk"; 1666 1667 cpu = <&CPU0>; 1668 1669 out-ports { 1670 port { 1671 etm0_out: endpoint { 1672 remote-endpoint = <&funnel_in0>; 1673 }; 1674 }; 1675 }; 1676 }; 1677 1678 etm@1a1d000 { 1679 compatible = "arm,coresight-etm3x", "arm,primecell"; 1680 reg = <0x1a1d000 0x1000>; 1681 1682 clocks = <&rpmcc RPM_QDSS_CLK>; 1683 clock-names = "apb_pclk"; 1684 1685 cpu = <&CPU1>; 1686 1687 out-ports { 1688 port { 1689 etm1_out: endpoint { 1690 remote-endpoint = <&funnel_in1>; 1691 }; 1692 }; 1693 }; 1694 }; 1695 1696 etm@1a1e000 { 1697 compatible = "arm,coresight-etm3x", "arm,primecell"; 1698 reg = <0x1a1e000 0x1000>; 1699 1700 clocks = <&rpmcc RPM_QDSS_CLK>; 1701 clock-names = "apb_pclk"; 1702 1703 cpu = <&CPU2>; 1704 1705 out-ports { 1706 port { 1707 etm2_out: endpoint { 1708 remote-endpoint = <&funnel_in4>; 1709 }; 1710 }; 1711 }; 1712 }; 1713 1714 etm@1a1f000 { 1715 compatible = "arm,coresight-etm3x", "arm,primecell"; 1716 reg = <0x1a1f000 0x1000>; 1717 1718 clocks = <&rpmcc RPM_QDSS_CLK>; 1719 clock-names = "apb_pclk"; 1720 1721 cpu = <&CPU3>; 1722 1723 out-ports { 1724 port { 1725 etm3_out: endpoint { 1726 remote-endpoint = <&funnel_in5>; 1727 }; 1728 }; 1729 }; 1730 }; 1731 }; 1732}; 1733#include "qcom-apq8064-pins.dtsi" 1734