1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2018-2022 TQ-Systems GmbH 4*724ba675SRob Herring * Author: Markus Niebel <Markus.Niebel@tq-group.com> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include "imx6ull.dtsi" 8*724ba675SRob Herring#include "imx6ul-tqma6ul-common.dtsi" 9*724ba675SRob Herring#include "imx6ul-tqma6ulxl-common.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring model = "TQ Systems TQMa6ULL2L SoM"; 13*724ba675SRob Herring compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; 14*724ba675SRob Herring}; 15*724ba675SRob Herring 16*724ba675SRob Herring&usdhc2 { 17*724ba675SRob Herring fsl,tuning-step = <6>; 18*724ba675SRob Herring /* Errata ERR010450 Workaround */ 19*724ba675SRob Herring max-frequency = <99000000>; 20*724ba675SRob Herring assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; 21*724ba675SRob Herring assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 22*724ba675SRob Herring assigned-clock-rates = <0>, <198000000>; 23*724ba675SRob Herring}; 24*724ba675SRob Herring 25*724ba675SRob Herring&iomuxc { 26*724ba675SRob Herring pinctrl_usdhc2: usdhc2grp { 27*724ba675SRob Herring fsl,pins = < 28*724ba675SRob Herring MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 29*724ba675SRob Herring MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 30*724ba675SRob Herring MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 31*724ba675SRob Herring MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 32*724ba675SRob Herring MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 33*724ba675SRob Herring MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 34*724ba675SRob Herring MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 35*724ba675SRob Herring MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 36*724ba675SRob Herring MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 37*724ba675SRob Herring MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 38*724ba675SRob Herring /* rst */ 39*724ba675SRob Herring MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 40*724ba675SRob Herring >; 41*724ba675SRob Herring }; 42*724ba675SRob Herring 43*724ba675SRob Herring pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 44*724ba675SRob Herring fsl,pins = < 45*724ba675SRob Herring MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 46*724ba675SRob Herring MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 47*724ba675SRob Herring MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 48*724ba675SRob Herring MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 49*724ba675SRob Herring MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 50*724ba675SRob Herring MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 51*724ba675SRob Herring MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 52*724ba675SRob Herring MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 53*724ba675SRob Herring MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 54*724ba675SRob Herring MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 55*724ba675SRob Herring /* rst */ 56*724ba675SRob Herring MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 57*724ba675SRob Herring >; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 61*724ba675SRob Herring fsl,pins = < 62*724ba675SRob Herring MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 63*724ba675SRob Herring MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 64*724ba675SRob Herring MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 65*724ba675SRob Herring MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 66*724ba675SRob Herring MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 67*724ba675SRob Herring MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 68*724ba675SRob Herring MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 69*724ba675SRob Herring MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 70*724ba675SRob Herring MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 71*724ba675SRob Herring MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 72*724ba675SRob Herring /* rst */ 73*724ba675SRob Herring MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 74*724ba675SRob Herring >; 75*724ba675SRob Herring }; 76*724ba675SRob Herring}; 77