1*e3b56971SParthiban Nallathambi// SPDX-License-Identifier: GPL-2.0 2*e3b56971SParthiban Nallathambi/* 3*e3b56971SParthiban Nallathambi * Copyright (c) 2024 Linumiz 4*e3b56971SParthiban Nallathambi * Author: Parthiban <parthiban@linumiz.com> 5*e3b56971SParthiban Nallathambi */ 6*e3b56971SParthiban Nallathambi 7*e3b56971SParthiban Nallathambi#include <dt-bindings/gpio/gpio.h> 8*e3b56971SParthiban Nallathambi 9*e3b56971SParthiban Nallathambi/ { 10*e3b56971SParthiban Nallathambi chosen { 11*e3b56971SParthiban Nallathambi stdout-path = &uart1; 12*e3b56971SParthiban Nallathambi }; 13*e3b56971SParthiban Nallathambi 14*e3b56971SParthiban Nallathambi gpio_buttons: gpio-keys { 15*e3b56971SParthiban Nallathambi compatible = "gpio-keys"; 16*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 17*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_button>; 18*e3b56971SParthiban Nallathambi 19*e3b56971SParthiban Nallathambi button-0 { 20*e3b56971SParthiban Nallathambi gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; 21*e3b56971SParthiban Nallathambi label = "SW2"; 22*e3b56971SParthiban Nallathambi linux,code = <KEY_A>; 23*e3b56971SParthiban Nallathambi wakeup-source; 24*e3b56971SParthiban Nallathambi }; 25*e3b56971SParthiban Nallathambi }; 26*e3b56971SParthiban Nallathambi 27*e3b56971SParthiban Nallathambi gpio-leds { 28*e3b56971SParthiban Nallathambi compatible = "gpio-leds"; 29*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 30*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_gpio_leds>; 31*e3b56971SParthiban Nallathambi 32*e3b56971SParthiban Nallathambi led-blue { 33*e3b56971SParthiban Nallathambi gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 34*e3b56971SParthiban Nallathambi label = "LED_B"; 35*e3b56971SParthiban Nallathambi linux,default-trigger = "heartbeat"; 36*e3b56971SParthiban Nallathambi default-state = "on"; 37*e3b56971SParthiban Nallathambi }; 38*e3b56971SParthiban Nallathambi 39*e3b56971SParthiban Nallathambi led-green { 40*e3b56971SParthiban Nallathambi gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; 41*e3b56971SParthiban Nallathambi label = "LED_G"; 42*e3b56971SParthiban Nallathambi linux,default-trigger = "heartbeat"; 43*e3b56971SParthiban Nallathambi default-state = "on"; 44*e3b56971SParthiban Nallathambi }; 45*e3b56971SParthiban Nallathambi 46*e3b56971SParthiban Nallathambi led-red { 47*e3b56971SParthiban Nallathambi gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 48*e3b56971SParthiban Nallathambi label = "LED_R"; 49*e3b56971SParthiban Nallathambi linux,default-trigger = "heartbeat"; 50*e3b56971SParthiban Nallathambi default-state = "on"; 51*e3b56971SParthiban Nallathambi }; 52*e3b56971SParthiban Nallathambi 53*e3b56971SParthiban Nallathambi led-user { 54*e3b56971SParthiban Nallathambi gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; 55*e3b56971SParthiban Nallathambi label = "User"; 56*e3b56971SParthiban Nallathambi linux,default-trigger = "heartbeat"; 57*e3b56971SParthiban Nallathambi default-state = "on"; 58*e3b56971SParthiban Nallathambi }; 59*e3b56971SParthiban Nallathambi }; 60*e3b56971SParthiban Nallathambi 61*e3b56971SParthiban Nallathambi reg_5v_sys: regulator-5v-sys { 62*e3b56971SParthiban Nallathambi compatible = "regulator-fixed"; 63*e3b56971SParthiban Nallathambi regulator-name = "5V_SYS"; 64*e3b56971SParthiban Nallathambi regulator-min-microvolt = <5000000>; 65*e3b56971SParthiban Nallathambi regulator-max-microvolt = <5000000>; 66*e3b56971SParthiban Nallathambi regulator-always-on; 67*e3b56971SParthiban Nallathambi }; 68*e3b56971SParthiban Nallathambi 69*e3b56971SParthiban Nallathambi reg_5v: regulator-5v { 70*e3b56971SParthiban Nallathambi compatible = "regulator-fixed"; 71*e3b56971SParthiban Nallathambi regulator-name = "5V"; 72*e3b56971SParthiban Nallathambi regulator-min-microvolt = <5000000>; 73*e3b56971SParthiban Nallathambi regulator-max-microvolt = <5000000>; 74*e3b56971SParthiban Nallathambi regulator-always-on; 75*e3b56971SParthiban Nallathambi vin-supply = <®_5v_sys>; 76*e3b56971SParthiban Nallathambi }; 77*e3b56971SParthiban Nallathambi 78*e3b56971SParthiban Nallathambi reg_3v3_in: regulator-3v3-in { 79*e3b56971SParthiban Nallathambi compatible = "regulator-fixed"; 80*e3b56971SParthiban Nallathambi regulator-name = "3V3_IN"; 81*e3b56971SParthiban Nallathambi regulator-min-microvolt = <3300000>; 82*e3b56971SParthiban Nallathambi regulator-max-microvolt = <3300000>; 83*e3b56971SParthiban Nallathambi regulator-always-on; 84*e3b56971SParthiban Nallathambi vin-supply = <®_5v_sys>; 85*e3b56971SParthiban Nallathambi }; 86*e3b56971SParthiban Nallathambi 87*e3b56971SParthiban Nallathambi reg_3v3: regulator-3v3 { 88*e3b56971SParthiban Nallathambi compatible = "regulator-fixed"; 89*e3b56971SParthiban Nallathambi regulator-name = "3V3"; 90*e3b56971SParthiban Nallathambi regulator-min-microvolt = <3300000>; 91*e3b56971SParthiban Nallathambi regulator-max-microvolt = <3300000>; 92*e3b56971SParthiban Nallathambi regulator-always-on; 93*e3b56971SParthiban Nallathambi vin-supply = <®_3v3_in>; 94*e3b56971SParthiban Nallathambi }; 95*e3b56971SParthiban Nallathambi 96*e3b56971SParthiban Nallathambi reg_sd1_vmmc: regulator-sd1-vmmc { 97*e3b56971SParthiban Nallathambi compatible = "regulator-fixed"; 98*e3b56971SParthiban Nallathambi regulator-name = "3V3_SD"; 99*e3b56971SParthiban Nallathambi regulator-min-microvolt = <3300000>; 100*e3b56971SParthiban Nallathambi regulator-max-microvolt = <3300000>; 101*e3b56971SParthiban Nallathambi gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 102*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 103*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_reg_vmmc>; 104*e3b56971SParthiban Nallathambi enable-active-high; 105*e3b56971SParthiban Nallathambi regulator-always-on; 106*e3b56971SParthiban Nallathambi vin-supply = <®_3v3>; 107*e3b56971SParthiban Nallathambi }; 108*e3b56971SParthiban Nallathambi}; 109*e3b56971SParthiban Nallathambi 110*e3b56971SParthiban Nallathambi&csi { 111*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 112*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_csi1>; 113*e3b56971SParthiban Nallathambi status = "disabled"; /* LED Blue & Green shared */ 114*e3b56971SParthiban Nallathambi}; 115*e3b56971SParthiban Nallathambi 116*e3b56971SParthiban Nallathambi&fec1 { 117*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 118*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_enet1>; 119*e3b56971SParthiban Nallathambi phy-mode = "rmii"; 120*e3b56971SParthiban Nallathambi phy-handle = <ðphy0>; 121*e3b56971SParthiban Nallathambi status = "okay"; 122*e3b56971SParthiban Nallathambi}; 123*e3b56971SParthiban Nallathambi 124*e3b56971SParthiban Nallathambi&fec2 { 125*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 126*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_enet2>; 127*e3b56971SParthiban Nallathambi phy-mode = "rmii"; 128*e3b56971SParthiban Nallathambi phy-handle = <ðphy1>; 129*e3b56971SParthiban Nallathambi status = "okay"; 130*e3b56971SParthiban Nallathambi 131*e3b56971SParthiban Nallathambi mdio { 132*e3b56971SParthiban Nallathambi #address-cells = <1>; 133*e3b56971SParthiban Nallathambi #size-cells = <0>; 134*e3b56971SParthiban Nallathambi 135*e3b56971SParthiban Nallathambi ethphy0: ethernet-phy@2 { 136*e3b56971SParthiban Nallathambi compatible = "ethernet-phy-ieee802.3-c22"; 137*e3b56971SParthiban Nallathambi reg = <2>; 138*e3b56971SParthiban Nallathambi micrel,led-mode = <1>; 139*e3b56971SParthiban Nallathambi clocks = <&clks IMX6UL_CLK_ENET_REF>; 140*e3b56971SParthiban Nallathambi clock-names = "rmii-ref"; 141*e3b56971SParthiban Nallathambi }; 142*e3b56971SParthiban Nallathambi 143*e3b56971SParthiban Nallathambi ethphy1: ethernet-phy@1 { 144*e3b56971SParthiban Nallathambi compatible = "ethernet-phy-ieee802.3-c22"; 145*e3b56971SParthiban Nallathambi reg = <1>; 146*e3b56971SParthiban Nallathambi micrel,led-mode = <1>; 147*e3b56971SParthiban Nallathambi clocks = <&clks IMX6UL_CLK_ENET2_REF>; 148*e3b56971SParthiban Nallathambi clock-names = "rmii-ref"; 149*e3b56971SParthiban Nallathambi }; 150*e3b56971SParthiban Nallathambi }; 151*e3b56971SParthiban Nallathambi}; 152*e3b56971SParthiban Nallathambi 153*e3b56971SParthiban Nallathambi&lcdif { 154*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_lcdif>; 155*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 156*e3b56971SParthiban Nallathambi status = "disabled"; 157*e3b56971SParthiban Nallathambi}; 158*e3b56971SParthiban Nallathambi 159*e3b56971SParthiban Nallathambi®_dcdc_3v3 { 160*e3b56971SParthiban Nallathambi vin-supply = <®_3v3_in>; 161*e3b56971SParthiban Nallathambi}; 162*e3b56971SParthiban Nallathambi 163*e3b56971SParthiban Nallathambi&sai2 { 164*e3b56971SParthiban Nallathambi assigned-clock-rates = <320000000>; 165*e3b56971SParthiban Nallathambi assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; 166*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_sai2>; 167*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 168*e3b56971SParthiban Nallathambi status = "okay"; 169*e3b56971SParthiban Nallathambi}; 170*e3b56971SParthiban Nallathambi 171*e3b56971SParthiban Nallathambi&snvs_poweroff { 172*e3b56971SParthiban Nallathambi status = "okay"; 173*e3b56971SParthiban Nallathambi}; 174*e3b56971SParthiban Nallathambi 175*e3b56971SParthiban Nallathambi&uart1 { 176*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_uart1>; 177*e3b56971SParthiban Nallathambi status = "okay"; 178*e3b56971SParthiban Nallathambi}; 179*e3b56971SParthiban Nallathambi 180*e3b56971SParthiban Nallathambi&uart2 { 181*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_uart2>; 182*e3b56971SParthiban Nallathambi uart-has-rtscts; 183*e3b56971SParthiban Nallathambi status = "okay"; 184*e3b56971SParthiban Nallathambi}; 185*e3b56971SParthiban Nallathambi 186*e3b56971SParthiban Nallathambi&uart3 { 187*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_uart3>; 188*e3b56971SParthiban Nallathambi uart-has-rtscts; 189*e3b56971SParthiban Nallathambi status = "okay"; 190*e3b56971SParthiban Nallathambi}; 191*e3b56971SParthiban Nallathambi 192*e3b56971SParthiban Nallathambi&uart4 { 193*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_uart4>; 194*e3b56971SParthiban Nallathambi status = "okay"; 195*e3b56971SParthiban Nallathambi}; 196*e3b56971SParthiban Nallathambi 197*e3b56971SParthiban Nallathambi&uart5 { 198*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_uart5>; 199*e3b56971SParthiban Nallathambi status = "okay"; 200*e3b56971SParthiban Nallathambi}; 201*e3b56971SParthiban Nallathambi 202*e3b56971SParthiban Nallathambi&usbotg1 { 203*e3b56971SParthiban Nallathambi pinctrl-names = "default"; 204*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_usb_otg1_id>; 205*e3b56971SParthiban Nallathambi dr_mode = "otg"; 206*e3b56971SParthiban Nallathambi srp-disable; 207*e3b56971SParthiban Nallathambi hnp-disable; 208*e3b56971SParthiban Nallathambi adp-disable; 209*e3b56971SParthiban Nallathambi status = "okay"; 210*e3b56971SParthiban Nallathambi}; 211*e3b56971SParthiban Nallathambi 212*e3b56971SParthiban Nallathambi&usbotg2 { 213*e3b56971SParthiban Nallathambi dr_mode = "host"; 214*e3b56971SParthiban Nallathambi disable-over-current; 215*e3b56971SParthiban Nallathambi status = "okay"; 216*e3b56971SParthiban Nallathambi}; 217*e3b56971SParthiban Nallathambi 218*e3b56971SParthiban Nallathambi&usdhc1 { 219*e3b56971SParthiban Nallathambi pinctrl-names = "default", "state_100mhz", "state_200mhz"; 220*e3b56971SParthiban Nallathambi pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; 221*e3b56971SParthiban Nallathambi pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_cd>; 222*e3b56971SParthiban Nallathambi pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_cd>; 223*e3b56971SParthiban Nallathambi cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 224*e3b56971SParthiban Nallathambi no-1-8-v; 225*e3b56971SParthiban Nallathambi keep-power-in-suspend; 226*e3b56971SParthiban Nallathambi wakeup-source; 227*e3b56971SParthiban Nallathambi vmmc-supply = <®_sd1_vmmc>; 228*e3b56971SParthiban Nallathambi status = "okay"; 229*e3b56971SParthiban Nallathambi}; 230*e3b56971SParthiban Nallathambi 231*e3b56971SParthiban Nallathambi&iomuxc { 232*e3b56971SParthiban Nallathambi pinctrl_button: buttongrp { 233*e3b56971SParthiban Nallathambi fsl,pins = < 234*e3b56971SParthiban Nallathambi MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 235*e3b56971SParthiban Nallathambi >; 236*e3b56971SParthiban Nallathambi }; 237*e3b56971SParthiban Nallathambi 238*e3b56971SParthiban Nallathambi pinctrl_csi1: csi1grp { 239*e3b56971SParthiban Nallathambi fsl,pins = < 240*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 241*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 242*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 243*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 244*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 245*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 246*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 247*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 248*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 249*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 250*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 251*e3b56971SParthiban Nallathambi >; 252*e3b56971SParthiban Nallathambi }; 253*e3b56971SParthiban Nallathambi 254*e3b56971SParthiban Nallathambi pinctrl_enet1: enet1grp { 255*e3b56971SParthiban Nallathambi fsl,pins = < 256*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 257*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 258*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 259*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 260*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 261*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 262*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 263*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 264*e3b56971SParthiban Nallathambi >; 265*e3b56971SParthiban Nallathambi }; 266*e3b56971SParthiban Nallathambi 267*e3b56971SParthiban Nallathambi pinctrl_enet2: enet2grp { 268*e3b56971SParthiban Nallathambi fsl,pins = < 269*e3b56971SParthiban Nallathambi MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 270*e3b56971SParthiban Nallathambi MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 271*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 272*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 273*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 274*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 275*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 276*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 277*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 278*e3b56971SParthiban Nallathambi MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 279*e3b56971SParthiban Nallathambi >; 280*e3b56971SParthiban Nallathambi }; 281*e3b56971SParthiban Nallathambi 282*e3b56971SParthiban Nallathambi pinctrl_gpio_leds: ledgrp { 283*e3b56971SParthiban Nallathambi fsl,pins = < 284*e3b56971SParthiban Nallathambi MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x0b0b0 285*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x0b0b0 286*e3b56971SParthiban Nallathambi MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x0b0b0 287*e3b56971SParthiban Nallathambi MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 288*e3b56971SParthiban Nallathambi >; 289*e3b56971SParthiban Nallathambi }; 290*e3b56971SParthiban Nallathambi 291*e3b56971SParthiban Nallathambi pinctrl_lcdif: lcdif-grp { 292*e3b56971SParthiban Nallathambi fsl,pins = < 293*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 294*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 295*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 296*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 297*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 298*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 299*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 300*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 301*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 302*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 303*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 304*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 305*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 306*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 307*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 308*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 309*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 310*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 311*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 312*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 313*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 314*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 315*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 316*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 317*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 318*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 319*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 320*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 321*e3b56971SParthiban Nallathambi MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 322*e3b56971SParthiban Nallathambi MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x79 323*e3b56971SParthiban Nallathambi >; 324*e3b56971SParthiban Nallathambi }; 325*e3b56971SParthiban Nallathambi 326*e3b56971SParthiban Nallathambi pinctrl_reg_vmmc: usdhc1regvmmc { 327*e3b56971SParthiban Nallathambi fsl,pins = < 328*e3b56971SParthiban Nallathambi MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 329*e3b56971SParthiban Nallathambi >; 330*e3b56971SParthiban Nallathambi }; 331*e3b56971SParthiban Nallathambi 332*e3b56971SParthiban Nallathambi pinctrl_sai2: sai2-grp { 333*e3b56971SParthiban Nallathambi fsl,pins = < 334*e3b56971SParthiban Nallathambi MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 335*e3b56971SParthiban Nallathambi MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 336*e3b56971SParthiban Nallathambi MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 337*e3b56971SParthiban Nallathambi MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 338*e3b56971SParthiban Nallathambi >; 339*e3b56971SParthiban Nallathambi }; 340*e3b56971SParthiban Nallathambi 341*e3b56971SParthiban Nallathambi pinctrl_uart1: uart1grp { 342*e3b56971SParthiban Nallathambi fsl,pin = < 343*e3b56971SParthiban Nallathambi MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 344*e3b56971SParthiban Nallathambi MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 345*e3b56971SParthiban Nallathambi >; 346*e3b56971SParthiban Nallathambi }; 347*e3b56971SParthiban Nallathambi 348*e3b56971SParthiban Nallathambi pinctrl_uart2: uart2grp { 349*e3b56971SParthiban Nallathambi fsl,pin = < 350*e3b56971SParthiban Nallathambi MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 351*e3b56971SParthiban Nallathambi MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 352*e3b56971SParthiban Nallathambi MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 353*e3b56971SParthiban Nallathambi MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 354*e3b56971SParthiban Nallathambi >; 355*e3b56971SParthiban Nallathambi }; 356*e3b56971SParthiban Nallathambi 357*e3b56971SParthiban Nallathambi pinctrl_uart3: uart3grp { 358*e3b56971SParthiban Nallathambi fsl,pin = < 359*e3b56971SParthiban Nallathambi MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 360*e3b56971SParthiban Nallathambi MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 361*e3b56971SParthiban Nallathambi MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 362*e3b56971SParthiban Nallathambi MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 363*e3b56971SParthiban Nallathambi >; 364*e3b56971SParthiban Nallathambi }; 365*e3b56971SParthiban Nallathambi 366*e3b56971SParthiban Nallathambi pinctrl_uart4: uart4grp { 367*e3b56971SParthiban Nallathambi fsl,pin = < 368*e3b56971SParthiban Nallathambi MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 369*e3b56971SParthiban Nallathambi MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 370*e3b56971SParthiban Nallathambi >; 371*e3b56971SParthiban Nallathambi }; 372*e3b56971SParthiban Nallathambi 373*e3b56971SParthiban Nallathambi pinctrl_uart5: uart5grp { 374*e3b56971SParthiban Nallathambi fsl,pin = < 375*e3b56971SParthiban Nallathambi MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 376*e3b56971SParthiban Nallathambi MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 377*e3b56971SParthiban Nallathambi >; 378*e3b56971SParthiban Nallathambi }; 379*e3b56971SParthiban Nallathambi 380*e3b56971SParthiban Nallathambi pinctrl_usb_otg1_id: usbotg1idgrp { 381*e3b56971SParthiban Nallathambi fsl,pin = < 382*e3b56971SParthiban Nallathambi MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 383*e3b56971SParthiban Nallathambi >; 384*e3b56971SParthiban Nallathambi }; 385*e3b56971SParthiban Nallathambi 386*e3b56971SParthiban Nallathambi pinctrl_usdhc1: usdhc1grp { 387*e3b56971SParthiban Nallathambi fsl,pins = < 388*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 389*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 390*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 391*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 392*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 393*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 394*e3b56971SParthiban Nallathambi >; 395*e3b56971SParthiban Nallathambi }; 396*e3b56971SParthiban Nallathambi 397*e3b56971SParthiban Nallathambi pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 398*e3b56971SParthiban Nallathambi fsl,pins = < 399*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 400*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 401*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 402*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 403*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 404*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 405*e3b56971SParthiban Nallathambi >; 406*e3b56971SParthiban Nallathambi }; 407*e3b56971SParthiban Nallathambi 408*e3b56971SParthiban Nallathambi pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 409*e3b56971SParthiban Nallathambi fsl,pins = < 410*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 411*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 412*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 413*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 414*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 415*e3b56971SParthiban Nallathambi MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 416*e3b56971SParthiban Nallathambi >; 417*e3b56971SParthiban Nallathambi }; 418*e3b56971SParthiban Nallathambi 419*e3b56971SParthiban Nallathambi pinctrl_usdhc1_cd: usdhc1cd { 420*e3b56971SParthiban Nallathambi fsl,pins = < 421*e3b56971SParthiban Nallathambi MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 422*e3b56971SParthiban Nallathambi >; 423*e3b56971SParthiban Nallathambi }; 424*e3b56971SParthiban Nallathambi}; 425