xref: /linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ul-var-som-concerto-common.dtsi (revision b2128290c29902315e632ea59e0504d6bc9e9b42)
119435b53SHugo Villeneuve// SPDX-License-Identifier: GPL-2.0+
219435b53SHugo Villeneuve/*
319435b53SHugo Villeneuve * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL
419435b53SHugo Villeneuve * Variscite SoM mounted on it (all CPU variants)
519435b53SHugo Villeneuve *
619435b53SHugo Villeneuve * Copyright 2019 Variscite Ltd.
719435b53SHugo Villeneuve * Copyright 2025 Bootlin
819435b53SHugo Villeneuve */
919435b53SHugo Villeneuve
1019435b53SHugo Villeneuve#include <dt-bindings/leds/common.h>
1119435b53SHugo Villeneuve
1219435b53SHugo Villeneuve/ {
1319435b53SHugo Villeneuve	chosen {
1419435b53SHugo Villeneuve		stdout-path = &uart1;
1519435b53SHugo Villeneuve	};
1619435b53SHugo Villeneuve
1719435b53SHugo Villeneuve	gpio-keys {
1819435b53SHugo Villeneuve		compatible = "gpio-keys";
1919435b53SHugo Villeneuve		pinctrl-names = "default";
2019435b53SHugo Villeneuve		pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
2119435b53SHugo Villeneuve
2219435b53SHugo Villeneuve		key-back {
2319435b53SHugo Villeneuve			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
2419435b53SHugo Villeneuve			linux,code = <KEY_BACK>;
2519435b53SHugo Villeneuve		};
2619435b53SHugo Villeneuve
2719435b53SHugo Villeneuve		key-wakeup {
2819435b53SHugo Villeneuve			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
2919435b53SHugo Villeneuve			linux,code = <KEY_WAKEUP>;
3019435b53SHugo Villeneuve			wakeup-source;
3119435b53SHugo Villeneuve		};
3219435b53SHugo Villeneuve	};
3319435b53SHugo Villeneuve
3419435b53SHugo Villeneuve	leds {
3519435b53SHugo Villeneuve		compatible = "gpio-leds";
3619435b53SHugo Villeneuve		pinctrl-names = "default";
3719435b53SHugo Villeneuve		pinctrl-0 = <&pinctrl_gpio_leds>;
3819435b53SHugo Villeneuve
3919435b53SHugo Villeneuve		led-0 {
4019435b53SHugo Villeneuve			function = LED_FUNCTION_STATUS;
4119435b53SHugo Villeneuve			color = <LED_COLOR_ID_GREEN>;
4219435b53SHugo Villeneuve			label = "gpled2";
4319435b53SHugo Villeneuve			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
4419435b53SHugo Villeneuve			linux,default-trigger = "heartbeat";
4519435b53SHugo Villeneuve		};
4619435b53SHugo Villeneuve	};
47*fe886aecSHugo Villeneuve
48*fe886aecSHugo Villeneuve	lvds_panel: lvds-panel {
49*fe886aecSHugo Villeneuve		compatible = "sgd,gktw70sdae4se", "panel-lvds";
50*fe886aecSHugo Villeneuve		data-mapping = "jeida-18";
51*fe886aecSHugo Villeneuve		width-mm = <153>;
52*fe886aecSHugo Villeneuve		height-mm = <86>;
53*fe886aecSHugo Villeneuve
54*fe886aecSHugo Villeneuve		panel-timing {
55*fe886aecSHugo Villeneuve			clock-frequency = <35000000>;
56*fe886aecSHugo Villeneuve			hactive = <800>;
57*fe886aecSHugo Villeneuve			vactive = <480>;
58*fe886aecSHugo Villeneuve			hback-porch = <40>;
59*fe886aecSHugo Villeneuve			hfront-porch = <40>;
60*fe886aecSHugo Villeneuve			vback-porch = <29>;
61*fe886aecSHugo Villeneuve			vfront-porch = <13>;
62*fe886aecSHugo Villeneuve			hsync-len = <48>;
63*fe886aecSHugo Villeneuve			vsync-len = <3>;
64*fe886aecSHugo Villeneuve			hsync-active = <0>;
65*fe886aecSHugo Villeneuve			vsync-active = <0>;
66*fe886aecSHugo Villeneuve			de-active = <1>;
67*fe886aecSHugo Villeneuve			pixelclk-active = <0>;
68*fe886aecSHugo Villeneuve		};
69*fe886aecSHugo Villeneuve	};
7019435b53SHugo Villeneuve};
7119435b53SHugo Villeneuve
7219435b53SHugo Villeneuve&can1 {
7319435b53SHugo Villeneuve	pinctrl-names = "default";
7419435b53SHugo Villeneuve	pinctrl-0 = <&pinctrl_flexcan1>;
7519435b53SHugo Villeneuve	status = "okay";
7619435b53SHugo Villeneuve};
7719435b53SHugo Villeneuve
7819435b53SHugo Villeneuve&i2c1 {
7919435b53SHugo Villeneuve	clock-frequency = <100000>;
8019435b53SHugo Villeneuve	pinctrl-names = "default";
8119435b53SHugo Villeneuve	pinctrl-0 = <&pinctrl_i2c1>;
8219435b53SHugo Villeneuve	status = "okay";
8319435b53SHugo Villeneuve
8419435b53SHugo Villeneuve	rtc@68 {
8519435b53SHugo Villeneuve		/*
8619435b53SHugo Villeneuve		 * To actually use this interrupt
8719435b53SHugo Villeneuve		 * connect pins J14.8 & J14.10 on the Concerto-Board.
8819435b53SHugo Villeneuve		 */
8919435b53SHugo Villeneuve		compatible = "dallas,ds1337";
9019435b53SHugo Villeneuve		reg = <0x68>;
9119435b53SHugo Villeneuve		pinctrl-names = "default";
9219435b53SHugo Villeneuve		pinctrl-0 = <&pinctrl_rtc>;
9319435b53SHugo Villeneuve		interrupt-parent = <&gpio1>;
9419435b53SHugo Villeneuve		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
9519435b53SHugo Villeneuve	};
9619435b53SHugo Villeneuve};
9719435b53SHugo Villeneuve
9819435b53SHugo Villeneuve&iomuxc {
9919435b53SHugo Villeneuve	pinctrl_flexcan1: flexcan1grp {
10019435b53SHugo Villeneuve		fsl,pins = <
10119435b53SHugo Villeneuve			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
10219435b53SHugo Villeneuve			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
10319435b53SHugo Villeneuve		>;
10419435b53SHugo Villeneuve	};
10519435b53SHugo Villeneuve
10619435b53SHugo Villeneuve	pinctrl_gpio_key_back: gpio-key-backgrp {
10719435b53SHugo Villeneuve		fsl,pins = <
10819435b53SHugo Villeneuve			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
10919435b53SHugo Villeneuve		>;
11019435b53SHugo Villeneuve	};
11119435b53SHugo Villeneuve
11219435b53SHugo Villeneuve	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
11319435b53SHugo Villeneuve		fsl,pins = <
11419435b53SHugo Villeneuve			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
11519435b53SHugo Villeneuve		>;
11619435b53SHugo Villeneuve	};
11719435b53SHugo Villeneuve
1180d2f2cd6SHugo Villeneuve	pinctrl_gpio_leds: gpio-ledsgrp {
1190d2f2cd6SHugo Villeneuve		fsl,pins = <
1200d2f2cd6SHugo Villeneuve			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
1210d2f2cd6SHugo Villeneuve		>;
1220d2f2cd6SHugo Villeneuve	};
1230d2f2cd6SHugo Villeneuve
12419435b53SHugo Villeneuve	pinctrl_rtc: rtcgrp {
12519435b53SHugo Villeneuve		fsl,pins = <
12619435b53SHugo Villeneuve			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
12719435b53SHugo Villeneuve		>;
12819435b53SHugo Villeneuve	};
12919435b53SHugo Villeneuve
13019435b53SHugo Villeneuve	pinctrl_uart1: uart1grp {
13119435b53SHugo Villeneuve		fsl,pins = <
13219435b53SHugo Villeneuve			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
13319435b53SHugo Villeneuve			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
13419435b53SHugo Villeneuve		>;
13519435b53SHugo Villeneuve	};
13619435b53SHugo Villeneuve
13719435b53SHugo Villeneuve	pinctrl_uart5: uart5grp {
13819435b53SHugo Villeneuve		fsl,pins = <
13919435b53SHugo Villeneuve			MX6UL_PAD_CSI_DATA00__UART5_DCE_TX	0x1b0b1
14019435b53SHugo Villeneuve			MX6UL_PAD_CSI_DATA01__UART5_DCE_RX	0x1b0b1
14119435b53SHugo Villeneuve			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
14219435b53SHugo Villeneuve			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
14319435b53SHugo Villeneuve		>;
14419435b53SHugo Villeneuve	};
14519435b53SHugo Villeneuve
14619435b53SHugo Villeneuve	pinctrl_usb_otg1_id: usbotg1idgrp {
14719435b53SHugo Villeneuve		fsl,pins = <
14819435b53SHugo Villeneuve			MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
14919435b53SHugo Villeneuve		>;
15019435b53SHugo Villeneuve	};
15119435b53SHugo Villeneuve
15219435b53SHugo Villeneuve	pinctrl_wdog: wdoggrp {
15319435b53SHugo Villeneuve		fsl,pins = <
15419435b53SHugo Villeneuve			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
15519435b53SHugo Villeneuve		>;
15619435b53SHugo Villeneuve	};
15719435b53SHugo Villeneuve};
15819435b53SHugo Villeneuve
15919435b53SHugo Villeneuve&snvs_pwrkey {
16019435b53SHugo Villeneuve	status = "disabled";
16119435b53SHugo Villeneuve};
16219435b53SHugo Villeneuve
16319435b53SHugo Villeneuve&snvs_rtc {
16419435b53SHugo Villeneuve	status = "disabled";
16519435b53SHugo Villeneuve};
16619435b53SHugo Villeneuve
16719435b53SHugo Villeneuve&tsc {
16819435b53SHugo Villeneuve	/*
16919435b53SHugo Villeneuve	 * Conflics with wdog1 ext-reset-output & SD CD pins,
17019435b53SHugo Villeneuve	 * so we keep it disabled by default.
17119435b53SHugo Villeneuve	 */
17219435b53SHugo Villeneuve	status = "disabled";
17319435b53SHugo Villeneuve};
17419435b53SHugo Villeneuve
17519435b53SHugo Villeneuve/* Console UART */
17619435b53SHugo Villeneuve&uart1 {
17719435b53SHugo Villeneuve	pinctrl-names = "default";
17819435b53SHugo Villeneuve	pinctrl-0 = <&pinctrl_uart1>;
17919435b53SHugo Villeneuve	status = "okay";
18019435b53SHugo Villeneuve};
18119435b53SHugo Villeneuve
18219435b53SHugo Villeneuve/* ttymxc4 UART */
18319435b53SHugo Villeneuve&uart5 {
18419435b53SHugo Villeneuve	pinctrl-names = "default";
18519435b53SHugo Villeneuve	pinctrl-0 = <&pinctrl_uart5>;
18619435b53SHugo Villeneuve	uart-has-rtscts;
18719435b53SHugo Villeneuve	status = "okay";
18819435b53SHugo Villeneuve};
18919435b53SHugo Villeneuve
19019435b53SHugo Villeneuve&usbotg1 {
19119435b53SHugo Villeneuve	pinctrl-names = "default";
19219435b53SHugo Villeneuve	pinctrl-0 = <&pinctrl_usb_otg1_id>;
19319435b53SHugo Villeneuve	dr_mode = "otg";
19419435b53SHugo Villeneuve	disable-over-current;
19519435b53SHugo Villeneuve	srp-disable;
19619435b53SHugo Villeneuve	hnp-disable;
19719435b53SHugo Villeneuve	adp-disable;
19819435b53SHugo Villeneuve	status = "okay";
19919435b53SHugo Villeneuve};
20019435b53SHugo Villeneuve
20119435b53SHugo Villeneuve&usbotg2 {
20219435b53SHugo Villeneuve	dr_mode = "host";
20319435b53SHugo Villeneuve	disable-over-current;
20419435b53SHugo Villeneuve	status = "okay";
20519435b53SHugo Villeneuve};
20619435b53SHugo Villeneuve
20719435b53SHugo Villeneuve&wdog1 {
20819435b53SHugo Villeneuve	pinctrl-names = "default";
20919435b53SHugo Villeneuve	pinctrl-0 = <&pinctrl_wdog>;
21019435b53SHugo Villeneuve	/*
21119435b53SHugo Villeneuve	 * To actually use ext-reset-output
21219435b53SHugo Villeneuve	 * connect pins J17.3 & J17.8 on the Concerto-Board
21319435b53SHugo Villeneuve	 */
21419435b53SHugo Villeneuve	fsl,ext-reset-output;
21519435b53SHugo Villeneuve};
216