1*5f173307SHugo Villeneuve// SPDX-License-Identifier: GPL-2.0+ 2*5f173307SHugo Villeneuve/* 3*5f173307SHugo Villeneuve * Audio support for Variscite VAR-SOM-6UL module. 4*5f173307SHugo Villeneuve * 5*5f173307SHugo Villeneuve * Copyright 2019-2024 Variscite Ltd. 6*5f173307SHugo Villeneuve * Copyright 2026 Dimonoff 7*5f173307SHugo Villeneuve */ 8*5f173307SHugo Villeneuve 9*5f173307SHugo Villeneuve&iomuxc { 10*5f173307SHugo Villeneuve pinctrl_sai2: sai2grp { 11*5f173307SHugo Villeneuve fsl,pins = < 12*5f173307SHugo Villeneuve MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 13*5f173307SHugo Villeneuve MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 14*5f173307SHugo Villeneuve MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 15*5f173307SHugo Villeneuve MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 16*5f173307SHugo Villeneuve MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 17*5f173307SHugo Villeneuve >; 18*5f173307SHugo Villeneuve }; 19*5f173307SHugo Villeneuve}; 20*5f173307SHugo Villeneuve 21*5f173307SHugo Villeneuve&sai2 { 22*5f173307SHugo Villeneuve pinctrl-names = "default"; 23*5f173307SHugo Villeneuve pinctrl-0 = <&pinctrl_sai2>; 24*5f173307SHugo Villeneuve assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 25*5f173307SHugo Villeneuve <&clks IMX6UL_CLK_SAI2>; 26*5f173307SHugo Villeneuve assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 27*5f173307SHugo Villeneuve assigned-clock-rates = <0>, <12288000>; 28*5f173307SHugo Villeneuve fsl,sai-mclk-direction-output; 29*5f173307SHugo Villeneuve status = "okay"; 30*5f173307SHugo Villeneuve}; 31